1 //===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "llvm/MC/MCDisassembler.h" 11 #include "MCTargetDesc/ARMAddressingModes.h" 12 #include "MCTargetDesc/ARMBaseInfo.h" 13 #include "MCTargetDesc/ARMMCExpr.h" 14 #include "llvm/MC/MCContext.h" 15 #include "llvm/MC/MCExpr.h" 16 #include "llvm/MC/MCFixedLenDisassembler.h" 17 #include "llvm/MC/MCInst.h" 18 #include "llvm/MC/MCInstrDesc.h" 19 #include "llvm/MC/MCSubtargetInfo.h" 20 #include "llvm/Support/Debug.h" 21 #include "llvm/Support/ErrorHandling.h" 22 #include "llvm/Support/LEB128.h" 23 #include "llvm/Support/TargetRegistry.h" 24 #include "llvm/Support/raw_ostream.h" 25 #include <vector> 26 27 using namespace llvm; 28 29 #define DEBUG_TYPE "arm-disassembler" 30 31 typedef MCDisassembler::DecodeStatus DecodeStatus; 32 33 namespace { 34 // Handles the condition code status of instructions in IT blocks 35 class ITStatus 36 { 37 public: 38 // Returns the condition code for instruction in IT block 39 unsigned getITCC() { 40 unsigned CC = ARMCC::AL; 41 if (instrInITBlock()) 42 CC = ITStates.back(); 43 return CC; 44 } 45 46 // Advances the IT block state to the next T or E 47 void advanceITState() { 48 ITStates.pop_back(); 49 } 50 51 // Returns true if the current instruction is in an IT block 52 bool instrInITBlock() { 53 return !ITStates.empty(); 54 } 55 56 // Returns true if current instruction is the last instruction in an IT block 57 bool instrLastInITBlock() { 58 return ITStates.size() == 1; 59 } 60 61 // Called when decoding an IT instruction. Sets the IT state for the following 62 // instructions that for the IT block. Firstcond and Mask correspond to the 63 // fields in the IT instruction encoding. 64 void setITState(char Firstcond, char Mask) { 65 // (3 - the number of trailing zeros) is the number of then / else. 66 unsigned CondBit0 = Firstcond & 1; 67 unsigned NumTZ = countTrailingZeros<uint8_t>(Mask); 68 unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf); 69 assert(NumTZ <= 3 && "Invalid IT mask!"); 70 // push condition codes onto the stack the correct order for the pops 71 for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) { 72 bool T = ((Mask >> Pos) & 1) == CondBit0; 73 if (T) 74 ITStates.push_back(CCBits); 75 else 76 ITStates.push_back(CCBits ^ 1); 77 } 78 ITStates.push_back(CCBits); 79 } 80 81 private: 82 std::vector<unsigned char> ITStates; 83 }; 84 } 85 86 namespace { 87 /// ARM disassembler for all ARM platforms. 88 class ARMDisassembler : public MCDisassembler { 89 public: 90 ARMDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 91 MCDisassembler(STI, Ctx) { 92 } 93 94 ~ARMDisassembler() {} 95 96 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 97 ArrayRef<uint8_t> Bytes, uint64_t Address, 98 raw_ostream &VStream, 99 raw_ostream &CStream) const override; 100 }; 101 102 /// Thumb disassembler for all Thumb platforms. 103 class ThumbDisassembler : public MCDisassembler { 104 public: 105 ThumbDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx) : 106 MCDisassembler(STI, Ctx) { 107 } 108 109 ~ThumbDisassembler() {} 110 111 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 112 ArrayRef<uint8_t> Bytes, uint64_t Address, 113 raw_ostream &VStream, 114 raw_ostream &CStream) const override; 115 116 private: 117 mutable ITStatus ITBlock; 118 DecodeStatus AddThumbPredicate(MCInst&) const; 119 void UpdateThumbVFPPredicate(MCInst&) const; 120 }; 121 } 122 123 static bool Check(DecodeStatus &Out, DecodeStatus In) { 124 switch (In) { 125 case MCDisassembler::Success: 126 // Out stays the same. 127 return true; 128 case MCDisassembler::SoftFail: 129 Out = In; 130 return true; 131 case MCDisassembler::Fail: 132 Out = In; 133 return false; 134 } 135 llvm_unreachable("Invalid DecodeStatus!"); 136 } 137 138 139 // Forward declare these because the autogenerated code will reference them. 140 // Definitions are further down. 141 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 142 uint64_t Address, const void *Decoder); 143 static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst, 144 unsigned RegNo, uint64_t Address, 145 const void *Decoder); 146 static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst, 147 unsigned RegNo, uint64_t Address, 148 const void *Decoder); 149 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 150 uint64_t Address, const void *Decoder); 151 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 152 uint64_t Address, const void *Decoder); 153 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 154 uint64_t Address, const void *Decoder); 155 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 156 uint64_t Address, const void *Decoder); 157 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 158 uint64_t Address, const void *Decoder); 159 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 160 uint64_t Address, const void *Decoder); 161 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 162 uint64_t Address, const void *Decoder); 163 static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst, 164 unsigned RegNo, 165 uint64_t Address, 166 const void *Decoder); 167 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 168 uint64_t Address, const void *Decoder); 169 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 170 uint64_t Address, const void *Decoder); 171 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 172 unsigned RegNo, uint64_t Address, 173 const void *Decoder); 174 175 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 176 uint64_t Address, const void *Decoder); 177 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 178 uint64_t Address, const void *Decoder); 179 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 180 uint64_t Address, const void *Decoder); 181 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 182 uint64_t Address, const void *Decoder); 183 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 184 uint64_t Address, const void *Decoder); 185 186 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn, 187 uint64_t Address, const void *Decoder); 188 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 189 uint64_t Address, const void *Decoder); 190 static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst, 191 unsigned Insn, 192 uint64_t Address, 193 const void *Decoder); 194 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn, 195 uint64_t Address, const void *Decoder); 196 static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn, 197 uint64_t Address, const void *Decoder); 198 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn, 199 uint64_t Address, const void *Decoder); 200 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn, 201 uint64_t Address, const void *Decoder); 202 203 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst, 204 unsigned Insn, 205 uint64_t Adddress, 206 const void *Decoder); 207 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 208 uint64_t Address, const void *Decoder); 209 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 210 uint64_t Address, const void *Decoder); 211 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 212 uint64_t Address, const void *Decoder); 213 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 214 uint64_t Address, const void *Decoder); 215 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 216 uint64_t Address, const void *Decoder); 217 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 218 uint64_t Address, const void *Decoder); 219 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 220 uint64_t Address, const void *Decoder); 221 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 222 uint64_t Address, const void *Decoder); 223 static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 224 uint64_t Address, const void *Decoder); 225 static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn, 226 uint64_t Address, const void *Decoder); 227 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 228 uint64_t Address, const void *Decoder); 229 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val, 230 uint64_t Address, const void *Decoder); 231 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val, 232 uint64_t Address, const void *Decoder); 233 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val, 234 uint64_t Address, const void *Decoder); 235 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val, 236 uint64_t Address, const void *Decoder); 237 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val, 238 uint64_t Address, const void *Decoder); 239 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val, 240 uint64_t Address, const void *Decoder); 241 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val, 242 uint64_t Address, const void *Decoder); 243 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val, 244 uint64_t Address, const void *Decoder); 245 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val, 246 uint64_t Address, const void *Decoder); 247 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val, 248 uint64_t Address, const void *Decoder); 249 static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val, 250 uint64_t Address, const void *Decoder); 251 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val, 252 uint64_t Address, const void *Decoder); 253 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 254 uint64_t Address, const void *Decoder); 255 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 256 uint64_t Address, const void *Decoder); 257 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 258 uint64_t Address, const void *Decoder); 259 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 260 uint64_t Address, const void *Decoder); 261 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 262 uint64_t Address, const void *Decoder); 263 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 264 uint64_t Address, const void *Decoder); 265 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn, 266 uint64_t Address, const void *Decoder); 267 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn, 268 uint64_t Address, const void *Decoder); 269 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn, 270 uint64_t Address, const void *Decoder); 271 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn, 272 uint64_t Address, const void *Decoder); 273 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Insn, 274 uint64_t Address, const void *Decoder); 275 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 276 uint64_t Address, const void *Decoder); 277 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 278 uint64_t Address, const void *Decoder); 279 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 280 uint64_t Address, const void *Decoder); 281 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 282 uint64_t Address, const void *Decoder); 283 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 284 uint64_t Address, const void *Decoder); 285 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 286 uint64_t Address, const void *Decoder); 287 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 288 uint64_t Address, const void *Decoder); 289 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 290 uint64_t Address, const void *Decoder); 291 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 292 uint64_t Address, const void *Decoder); 293 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 294 uint64_t Address, const void *Decoder); 295 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 296 uint64_t Address, const void *Decoder); 297 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 298 uint64_t Address, const void *Decoder); 299 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 300 uint64_t Address, const void *Decoder); 301 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 302 uint64_t Address, const void *Decoder); 303 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 304 uint64_t Address, const void *Decoder); 305 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 306 uint64_t Address, const void *Decoder); 307 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 308 uint64_t Address, const void *Decoder); 309 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 310 uint64_t Address, const void *Decoder); 311 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 312 uint64_t Address, const void *Decoder); 313 314 315 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 316 uint64_t Address, const void *Decoder); 317 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 318 uint64_t Address, const void *Decoder); 319 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 320 uint64_t Address, const void *Decoder); 321 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 322 uint64_t Address, const void *Decoder); 323 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 324 uint64_t Address, const void *Decoder); 325 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 326 uint64_t Address, const void *Decoder); 327 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 328 uint64_t Address, const void *Decoder); 329 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 330 uint64_t Address, const void *Decoder); 331 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 332 uint64_t Address, const void *Decoder); 333 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val, 334 uint64_t Address, const void *Decoder); 335 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 336 uint64_t Address, const void* Decoder); 337 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 338 uint64_t Address, const void* Decoder); 339 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 340 uint64_t Address, const void* Decoder); 341 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 342 uint64_t Address, const void* Decoder); 343 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 344 uint64_t Address, const void *Decoder); 345 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 346 uint64_t Address, const void *Decoder); 347 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 348 uint64_t Address, const void *Decoder); 349 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 350 uint64_t Address, const void *Decoder); 351 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 352 uint64_t Address, const void *Decoder); 353 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val, 354 uint64_t Address, const void *Decoder); 355 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 356 uint64_t Address, const void *Decoder); 357 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 358 uint64_t Address, const void *Decoder); 359 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 360 uint64_t Address, const void *Decoder); 361 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn, 362 uint64_t Address, const void *Decoder); 363 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 364 uint64_t Address, const void *Decoder); 365 static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val, 366 uint64_t Address, const void *Decoder); 367 static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val, 368 uint64_t Address, const void *Decoder); 369 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 370 uint64_t Address, const void *Decoder); 371 static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val, 372 uint64_t Address, const void *Decoder); 373 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 374 uint64_t Address, const void *Decoder); 375 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val, 376 uint64_t Address, const void *Decoder); 377 static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn, 378 uint64_t Address, const void *Decoder); 379 static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn, 380 uint64_t Address, const void *Decoder); 381 static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val, 382 uint64_t Address, const void *Decoder); 383 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val, 384 uint64_t Address, const void *Decoder); 385 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val, 386 uint64_t Address, const void *Decoder); 387 388 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 389 uint64_t Address, const void *Decoder); 390 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 391 uint64_t Address, const void *Decoder); 392 #include "ARMGenDisassemblerTables.inc" 393 394 static MCDisassembler *createARMDisassembler(const Target &T, 395 const MCSubtargetInfo &STI, 396 MCContext &Ctx) { 397 return new ARMDisassembler(STI, Ctx); 398 } 399 400 static MCDisassembler *createThumbDisassembler(const Target &T, 401 const MCSubtargetInfo &STI, 402 MCContext &Ctx) { 403 return new ThumbDisassembler(STI, Ctx); 404 } 405 406 // Post-decoding checks 407 static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size, 408 uint64_t Address, raw_ostream &OS, 409 raw_ostream &CS, 410 uint32_t Insn, 411 DecodeStatus Result) 412 { 413 switch (MI.getOpcode()) { 414 case ARM::HVC: { 415 // HVC is undefined if condition = 0xf otherwise upredictable 416 // if condition != 0xe 417 uint32_t Cond = (Insn >> 28) & 0xF; 418 if (Cond == 0xF) 419 return MCDisassembler::Fail; 420 if (Cond != 0xE) 421 return MCDisassembler::SoftFail; 422 return Result; 423 } 424 default: return Result; 425 } 426 } 427 428 DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 429 ArrayRef<uint8_t> Bytes, 430 uint64_t Address, raw_ostream &OS, 431 raw_ostream &CS) const { 432 CommentStream = &CS; 433 434 assert(!(STI.getFeatureBits() & ARM::ModeThumb) && 435 "Asked to disassemble an ARM instruction but Subtarget is in Thumb " 436 "mode!"); 437 438 // We want to read exactly 4 bytes of data. 439 if (Bytes.size() < 4) { 440 Size = 0; 441 return MCDisassembler::Fail; 442 } 443 444 // Encoded as a small-endian 32-bit word in the stream. 445 uint32_t Insn = 446 (Bytes[3] << 24) | (Bytes[2] << 16) | (Bytes[1] << 8) | (Bytes[0] << 0); 447 448 // Calling the auto-generated decoder function. 449 DecodeStatus Result = 450 decodeInstruction(DecoderTableARM32, MI, Insn, Address, this, STI); 451 if (Result != MCDisassembler::Fail) { 452 Size = 4; 453 return checkDecodedInstruction(MI, Size, Address, OS, CS, Insn, Result); 454 } 455 456 // VFP and NEON instructions, similarly, are shared between ARM 457 // and Thumb modes. 458 MI.clear(); 459 Result = decodeInstruction(DecoderTableVFP32, MI, Insn, Address, this, STI); 460 if (Result != MCDisassembler::Fail) { 461 Size = 4; 462 return Result; 463 } 464 465 MI.clear(); 466 Result = decodeInstruction(DecoderTableVFPV832, MI, Insn, Address, this, STI); 467 if (Result != MCDisassembler::Fail) { 468 Size = 4; 469 return Result; 470 } 471 472 MI.clear(); 473 Result = 474 decodeInstruction(DecoderTableNEONData32, MI, Insn, Address, this, STI); 475 if (Result != MCDisassembler::Fail) { 476 Size = 4; 477 // Add a fake predicate operand, because we share these instruction 478 // definitions with Thumb2 where these instructions are predicable. 479 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 480 return MCDisassembler::Fail; 481 return Result; 482 } 483 484 MI.clear(); 485 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, Insn, Address, 486 this, STI); 487 if (Result != MCDisassembler::Fail) { 488 Size = 4; 489 // Add a fake predicate operand, because we share these instruction 490 // definitions with Thumb2 where these instructions are predicable. 491 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 492 return MCDisassembler::Fail; 493 return Result; 494 } 495 496 MI.clear(); 497 Result = 498 decodeInstruction(DecoderTableNEONDup32, MI, Insn, Address, this, STI); 499 if (Result != MCDisassembler::Fail) { 500 Size = 4; 501 // Add a fake predicate operand, because we share these instruction 502 // definitions with Thumb2 where these instructions are predicable. 503 if (!DecodePredicateOperand(MI, 0xE, Address, this)) 504 return MCDisassembler::Fail; 505 return Result; 506 } 507 508 MI.clear(); 509 Result = 510 decodeInstruction(DecoderTablev8NEON32, MI, Insn, Address, this, STI); 511 if (Result != MCDisassembler::Fail) { 512 Size = 4; 513 return Result; 514 } 515 516 MI.clear(); 517 Result = 518 decodeInstruction(DecoderTablev8Crypto32, MI, Insn, Address, this, STI); 519 if (Result != MCDisassembler::Fail) { 520 Size = 4; 521 return Result; 522 } 523 524 MI.clear(); 525 Size = 0; 526 return MCDisassembler::Fail; 527 } 528 529 namespace llvm { 530 extern const MCInstrDesc ARMInsts[]; 531 } 532 533 /// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the 534 /// immediate Value in the MCInst. The immediate Value has had any PC 535 /// adjustment made by the caller. If the instruction is a branch instruction 536 /// then isBranch is true, else false. If the getOpInfo() function was set as 537 /// part of the setupForSymbolicDisassembly() call then that function is called 538 /// to get any symbolic information at the Address for this instruction. If 539 /// that returns non-zero then the symbolic information it returns is used to 540 /// create an MCExpr and that is added as an operand to the MCInst. If 541 /// getOpInfo() returns zero and isBranch is true then a symbol look up for 542 /// Value is done and if a symbol is found an MCExpr is created with that, else 543 /// an MCExpr with Value is created. This function returns true if it adds an 544 /// operand to the MCInst and false otherwise. 545 static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value, 546 bool isBranch, uint64_t InstSize, 547 MCInst &MI, const void *Decoder) { 548 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 549 // FIXME: Does it make sense for value to be negative? 550 return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch, 551 /* Offset */ 0, InstSize); 552 } 553 554 /// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being 555 /// referenced by a load instruction with the base register that is the Pc. 556 /// These can often be values in a literal pool near the Address of the 557 /// instruction. The Address of the instruction and its immediate Value are 558 /// used as a possible literal pool entry. The SymbolLookUp call back will 559 /// return the name of a symbol referenced by the literal pool's entry if 560 /// the referenced address is that of a symbol. Or it will return a pointer to 561 /// a literal 'C' string if the referenced address of the literal pool's entry 562 /// is an address into a section with 'C' string literals. 563 static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value, 564 const void *Decoder) { 565 const MCDisassembler *Dis = static_cast<const MCDisassembler*>(Decoder); 566 Dis->tryAddingPcLoadReferenceComment(Value, Address); 567 } 568 569 // Thumb1 instructions don't have explicit S bits. Rather, they 570 // implicitly set CPSR. Since it's not represented in the encoding, the 571 // auto-generated decoder won't inject the CPSR operand. We need to fix 572 // that as a post-pass. 573 static void AddThumb1SBit(MCInst &MI, bool InITBlock) { 574 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 575 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 576 MCInst::iterator I = MI.begin(); 577 for (unsigned i = 0; i < NumOps; ++i, ++I) { 578 if (I == MI.end()) break; 579 if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) { 580 if (i > 0 && OpInfo[i-1].isPredicate()) continue; 581 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 582 return; 583 } 584 } 585 586 MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR)); 587 } 588 589 // Most Thumb instructions don't have explicit predicates in the 590 // encoding, but rather get their predicates from IT context. We need 591 // to fix up the predicate operands using this context information as a 592 // post-pass. 593 MCDisassembler::DecodeStatus 594 ThumbDisassembler::AddThumbPredicate(MCInst &MI) const { 595 MCDisassembler::DecodeStatus S = Success; 596 597 // A few instructions actually have predicates encoded in them. Don't 598 // try to overwrite it if we're seeing one of those. 599 switch (MI.getOpcode()) { 600 case ARM::tBcc: 601 case ARM::t2Bcc: 602 case ARM::tCBZ: 603 case ARM::tCBNZ: 604 case ARM::tCPS: 605 case ARM::t2CPS3p: 606 case ARM::t2CPS2p: 607 case ARM::t2CPS1p: 608 case ARM::tMOVSr: 609 case ARM::tSETEND: 610 // Some instructions (mostly conditional branches) are not 611 // allowed in IT blocks. 612 if (ITBlock.instrInITBlock()) 613 S = SoftFail; 614 else 615 return Success; 616 break; 617 case ARM::tB: 618 case ARM::t2B: 619 case ARM::t2TBB: 620 case ARM::t2TBH: 621 // Some instructions (mostly unconditional branches) can 622 // only appears at the end of, or outside of, an IT. 623 if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock()) 624 S = SoftFail; 625 break; 626 default: 627 break; 628 } 629 630 // If we're in an IT block, base the predicate on that. Otherwise, 631 // assume a predicate of AL. 632 unsigned CC; 633 CC = ITBlock.getITCC(); 634 if (CC == 0xF) 635 CC = ARMCC::AL; 636 if (ITBlock.instrInITBlock()) 637 ITBlock.advanceITState(); 638 639 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 640 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 641 MCInst::iterator I = MI.begin(); 642 for (unsigned i = 0; i < NumOps; ++i, ++I) { 643 if (I == MI.end()) break; 644 if (OpInfo[i].isPredicate()) { 645 I = MI.insert(I, MCOperand::CreateImm(CC)); 646 ++I; 647 if (CC == ARMCC::AL) 648 MI.insert(I, MCOperand::CreateReg(0)); 649 else 650 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 651 return S; 652 } 653 } 654 655 I = MI.insert(I, MCOperand::CreateImm(CC)); 656 ++I; 657 if (CC == ARMCC::AL) 658 MI.insert(I, MCOperand::CreateReg(0)); 659 else 660 MI.insert(I, MCOperand::CreateReg(ARM::CPSR)); 661 662 return S; 663 } 664 665 // Thumb VFP instructions are a special case. Because we share their 666 // encodings between ARM and Thumb modes, and they are predicable in ARM 667 // mode, the auto-generated decoder will give them an (incorrect) 668 // predicate operand. We need to rewrite these operands based on the IT 669 // context as a post-pass. 670 void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const { 671 unsigned CC; 672 CC = ITBlock.getITCC(); 673 if (ITBlock.instrInITBlock()) 674 ITBlock.advanceITState(); 675 676 const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo; 677 MCInst::iterator I = MI.begin(); 678 unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands; 679 for (unsigned i = 0; i < NumOps; ++i, ++I) { 680 if (OpInfo[i].isPredicate() ) { 681 I->setImm(CC); 682 ++I; 683 if (CC == ARMCC::AL) 684 I->setReg(0); 685 else 686 I->setReg(ARM::CPSR); 687 return; 688 } 689 } 690 } 691 692 DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 693 ArrayRef<uint8_t> Bytes, 694 uint64_t Address, 695 raw_ostream &OS, 696 raw_ostream &CS) const { 697 CommentStream = &CS; 698 699 assert((STI.getFeatureBits() & ARM::ModeThumb) && 700 "Asked to disassemble in Thumb mode but Subtarget is in ARM mode!"); 701 702 // We want to read exactly 2 bytes of data. 703 if (Bytes.size() < 2) { 704 Size = 0; 705 return MCDisassembler::Fail; 706 } 707 708 uint16_t Insn16 = (Bytes[1] << 8) | Bytes[0]; 709 DecodeStatus Result = 710 decodeInstruction(DecoderTableThumb16, MI, Insn16, Address, this, STI); 711 if (Result != MCDisassembler::Fail) { 712 Size = 2; 713 Check(Result, AddThumbPredicate(MI)); 714 return Result; 715 } 716 717 MI.clear(); 718 Result = decodeInstruction(DecoderTableThumbSBit16, MI, Insn16, Address, this, 719 STI); 720 if (Result) { 721 Size = 2; 722 bool InITBlock = ITBlock.instrInITBlock(); 723 Check(Result, AddThumbPredicate(MI)); 724 AddThumb1SBit(MI, InITBlock); 725 return Result; 726 } 727 728 MI.clear(); 729 Result = 730 decodeInstruction(DecoderTableThumb216, MI, Insn16, Address, this, STI); 731 if (Result != MCDisassembler::Fail) { 732 Size = 2; 733 734 // Nested IT blocks are UNPREDICTABLE. Must be checked before we add 735 // the Thumb predicate. 736 if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock()) 737 Result = MCDisassembler::SoftFail; 738 739 Check(Result, AddThumbPredicate(MI)); 740 741 // If we find an IT instruction, we need to parse its condition 742 // code and mask operands so that we can apply them correctly 743 // to the subsequent instructions. 744 if (MI.getOpcode() == ARM::t2IT) { 745 746 unsigned Firstcond = MI.getOperand(0).getImm(); 747 unsigned Mask = MI.getOperand(1).getImm(); 748 ITBlock.setITState(Firstcond, Mask); 749 } 750 751 return Result; 752 } 753 754 // We want to read exactly 4 bytes of data. 755 if (Bytes.size() < 4) { 756 Size = 0; 757 return MCDisassembler::Fail; 758 } 759 760 uint32_t Insn32 = 761 (Bytes[3] << 8) | (Bytes[2] << 0) | (Bytes[1] << 24) | (Bytes[0] << 16); 762 MI.clear(); 763 Result = 764 decodeInstruction(DecoderTableThumb32, MI, Insn32, Address, this, STI); 765 if (Result != MCDisassembler::Fail) { 766 Size = 4; 767 bool InITBlock = ITBlock.instrInITBlock(); 768 Check(Result, AddThumbPredicate(MI)); 769 AddThumb1SBit(MI, InITBlock); 770 return Result; 771 } 772 773 MI.clear(); 774 Result = 775 decodeInstruction(DecoderTableThumb232, MI, Insn32, Address, this, STI); 776 if (Result != MCDisassembler::Fail) { 777 Size = 4; 778 Check(Result, AddThumbPredicate(MI)); 779 return Result; 780 } 781 782 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 783 MI.clear(); 784 Result = 785 decodeInstruction(DecoderTableVFP32, MI, Insn32, Address, this, STI); 786 if (Result != MCDisassembler::Fail) { 787 Size = 4; 788 UpdateThumbVFPPredicate(MI); 789 return Result; 790 } 791 } 792 793 MI.clear(); 794 Result = 795 decodeInstruction(DecoderTableVFPV832, MI, Insn32, Address, this, STI); 796 if (Result != MCDisassembler::Fail) { 797 Size = 4; 798 return Result; 799 } 800 801 if (fieldFromInstruction(Insn32, 28, 4) == 0xE) { 802 MI.clear(); 803 Result = decodeInstruction(DecoderTableNEONDup32, MI, Insn32, Address, this, 804 STI); 805 if (Result != MCDisassembler::Fail) { 806 Size = 4; 807 Check(Result, AddThumbPredicate(MI)); 808 return Result; 809 } 810 } 811 812 if (fieldFromInstruction(Insn32, 24, 8) == 0xF9) { 813 MI.clear(); 814 uint32_t NEONLdStInsn = Insn32; 815 NEONLdStInsn &= 0xF0FFFFFF; 816 NEONLdStInsn |= 0x04000000; 817 Result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn, 818 Address, this, STI); 819 if (Result != MCDisassembler::Fail) { 820 Size = 4; 821 Check(Result, AddThumbPredicate(MI)); 822 return Result; 823 } 824 } 825 826 if (fieldFromInstruction(Insn32, 24, 4) == 0xF) { 827 MI.clear(); 828 uint32_t NEONDataInsn = Insn32; 829 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24 830 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 831 NEONDataInsn |= 0x12000000; // Set bits 28 and 25 832 Result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn, 833 Address, this, STI); 834 if (Result != MCDisassembler::Fail) { 835 Size = 4; 836 Check(Result, AddThumbPredicate(MI)); 837 return Result; 838 } 839 840 MI.clear(); 841 uint32_t NEONCryptoInsn = Insn32; 842 NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24 843 NEONCryptoInsn |= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24 844 NEONCryptoInsn |= 0x12000000; // Set bits 28 and 25 845 Result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn, 846 Address, this, STI); 847 if (Result != MCDisassembler::Fail) { 848 Size = 4; 849 return Result; 850 } 851 852 MI.clear(); 853 uint32_t NEONv8Insn = Insn32; 854 NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26 855 Result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address, 856 this, STI); 857 if (Result != MCDisassembler::Fail) { 858 Size = 4; 859 return Result; 860 } 861 } 862 863 MI.clear(); 864 Size = 0; 865 return MCDisassembler::Fail; 866 } 867 868 869 extern "C" void LLVMInitializeARMDisassembler() { 870 TargetRegistry::RegisterMCDisassembler(TheARMLETarget, 871 createARMDisassembler); 872 TargetRegistry::RegisterMCDisassembler(TheARMBETarget, 873 createARMDisassembler); 874 TargetRegistry::RegisterMCDisassembler(TheThumbLETarget, 875 createThumbDisassembler); 876 TargetRegistry::RegisterMCDisassembler(TheThumbBETarget, 877 createThumbDisassembler); 878 } 879 880 static const uint16_t GPRDecoderTable[] = { 881 ARM::R0, ARM::R1, ARM::R2, ARM::R3, 882 ARM::R4, ARM::R5, ARM::R6, ARM::R7, 883 ARM::R8, ARM::R9, ARM::R10, ARM::R11, 884 ARM::R12, ARM::SP, ARM::LR, ARM::PC 885 }; 886 887 static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo, 888 uint64_t Address, const void *Decoder) { 889 if (RegNo > 15) 890 return MCDisassembler::Fail; 891 892 unsigned Register = GPRDecoderTable[RegNo]; 893 Inst.addOperand(MCOperand::CreateReg(Register)); 894 return MCDisassembler::Success; 895 } 896 897 static DecodeStatus 898 DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo, 899 uint64_t Address, const void *Decoder) { 900 DecodeStatus S = MCDisassembler::Success; 901 902 if (RegNo == 15) 903 S = MCDisassembler::SoftFail; 904 905 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 906 907 return S; 908 } 909 910 static DecodeStatus 911 DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo, 912 uint64_t Address, const void *Decoder) { 913 DecodeStatus S = MCDisassembler::Success; 914 915 if (RegNo == 15) 916 { 917 Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV)); 918 return MCDisassembler::Success; 919 } 920 921 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 922 return S; 923 } 924 925 static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo, 926 uint64_t Address, const void *Decoder) { 927 if (RegNo > 7) 928 return MCDisassembler::Fail; 929 return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder); 930 } 931 932 static const uint16_t GPRPairDecoderTable[] = { 933 ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7, 934 ARM::R8_R9, ARM::R10_R11, ARM::R12_SP 935 }; 936 937 static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo, 938 uint64_t Address, const void *Decoder) { 939 DecodeStatus S = MCDisassembler::Success; 940 941 if (RegNo > 13) 942 return MCDisassembler::Fail; 943 944 if ((RegNo & 1) || RegNo == 0xe) 945 S = MCDisassembler::SoftFail; 946 947 unsigned RegisterPair = GPRPairDecoderTable[RegNo/2]; 948 Inst.addOperand(MCOperand::CreateReg(RegisterPair)); 949 return S; 950 } 951 952 static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo, 953 uint64_t Address, const void *Decoder) { 954 unsigned Register = 0; 955 switch (RegNo) { 956 case 0: 957 Register = ARM::R0; 958 break; 959 case 1: 960 Register = ARM::R1; 961 break; 962 case 2: 963 Register = ARM::R2; 964 break; 965 case 3: 966 Register = ARM::R3; 967 break; 968 case 9: 969 Register = ARM::R9; 970 break; 971 case 12: 972 Register = ARM::R12; 973 break; 974 default: 975 return MCDisassembler::Fail; 976 } 977 978 Inst.addOperand(MCOperand::CreateReg(Register)); 979 return MCDisassembler::Success; 980 } 981 982 static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo, 983 uint64_t Address, const void *Decoder) { 984 DecodeStatus S = MCDisassembler::Success; 985 if (RegNo == 13 || RegNo == 15) 986 S = MCDisassembler::SoftFail; 987 Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder)); 988 return S; 989 } 990 991 static const uint16_t SPRDecoderTable[] = { 992 ARM::S0, ARM::S1, ARM::S2, ARM::S3, 993 ARM::S4, ARM::S5, ARM::S6, ARM::S7, 994 ARM::S8, ARM::S9, ARM::S10, ARM::S11, 995 ARM::S12, ARM::S13, ARM::S14, ARM::S15, 996 ARM::S16, ARM::S17, ARM::S18, ARM::S19, 997 ARM::S20, ARM::S21, ARM::S22, ARM::S23, 998 ARM::S24, ARM::S25, ARM::S26, ARM::S27, 999 ARM::S28, ARM::S29, ARM::S30, ARM::S31 1000 }; 1001 1002 static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo, 1003 uint64_t Address, const void *Decoder) { 1004 if (RegNo > 31) 1005 return MCDisassembler::Fail; 1006 1007 unsigned Register = SPRDecoderTable[RegNo]; 1008 Inst.addOperand(MCOperand::CreateReg(Register)); 1009 return MCDisassembler::Success; 1010 } 1011 1012 static const uint16_t DPRDecoderTable[] = { 1013 ARM::D0, ARM::D1, ARM::D2, ARM::D3, 1014 ARM::D4, ARM::D5, ARM::D6, ARM::D7, 1015 ARM::D8, ARM::D9, ARM::D10, ARM::D11, 1016 ARM::D12, ARM::D13, ARM::D14, ARM::D15, 1017 ARM::D16, ARM::D17, ARM::D18, ARM::D19, 1018 ARM::D20, ARM::D21, ARM::D22, ARM::D23, 1019 ARM::D24, ARM::D25, ARM::D26, ARM::D27, 1020 ARM::D28, ARM::D29, ARM::D30, ARM::D31 1021 }; 1022 1023 static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo, 1024 uint64_t Address, const void *Decoder) { 1025 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() 1026 .getFeatureBits(); 1027 bool hasD16 = featureBits & ARM::FeatureD16; 1028 1029 if (RegNo > 31 || (hasD16 && RegNo > 15)) 1030 return MCDisassembler::Fail; 1031 1032 unsigned Register = DPRDecoderTable[RegNo]; 1033 Inst.addOperand(MCOperand::CreateReg(Register)); 1034 return MCDisassembler::Success; 1035 } 1036 1037 static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo, 1038 uint64_t Address, const void *Decoder) { 1039 if (RegNo > 7) 1040 return MCDisassembler::Fail; 1041 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1042 } 1043 1044 static DecodeStatus 1045 DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo, 1046 uint64_t Address, const void *Decoder) { 1047 if (RegNo > 15) 1048 return MCDisassembler::Fail; 1049 return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder); 1050 } 1051 1052 static const uint16_t QPRDecoderTable[] = { 1053 ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3, 1054 ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7, 1055 ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11, 1056 ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15 1057 }; 1058 1059 1060 static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo, 1061 uint64_t Address, const void *Decoder) { 1062 if (RegNo > 31 || (RegNo & 1) != 0) 1063 return MCDisassembler::Fail; 1064 RegNo >>= 1; 1065 1066 unsigned Register = QPRDecoderTable[RegNo]; 1067 Inst.addOperand(MCOperand::CreateReg(Register)); 1068 return MCDisassembler::Success; 1069 } 1070 1071 static const uint16_t DPairDecoderTable[] = { 1072 ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6, 1073 ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12, 1074 ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18, 1075 ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24, 1076 ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30, 1077 ARM::Q15 1078 }; 1079 1080 static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo, 1081 uint64_t Address, const void *Decoder) { 1082 if (RegNo > 30) 1083 return MCDisassembler::Fail; 1084 1085 unsigned Register = DPairDecoderTable[RegNo]; 1086 Inst.addOperand(MCOperand::CreateReg(Register)); 1087 return MCDisassembler::Success; 1088 } 1089 1090 static const uint16_t DPairSpacedDecoderTable[] = { 1091 ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5, 1092 ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9, 1093 ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13, 1094 ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17, 1095 ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21, 1096 ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25, 1097 ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29, 1098 ARM::D28_D30, ARM::D29_D31 1099 }; 1100 1101 static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst, 1102 unsigned RegNo, 1103 uint64_t Address, 1104 const void *Decoder) { 1105 if (RegNo > 29) 1106 return MCDisassembler::Fail; 1107 1108 unsigned Register = DPairSpacedDecoderTable[RegNo]; 1109 Inst.addOperand(MCOperand::CreateReg(Register)); 1110 return MCDisassembler::Success; 1111 } 1112 1113 static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val, 1114 uint64_t Address, const void *Decoder) { 1115 if (Val == 0xF) return MCDisassembler::Fail; 1116 // AL predicate is not allowed on Thumb1 branches. 1117 if (Inst.getOpcode() == ARM::tBcc && Val == 0xE) 1118 return MCDisassembler::Fail; 1119 Inst.addOperand(MCOperand::CreateImm(Val)); 1120 if (Val == ARMCC::AL) { 1121 Inst.addOperand(MCOperand::CreateReg(0)); 1122 } else 1123 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1124 return MCDisassembler::Success; 1125 } 1126 1127 static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val, 1128 uint64_t Address, const void *Decoder) { 1129 if (Val) 1130 Inst.addOperand(MCOperand::CreateReg(ARM::CPSR)); 1131 else 1132 Inst.addOperand(MCOperand::CreateReg(0)); 1133 return MCDisassembler::Success; 1134 } 1135 1136 static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val, 1137 uint64_t Address, const void *Decoder) { 1138 DecodeStatus S = MCDisassembler::Success; 1139 1140 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1141 unsigned type = fieldFromInstruction(Val, 5, 2); 1142 unsigned imm = fieldFromInstruction(Val, 7, 5); 1143 1144 // Register-immediate 1145 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1146 return MCDisassembler::Fail; 1147 1148 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1149 switch (type) { 1150 case 0: 1151 Shift = ARM_AM::lsl; 1152 break; 1153 case 1: 1154 Shift = ARM_AM::lsr; 1155 break; 1156 case 2: 1157 Shift = ARM_AM::asr; 1158 break; 1159 case 3: 1160 Shift = ARM_AM::ror; 1161 break; 1162 } 1163 1164 if (Shift == ARM_AM::ror && imm == 0) 1165 Shift = ARM_AM::rrx; 1166 1167 unsigned Op = Shift | (imm << 3); 1168 Inst.addOperand(MCOperand::CreateImm(Op)); 1169 1170 return S; 1171 } 1172 1173 static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val, 1174 uint64_t Address, const void *Decoder) { 1175 DecodeStatus S = MCDisassembler::Success; 1176 1177 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1178 unsigned type = fieldFromInstruction(Val, 5, 2); 1179 unsigned Rs = fieldFromInstruction(Val, 8, 4); 1180 1181 // Register-register 1182 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1183 return MCDisassembler::Fail; 1184 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder))) 1185 return MCDisassembler::Fail; 1186 1187 ARM_AM::ShiftOpc Shift = ARM_AM::lsl; 1188 switch (type) { 1189 case 0: 1190 Shift = ARM_AM::lsl; 1191 break; 1192 case 1: 1193 Shift = ARM_AM::lsr; 1194 break; 1195 case 2: 1196 Shift = ARM_AM::asr; 1197 break; 1198 case 3: 1199 Shift = ARM_AM::ror; 1200 break; 1201 } 1202 1203 Inst.addOperand(MCOperand::CreateImm(Shift)); 1204 1205 return S; 1206 } 1207 1208 static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val, 1209 uint64_t Address, const void *Decoder) { 1210 DecodeStatus S = MCDisassembler::Success; 1211 1212 bool NeedDisjointWriteback = false; 1213 unsigned WritebackReg = 0; 1214 switch (Inst.getOpcode()) { 1215 default: 1216 break; 1217 case ARM::LDMIA_UPD: 1218 case ARM::LDMDB_UPD: 1219 case ARM::LDMIB_UPD: 1220 case ARM::LDMDA_UPD: 1221 case ARM::t2LDMIA_UPD: 1222 case ARM::t2LDMDB_UPD: 1223 case ARM::t2STMIA_UPD: 1224 case ARM::t2STMDB_UPD: 1225 NeedDisjointWriteback = true; 1226 WritebackReg = Inst.getOperand(0).getReg(); 1227 break; 1228 } 1229 1230 // Empty register lists are not allowed. 1231 if (Val == 0) return MCDisassembler::Fail; 1232 for (unsigned i = 0; i < 16; ++i) { 1233 if (Val & (1 << i)) { 1234 if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder))) 1235 return MCDisassembler::Fail; 1236 // Writeback not allowed if Rn is in the target list. 1237 if (NeedDisjointWriteback && WritebackReg == Inst.end()[-1].getReg()) 1238 Check(S, MCDisassembler::SoftFail); 1239 } 1240 } 1241 1242 return S; 1243 } 1244 1245 static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val, 1246 uint64_t Address, const void *Decoder) { 1247 DecodeStatus S = MCDisassembler::Success; 1248 1249 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1250 unsigned regs = fieldFromInstruction(Val, 0, 8); 1251 1252 // In case of unpredictable encoding, tweak the operands. 1253 if (regs == 0 || (Vd + regs) > 32) { 1254 regs = Vd + regs > 32 ? 32 - Vd : regs; 1255 regs = std::max( 1u, regs); 1256 S = MCDisassembler::SoftFail; 1257 } 1258 1259 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) 1260 return MCDisassembler::Fail; 1261 for (unsigned i = 0; i < (regs - 1); ++i) { 1262 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1263 return MCDisassembler::Fail; 1264 } 1265 1266 return S; 1267 } 1268 1269 static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val, 1270 uint64_t Address, const void *Decoder) { 1271 DecodeStatus S = MCDisassembler::Success; 1272 1273 unsigned Vd = fieldFromInstruction(Val, 8, 5); 1274 unsigned regs = fieldFromInstruction(Val, 1, 7); 1275 1276 // In case of unpredictable encoding, tweak the operands. 1277 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { 1278 regs = Vd + regs > 32 ? 32 - Vd : regs; 1279 regs = std::max( 1u, regs); 1280 regs = std::min(16u, regs); 1281 S = MCDisassembler::SoftFail; 1282 } 1283 1284 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 1285 return MCDisassembler::Fail; 1286 for (unsigned i = 0; i < (regs - 1); ++i) { 1287 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) 1288 return MCDisassembler::Fail; 1289 } 1290 1291 return S; 1292 } 1293 1294 static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val, 1295 uint64_t Address, const void *Decoder) { 1296 // This operand encodes a mask of contiguous zeros between a specified MSB 1297 // and LSB. To decode it, we create the mask of all bits MSB-and-lower, 1298 // the mask of all bits LSB-and-lower, and then xor them to create 1299 // the mask of that's all ones on [msb, lsb]. Finally we not it to 1300 // create the final mask. 1301 unsigned msb = fieldFromInstruction(Val, 5, 5); 1302 unsigned lsb = fieldFromInstruction(Val, 0, 5); 1303 1304 DecodeStatus S = MCDisassembler::Success; 1305 if (lsb > msb) { 1306 Check(S, MCDisassembler::SoftFail); 1307 // The check above will cause the warning for the "potentially undefined 1308 // instruction encoding" but we can't build a bad MCOperand value here 1309 // with a lsb > msb or else printing the MCInst will cause a crash. 1310 lsb = msb; 1311 } 1312 1313 uint32_t msb_mask = 0xFFFFFFFF; 1314 if (msb != 31) msb_mask = (1U << (msb+1)) - 1; 1315 uint32_t lsb_mask = (1U << lsb) - 1; 1316 1317 Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask))); 1318 return S; 1319 } 1320 1321 static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn, 1322 uint64_t Address, const void *Decoder) { 1323 DecodeStatus S = MCDisassembler::Success; 1324 1325 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1326 unsigned CRd = fieldFromInstruction(Insn, 12, 4); 1327 unsigned coproc = fieldFromInstruction(Insn, 8, 4); 1328 unsigned imm = fieldFromInstruction(Insn, 0, 8); 1329 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1330 unsigned U = fieldFromInstruction(Insn, 23, 1); 1331 1332 switch (Inst.getOpcode()) { 1333 case ARM::LDC_OFFSET: 1334 case ARM::LDC_PRE: 1335 case ARM::LDC_POST: 1336 case ARM::LDC_OPTION: 1337 case ARM::LDCL_OFFSET: 1338 case ARM::LDCL_PRE: 1339 case ARM::LDCL_POST: 1340 case ARM::LDCL_OPTION: 1341 case ARM::STC_OFFSET: 1342 case ARM::STC_PRE: 1343 case ARM::STC_POST: 1344 case ARM::STC_OPTION: 1345 case ARM::STCL_OFFSET: 1346 case ARM::STCL_PRE: 1347 case ARM::STCL_POST: 1348 case ARM::STCL_OPTION: 1349 case ARM::t2LDC_OFFSET: 1350 case ARM::t2LDC_PRE: 1351 case ARM::t2LDC_POST: 1352 case ARM::t2LDC_OPTION: 1353 case ARM::t2LDCL_OFFSET: 1354 case ARM::t2LDCL_PRE: 1355 case ARM::t2LDCL_POST: 1356 case ARM::t2LDCL_OPTION: 1357 case ARM::t2STC_OFFSET: 1358 case ARM::t2STC_PRE: 1359 case ARM::t2STC_POST: 1360 case ARM::t2STC_OPTION: 1361 case ARM::t2STCL_OFFSET: 1362 case ARM::t2STCL_PRE: 1363 case ARM::t2STCL_POST: 1364 case ARM::t2STCL_OPTION: 1365 if (coproc == 0xA || coproc == 0xB) 1366 return MCDisassembler::Fail; 1367 break; 1368 default: 1369 break; 1370 } 1371 1372 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() 1373 .getFeatureBits(); 1374 if ((featureBits & ARM::HasV8Ops) && (coproc != 14)) 1375 return MCDisassembler::Fail; 1376 1377 Inst.addOperand(MCOperand::CreateImm(coproc)); 1378 Inst.addOperand(MCOperand::CreateImm(CRd)); 1379 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1380 return MCDisassembler::Fail; 1381 1382 switch (Inst.getOpcode()) { 1383 case ARM::t2LDC2_OFFSET: 1384 case ARM::t2LDC2L_OFFSET: 1385 case ARM::t2LDC2_PRE: 1386 case ARM::t2LDC2L_PRE: 1387 case ARM::t2STC2_OFFSET: 1388 case ARM::t2STC2L_OFFSET: 1389 case ARM::t2STC2_PRE: 1390 case ARM::t2STC2L_PRE: 1391 case ARM::LDC2_OFFSET: 1392 case ARM::LDC2L_OFFSET: 1393 case ARM::LDC2_PRE: 1394 case ARM::LDC2L_PRE: 1395 case ARM::STC2_OFFSET: 1396 case ARM::STC2L_OFFSET: 1397 case ARM::STC2_PRE: 1398 case ARM::STC2L_PRE: 1399 case ARM::t2LDC_OFFSET: 1400 case ARM::t2LDCL_OFFSET: 1401 case ARM::t2LDC_PRE: 1402 case ARM::t2LDCL_PRE: 1403 case ARM::t2STC_OFFSET: 1404 case ARM::t2STCL_OFFSET: 1405 case ARM::t2STC_PRE: 1406 case ARM::t2STCL_PRE: 1407 case ARM::LDC_OFFSET: 1408 case ARM::LDCL_OFFSET: 1409 case ARM::LDC_PRE: 1410 case ARM::LDCL_PRE: 1411 case ARM::STC_OFFSET: 1412 case ARM::STCL_OFFSET: 1413 case ARM::STC_PRE: 1414 case ARM::STCL_PRE: 1415 imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm); 1416 Inst.addOperand(MCOperand::CreateImm(imm)); 1417 break; 1418 case ARM::t2LDC2_POST: 1419 case ARM::t2LDC2L_POST: 1420 case ARM::t2STC2_POST: 1421 case ARM::t2STC2L_POST: 1422 case ARM::LDC2_POST: 1423 case ARM::LDC2L_POST: 1424 case ARM::STC2_POST: 1425 case ARM::STC2L_POST: 1426 case ARM::t2LDC_POST: 1427 case ARM::t2LDCL_POST: 1428 case ARM::t2STC_POST: 1429 case ARM::t2STCL_POST: 1430 case ARM::LDC_POST: 1431 case ARM::LDCL_POST: 1432 case ARM::STC_POST: 1433 case ARM::STCL_POST: 1434 imm |= U << 8; 1435 // fall through. 1436 default: 1437 // The 'option' variant doesn't encode 'U' in the immediate since 1438 // the immediate is unsigned [0,255]. 1439 Inst.addOperand(MCOperand::CreateImm(imm)); 1440 break; 1441 } 1442 1443 switch (Inst.getOpcode()) { 1444 case ARM::LDC_OFFSET: 1445 case ARM::LDC_PRE: 1446 case ARM::LDC_POST: 1447 case ARM::LDC_OPTION: 1448 case ARM::LDCL_OFFSET: 1449 case ARM::LDCL_PRE: 1450 case ARM::LDCL_POST: 1451 case ARM::LDCL_OPTION: 1452 case ARM::STC_OFFSET: 1453 case ARM::STC_PRE: 1454 case ARM::STC_POST: 1455 case ARM::STC_OPTION: 1456 case ARM::STCL_OFFSET: 1457 case ARM::STCL_PRE: 1458 case ARM::STCL_POST: 1459 case ARM::STCL_OPTION: 1460 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1461 return MCDisassembler::Fail; 1462 break; 1463 default: 1464 break; 1465 } 1466 1467 return S; 1468 } 1469 1470 static DecodeStatus 1471 DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn, 1472 uint64_t Address, const void *Decoder) { 1473 DecodeStatus S = MCDisassembler::Success; 1474 1475 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1476 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1477 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1478 unsigned imm = fieldFromInstruction(Insn, 0, 12); 1479 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1480 unsigned reg = fieldFromInstruction(Insn, 25, 1); 1481 unsigned P = fieldFromInstruction(Insn, 24, 1); 1482 unsigned W = fieldFromInstruction(Insn, 21, 1); 1483 1484 // On stores, the writeback operand precedes Rt. 1485 switch (Inst.getOpcode()) { 1486 case ARM::STR_POST_IMM: 1487 case ARM::STR_POST_REG: 1488 case ARM::STRB_POST_IMM: 1489 case ARM::STRB_POST_REG: 1490 case ARM::STRT_POST_REG: 1491 case ARM::STRT_POST_IMM: 1492 case ARM::STRBT_POST_REG: 1493 case ARM::STRBT_POST_IMM: 1494 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1495 return MCDisassembler::Fail; 1496 break; 1497 default: 1498 break; 1499 } 1500 1501 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1502 return MCDisassembler::Fail; 1503 1504 // On loads, the writeback operand comes after Rt. 1505 switch (Inst.getOpcode()) { 1506 case ARM::LDR_POST_IMM: 1507 case ARM::LDR_POST_REG: 1508 case ARM::LDRB_POST_IMM: 1509 case ARM::LDRB_POST_REG: 1510 case ARM::LDRBT_POST_REG: 1511 case ARM::LDRBT_POST_IMM: 1512 case ARM::LDRT_POST_REG: 1513 case ARM::LDRT_POST_IMM: 1514 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1515 return MCDisassembler::Fail; 1516 break; 1517 default: 1518 break; 1519 } 1520 1521 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1522 return MCDisassembler::Fail; 1523 1524 ARM_AM::AddrOpc Op = ARM_AM::add; 1525 if (!fieldFromInstruction(Insn, 23, 1)) 1526 Op = ARM_AM::sub; 1527 1528 bool writeback = (P == 0) || (W == 1); 1529 unsigned idx_mode = 0; 1530 if (P && writeback) 1531 idx_mode = ARMII::IndexModePre; 1532 else if (!P && writeback) 1533 idx_mode = ARMII::IndexModePost; 1534 1535 if (writeback && (Rn == 15 || Rn == Rt)) 1536 S = MCDisassembler::SoftFail; // UNPREDICTABLE 1537 1538 if (reg) { 1539 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1540 return MCDisassembler::Fail; 1541 ARM_AM::ShiftOpc Opc = ARM_AM::lsl; 1542 switch( fieldFromInstruction(Insn, 5, 2)) { 1543 case 0: 1544 Opc = ARM_AM::lsl; 1545 break; 1546 case 1: 1547 Opc = ARM_AM::lsr; 1548 break; 1549 case 2: 1550 Opc = ARM_AM::asr; 1551 break; 1552 case 3: 1553 Opc = ARM_AM::ror; 1554 break; 1555 default: 1556 return MCDisassembler::Fail; 1557 } 1558 unsigned amt = fieldFromInstruction(Insn, 7, 5); 1559 if (Opc == ARM_AM::ror && amt == 0) 1560 Opc = ARM_AM::rrx; 1561 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode); 1562 1563 Inst.addOperand(MCOperand::CreateImm(imm)); 1564 } else { 1565 Inst.addOperand(MCOperand::CreateReg(0)); 1566 unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode); 1567 Inst.addOperand(MCOperand::CreateImm(tmp)); 1568 } 1569 1570 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1571 return MCDisassembler::Fail; 1572 1573 return S; 1574 } 1575 1576 static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val, 1577 uint64_t Address, const void *Decoder) { 1578 DecodeStatus S = MCDisassembler::Success; 1579 1580 unsigned Rn = fieldFromInstruction(Val, 13, 4); 1581 unsigned Rm = fieldFromInstruction(Val, 0, 4); 1582 unsigned type = fieldFromInstruction(Val, 5, 2); 1583 unsigned imm = fieldFromInstruction(Val, 7, 5); 1584 unsigned U = fieldFromInstruction(Val, 12, 1); 1585 1586 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl; 1587 switch (type) { 1588 case 0: 1589 ShOp = ARM_AM::lsl; 1590 break; 1591 case 1: 1592 ShOp = ARM_AM::lsr; 1593 break; 1594 case 2: 1595 ShOp = ARM_AM::asr; 1596 break; 1597 case 3: 1598 ShOp = ARM_AM::ror; 1599 break; 1600 } 1601 1602 if (ShOp == ARM_AM::ror && imm == 0) 1603 ShOp = ARM_AM::rrx; 1604 1605 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1606 return MCDisassembler::Fail; 1607 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1608 return MCDisassembler::Fail; 1609 unsigned shift; 1610 if (U) 1611 shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp); 1612 else 1613 shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp); 1614 Inst.addOperand(MCOperand::CreateImm(shift)); 1615 1616 return S; 1617 } 1618 1619 static DecodeStatus 1620 DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn, 1621 uint64_t Address, const void *Decoder) { 1622 DecodeStatus S = MCDisassembler::Success; 1623 1624 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 1625 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1626 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1627 unsigned type = fieldFromInstruction(Insn, 22, 1); 1628 unsigned imm = fieldFromInstruction(Insn, 8, 4); 1629 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8; 1630 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1631 unsigned W = fieldFromInstruction(Insn, 21, 1); 1632 unsigned P = fieldFromInstruction(Insn, 24, 1); 1633 unsigned Rt2 = Rt + 1; 1634 1635 bool writeback = (W == 1) | (P == 0); 1636 1637 // For {LD,ST}RD, Rt must be even, else undefined. 1638 switch (Inst.getOpcode()) { 1639 case ARM::STRD: 1640 case ARM::STRD_PRE: 1641 case ARM::STRD_POST: 1642 case ARM::LDRD: 1643 case ARM::LDRD_PRE: 1644 case ARM::LDRD_POST: 1645 if (Rt & 0x1) S = MCDisassembler::SoftFail; 1646 break; 1647 default: 1648 break; 1649 } 1650 switch (Inst.getOpcode()) { 1651 case ARM::STRD: 1652 case ARM::STRD_PRE: 1653 case ARM::STRD_POST: 1654 if (P == 0 && W == 1) 1655 S = MCDisassembler::SoftFail; 1656 1657 if (writeback && (Rn == 15 || Rn == Rt || Rn == Rt2)) 1658 S = MCDisassembler::SoftFail; 1659 if (type && Rm == 15) 1660 S = MCDisassembler::SoftFail; 1661 if (Rt2 == 15) 1662 S = MCDisassembler::SoftFail; 1663 if (!type && fieldFromInstruction(Insn, 8, 4)) 1664 S = MCDisassembler::SoftFail; 1665 break; 1666 case ARM::STRH: 1667 case ARM::STRH_PRE: 1668 case ARM::STRH_POST: 1669 if (Rt == 15) 1670 S = MCDisassembler::SoftFail; 1671 if (writeback && (Rn == 15 || Rn == Rt)) 1672 S = MCDisassembler::SoftFail; 1673 if (!type && Rm == 15) 1674 S = MCDisassembler::SoftFail; 1675 break; 1676 case ARM::LDRD: 1677 case ARM::LDRD_PRE: 1678 case ARM::LDRD_POST: 1679 if (type && Rn == 15){ 1680 if (Rt2 == 15) 1681 S = MCDisassembler::SoftFail; 1682 break; 1683 } 1684 if (P == 0 && W == 1) 1685 S = MCDisassembler::SoftFail; 1686 if (!type && (Rt2 == 15 || Rm == 15 || Rm == Rt || Rm == Rt2)) 1687 S = MCDisassembler::SoftFail; 1688 if (!type && writeback && Rn == 15) 1689 S = MCDisassembler::SoftFail; 1690 if (writeback && (Rn == Rt || Rn == Rt2)) 1691 S = MCDisassembler::SoftFail; 1692 break; 1693 case ARM::LDRH: 1694 case ARM::LDRH_PRE: 1695 case ARM::LDRH_POST: 1696 if (type && Rn == 15){ 1697 if (Rt == 15) 1698 S = MCDisassembler::SoftFail; 1699 break; 1700 } 1701 if (Rt == 15) 1702 S = MCDisassembler::SoftFail; 1703 if (!type && Rm == 15) 1704 S = MCDisassembler::SoftFail; 1705 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1706 S = MCDisassembler::SoftFail; 1707 break; 1708 case ARM::LDRSH: 1709 case ARM::LDRSH_PRE: 1710 case ARM::LDRSH_POST: 1711 case ARM::LDRSB: 1712 case ARM::LDRSB_PRE: 1713 case ARM::LDRSB_POST: 1714 if (type && Rn == 15){ 1715 if (Rt == 15) 1716 S = MCDisassembler::SoftFail; 1717 break; 1718 } 1719 if (type && (Rt == 15 || (writeback && Rn == Rt))) 1720 S = MCDisassembler::SoftFail; 1721 if (!type && (Rt == 15 || Rm == 15)) 1722 S = MCDisassembler::SoftFail; 1723 if (!type && writeback && (Rn == 15 || Rn == Rt)) 1724 S = MCDisassembler::SoftFail; 1725 break; 1726 default: 1727 break; 1728 } 1729 1730 if (writeback) { // Writeback 1731 if (P) 1732 U |= ARMII::IndexModePre << 9; 1733 else 1734 U |= ARMII::IndexModePost << 9; 1735 1736 // On stores, the writeback operand precedes Rt. 1737 switch (Inst.getOpcode()) { 1738 case ARM::STRD: 1739 case ARM::STRD_PRE: 1740 case ARM::STRD_POST: 1741 case ARM::STRH: 1742 case ARM::STRH_PRE: 1743 case ARM::STRH_POST: 1744 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1745 return MCDisassembler::Fail; 1746 break; 1747 default: 1748 break; 1749 } 1750 } 1751 1752 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 1753 return MCDisassembler::Fail; 1754 switch (Inst.getOpcode()) { 1755 case ARM::STRD: 1756 case ARM::STRD_PRE: 1757 case ARM::STRD_POST: 1758 case ARM::LDRD: 1759 case ARM::LDRD_PRE: 1760 case ARM::LDRD_POST: 1761 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder))) 1762 return MCDisassembler::Fail; 1763 break; 1764 default: 1765 break; 1766 } 1767 1768 if (writeback) { 1769 // On loads, the writeback operand comes after Rt. 1770 switch (Inst.getOpcode()) { 1771 case ARM::LDRD: 1772 case ARM::LDRD_PRE: 1773 case ARM::LDRD_POST: 1774 case ARM::LDRH: 1775 case ARM::LDRH_PRE: 1776 case ARM::LDRH_POST: 1777 case ARM::LDRSH: 1778 case ARM::LDRSH_PRE: 1779 case ARM::LDRSH_POST: 1780 case ARM::LDRSB: 1781 case ARM::LDRSB_PRE: 1782 case ARM::LDRSB_POST: 1783 case ARM::LDRHTr: 1784 case ARM::LDRSBTr: 1785 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1786 return MCDisassembler::Fail; 1787 break; 1788 default: 1789 break; 1790 } 1791 } 1792 1793 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1794 return MCDisassembler::Fail; 1795 1796 if (type) { 1797 Inst.addOperand(MCOperand::CreateReg(0)); 1798 Inst.addOperand(MCOperand::CreateImm(U | (imm << 4) | Rm)); 1799 } else { 1800 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 1801 return MCDisassembler::Fail; 1802 Inst.addOperand(MCOperand::CreateImm(U)); 1803 } 1804 1805 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1806 return MCDisassembler::Fail; 1807 1808 return S; 1809 } 1810 1811 static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn, 1812 uint64_t Address, const void *Decoder) { 1813 DecodeStatus S = MCDisassembler::Success; 1814 1815 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1816 unsigned mode = fieldFromInstruction(Insn, 23, 2); 1817 1818 switch (mode) { 1819 case 0: 1820 mode = ARM_AM::da; 1821 break; 1822 case 1: 1823 mode = ARM_AM::ia; 1824 break; 1825 case 2: 1826 mode = ARM_AM::db; 1827 break; 1828 case 3: 1829 mode = ARM_AM::ib; 1830 break; 1831 } 1832 1833 Inst.addOperand(MCOperand::CreateImm(mode)); 1834 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1835 return MCDisassembler::Fail; 1836 1837 return S; 1838 } 1839 1840 static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn, 1841 uint64_t Address, const void *Decoder) { 1842 DecodeStatus S = MCDisassembler::Success; 1843 1844 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 1845 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 1846 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1847 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1848 1849 if (pred == 0xF) 1850 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 1851 1852 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 1853 return MCDisassembler::Fail; 1854 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 1855 return MCDisassembler::Fail; 1856 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 1857 return MCDisassembler::Fail; 1858 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1859 return MCDisassembler::Fail; 1860 return S; 1861 } 1862 1863 static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst, 1864 unsigned Insn, 1865 uint64_t Address, const void *Decoder) { 1866 DecodeStatus S = MCDisassembler::Success; 1867 1868 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 1869 unsigned pred = fieldFromInstruction(Insn, 28, 4); 1870 unsigned reglist = fieldFromInstruction(Insn, 0, 16); 1871 1872 if (pred == 0xF) { 1873 // Ambiguous with RFE and SRS 1874 switch (Inst.getOpcode()) { 1875 case ARM::LDMDA: 1876 Inst.setOpcode(ARM::RFEDA); 1877 break; 1878 case ARM::LDMDA_UPD: 1879 Inst.setOpcode(ARM::RFEDA_UPD); 1880 break; 1881 case ARM::LDMDB: 1882 Inst.setOpcode(ARM::RFEDB); 1883 break; 1884 case ARM::LDMDB_UPD: 1885 Inst.setOpcode(ARM::RFEDB_UPD); 1886 break; 1887 case ARM::LDMIA: 1888 Inst.setOpcode(ARM::RFEIA); 1889 break; 1890 case ARM::LDMIA_UPD: 1891 Inst.setOpcode(ARM::RFEIA_UPD); 1892 break; 1893 case ARM::LDMIB: 1894 Inst.setOpcode(ARM::RFEIB); 1895 break; 1896 case ARM::LDMIB_UPD: 1897 Inst.setOpcode(ARM::RFEIB_UPD); 1898 break; 1899 case ARM::STMDA: 1900 Inst.setOpcode(ARM::SRSDA); 1901 break; 1902 case ARM::STMDA_UPD: 1903 Inst.setOpcode(ARM::SRSDA_UPD); 1904 break; 1905 case ARM::STMDB: 1906 Inst.setOpcode(ARM::SRSDB); 1907 break; 1908 case ARM::STMDB_UPD: 1909 Inst.setOpcode(ARM::SRSDB_UPD); 1910 break; 1911 case ARM::STMIA: 1912 Inst.setOpcode(ARM::SRSIA); 1913 break; 1914 case ARM::STMIA_UPD: 1915 Inst.setOpcode(ARM::SRSIA_UPD); 1916 break; 1917 case ARM::STMIB: 1918 Inst.setOpcode(ARM::SRSIB); 1919 break; 1920 case ARM::STMIB_UPD: 1921 Inst.setOpcode(ARM::SRSIB_UPD); 1922 break; 1923 default: 1924 return MCDisassembler::Fail; 1925 } 1926 1927 // For stores (which become SRS's, the only operand is the mode. 1928 if (fieldFromInstruction(Insn, 20, 1) == 0) { 1929 // Check SRS encoding constraints 1930 if (!(fieldFromInstruction(Insn, 22, 1) == 1 && 1931 fieldFromInstruction(Insn, 20, 1) == 0)) 1932 return MCDisassembler::Fail; 1933 1934 Inst.addOperand( 1935 MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4))); 1936 return S; 1937 } 1938 1939 return DecodeRFEInstruction(Inst, Insn, Address, Decoder); 1940 } 1941 1942 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1943 return MCDisassembler::Fail; 1944 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 1945 return MCDisassembler::Fail; // Tied 1946 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 1947 return MCDisassembler::Fail; 1948 if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder))) 1949 return MCDisassembler::Fail; 1950 1951 return S; 1952 } 1953 1954 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn, 1955 uint64_t Address, const void *Decoder) { 1956 unsigned imod = fieldFromInstruction(Insn, 18, 2); 1957 unsigned M = fieldFromInstruction(Insn, 17, 1); 1958 unsigned iflags = fieldFromInstruction(Insn, 6, 3); 1959 unsigned mode = fieldFromInstruction(Insn, 0, 5); 1960 1961 DecodeStatus S = MCDisassembler::Success; 1962 1963 // This decoder is called from multiple location that do not check 1964 // the full encoding is valid before they do. 1965 if (fieldFromInstruction(Insn, 5, 1) != 0 || 1966 fieldFromInstruction(Insn, 16, 1) != 0 || 1967 fieldFromInstruction(Insn, 20, 8) != 0x10) 1968 return MCDisassembler::Fail; 1969 1970 // imod == '01' --> UNPREDICTABLE 1971 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 1972 // return failure here. The '01' imod value is unprintable, so there's 1973 // nothing useful we could do even if we returned UNPREDICTABLE. 1974 1975 if (imod == 1) return MCDisassembler::Fail; 1976 1977 if (imod && M) { 1978 Inst.setOpcode(ARM::CPS3p); 1979 Inst.addOperand(MCOperand::CreateImm(imod)); 1980 Inst.addOperand(MCOperand::CreateImm(iflags)); 1981 Inst.addOperand(MCOperand::CreateImm(mode)); 1982 } else if (imod && !M) { 1983 Inst.setOpcode(ARM::CPS2p); 1984 Inst.addOperand(MCOperand::CreateImm(imod)); 1985 Inst.addOperand(MCOperand::CreateImm(iflags)); 1986 if (mode) S = MCDisassembler::SoftFail; 1987 } else if (!imod && M) { 1988 Inst.setOpcode(ARM::CPS1p); 1989 Inst.addOperand(MCOperand::CreateImm(mode)); 1990 if (iflags) S = MCDisassembler::SoftFail; 1991 } else { 1992 // imod == '00' && M == '0' --> UNPREDICTABLE 1993 Inst.setOpcode(ARM::CPS1p); 1994 Inst.addOperand(MCOperand::CreateImm(mode)); 1995 S = MCDisassembler::SoftFail; 1996 } 1997 1998 return S; 1999 } 2000 2001 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn, 2002 uint64_t Address, const void *Decoder) { 2003 unsigned imod = fieldFromInstruction(Insn, 9, 2); 2004 unsigned M = fieldFromInstruction(Insn, 8, 1); 2005 unsigned iflags = fieldFromInstruction(Insn, 5, 3); 2006 unsigned mode = fieldFromInstruction(Insn, 0, 5); 2007 2008 DecodeStatus S = MCDisassembler::Success; 2009 2010 // imod == '01' --> UNPREDICTABLE 2011 // NOTE: Even though this is technically UNPREDICTABLE, we choose to 2012 // return failure here. The '01' imod value is unprintable, so there's 2013 // nothing useful we could do even if we returned UNPREDICTABLE. 2014 2015 if (imod == 1) return MCDisassembler::Fail; 2016 2017 if (imod && M) { 2018 Inst.setOpcode(ARM::t2CPS3p); 2019 Inst.addOperand(MCOperand::CreateImm(imod)); 2020 Inst.addOperand(MCOperand::CreateImm(iflags)); 2021 Inst.addOperand(MCOperand::CreateImm(mode)); 2022 } else if (imod && !M) { 2023 Inst.setOpcode(ARM::t2CPS2p); 2024 Inst.addOperand(MCOperand::CreateImm(imod)); 2025 Inst.addOperand(MCOperand::CreateImm(iflags)); 2026 if (mode) S = MCDisassembler::SoftFail; 2027 } else if (!imod && M) { 2028 Inst.setOpcode(ARM::t2CPS1p); 2029 Inst.addOperand(MCOperand::CreateImm(mode)); 2030 if (iflags) S = MCDisassembler::SoftFail; 2031 } else { 2032 // imod == '00' && M == '0' --> this is a HINT instruction 2033 int imm = fieldFromInstruction(Insn, 0, 8); 2034 // HINT are defined only for immediate in [0..4] 2035 if(imm > 4) return MCDisassembler::Fail; 2036 Inst.setOpcode(ARM::t2HINT); 2037 Inst.addOperand(MCOperand::CreateImm(imm)); 2038 } 2039 2040 return S; 2041 } 2042 2043 static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn, 2044 uint64_t Address, const void *Decoder) { 2045 DecodeStatus S = MCDisassembler::Success; 2046 2047 unsigned Rd = fieldFromInstruction(Insn, 8, 4); 2048 unsigned imm = 0; 2049 2050 imm |= (fieldFromInstruction(Insn, 0, 8) << 0); 2051 imm |= (fieldFromInstruction(Insn, 12, 3) << 8); 2052 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2053 imm |= (fieldFromInstruction(Insn, 26, 1) << 11); 2054 2055 if (Inst.getOpcode() == ARM::t2MOVTi16) 2056 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2057 return MCDisassembler::Fail; 2058 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder))) 2059 return MCDisassembler::Fail; 2060 2061 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2062 Inst.addOperand(MCOperand::CreateImm(imm)); 2063 2064 return S; 2065 } 2066 2067 static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn, 2068 uint64_t Address, const void *Decoder) { 2069 DecodeStatus S = MCDisassembler::Success; 2070 2071 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2072 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2073 unsigned imm = 0; 2074 2075 imm |= (fieldFromInstruction(Insn, 0, 12) << 0); 2076 imm |= (fieldFromInstruction(Insn, 16, 4) << 12); 2077 2078 if (Inst.getOpcode() == ARM::MOVTi16) 2079 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2080 return MCDisassembler::Fail; 2081 2082 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2083 return MCDisassembler::Fail; 2084 2085 if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder)) 2086 Inst.addOperand(MCOperand::CreateImm(imm)); 2087 2088 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2089 return MCDisassembler::Fail; 2090 2091 return S; 2092 } 2093 2094 static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn, 2095 uint64_t Address, const void *Decoder) { 2096 DecodeStatus S = MCDisassembler::Success; 2097 2098 unsigned Rd = fieldFromInstruction(Insn, 16, 4); 2099 unsigned Rn = fieldFromInstruction(Insn, 0, 4); 2100 unsigned Rm = fieldFromInstruction(Insn, 8, 4); 2101 unsigned Ra = fieldFromInstruction(Insn, 12, 4); 2102 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2103 2104 if (pred == 0xF) 2105 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 2106 2107 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 2108 return MCDisassembler::Fail; 2109 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 2110 return MCDisassembler::Fail; 2111 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 2112 return MCDisassembler::Fail; 2113 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder))) 2114 return MCDisassembler::Fail; 2115 2116 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2117 return MCDisassembler::Fail; 2118 2119 return S; 2120 } 2121 2122 static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val, 2123 uint64_t Address, const void *Decoder) { 2124 DecodeStatus S = MCDisassembler::Success; 2125 2126 unsigned add = fieldFromInstruction(Val, 12, 1); 2127 unsigned imm = fieldFromInstruction(Val, 0, 12); 2128 unsigned Rn = fieldFromInstruction(Val, 13, 4); 2129 2130 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2131 return MCDisassembler::Fail; 2132 2133 if (!add) imm *= -1; 2134 if (imm == 0 && !add) imm = INT32_MIN; 2135 Inst.addOperand(MCOperand::CreateImm(imm)); 2136 if (Rn == 15) 2137 tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder); 2138 2139 return S; 2140 } 2141 2142 static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val, 2143 uint64_t Address, const void *Decoder) { 2144 DecodeStatus S = MCDisassembler::Success; 2145 2146 unsigned Rn = fieldFromInstruction(Val, 9, 4); 2147 unsigned U = fieldFromInstruction(Val, 8, 1); 2148 unsigned imm = fieldFromInstruction(Val, 0, 8); 2149 2150 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2151 return MCDisassembler::Fail; 2152 2153 if (U) 2154 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm))); 2155 else 2156 Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm))); 2157 2158 return S; 2159 } 2160 2161 static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val, 2162 uint64_t Address, const void *Decoder) { 2163 return DecodeGPRRegisterClass(Inst, Val, Address, Decoder); 2164 } 2165 2166 static DecodeStatus 2167 DecodeT2BInstruction(MCInst &Inst, unsigned Insn, 2168 uint64_t Address, const void *Decoder) { 2169 DecodeStatus Status = MCDisassembler::Success; 2170 2171 // Note the J1 and J2 values are from the encoded instruction. So here 2172 // change them to I1 and I2 values via as documented: 2173 // I1 = NOT(J1 EOR S); 2174 // I2 = NOT(J2 EOR S); 2175 // and build the imm32 with one trailing zero as documented: 2176 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 2177 unsigned S = fieldFromInstruction(Insn, 26, 1); 2178 unsigned J1 = fieldFromInstruction(Insn, 13, 1); 2179 unsigned J2 = fieldFromInstruction(Insn, 11, 1); 2180 unsigned I1 = !(J1 ^ S); 2181 unsigned I2 = !(J2 ^ S); 2182 unsigned imm10 = fieldFromInstruction(Insn, 16, 10); 2183 unsigned imm11 = fieldFromInstruction(Insn, 0, 11); 2184 unsigned tmp = (S << 23) | (I1 << 22) | (I2 << 21) | (imm10 << 11) | imm11; 2185 int imm32 = SignExtend32<25>(tmp << 1); 2186 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 2187 true, 4, Inst, Decoder)) 2188 Inst.addOperand(MCOperand::CreateImm(imm32)); 2189 2190 return Status; 2191 } 2192 2193 static DecodeStatus 2194 DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn, 2195 uint64_t Address, const void *Decoder) { 2196 DecodeStatus S = MCDisassembler::Success; 2197 2198 unsigned pred = fieldFromInstruction(Insn, 28, 4); 2199 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2; 2200 2201 if (pred == 0xF) { 2202 Inst.setOpcode(ARM::BLXi); 2203 imm |= fieldFromInstruction(Insn, 24, 1) << 1; 2204 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2205 true, 4, Inst, Decoder)) 2206 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2207 return S; 2208 } 2209 2210 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8, 2211 true, 4, Inst, Decoder)) 2212 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm))); 2213 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 2214 return MCDisassembler::Fail; 2215 2216 return S; 2217 } 2218 2219 2220 static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val, 2221 uint64_t Address, const void *Decoder) { 2222 DecodeStatus S = MCDisassembler::Success; 2223 2224 unsigned Rm = fieldFromInstruction(Val, 0, 4); 2225 unsigned align = fieldFromInstruction(Val, 4, 2); 2226 2227 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2228 return MCDisassembler::Fail; 2229 if (!align) 2230 Inst.addOperand(MCOperand::CreateImm(0)); 2231 else 2232 Inst.addOperand(MCOperand::CreateImm(4 << align)); 2233 2234 return S; 2235 } 2236 2237 static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn, 2238 uint64_t Address, const void *Decoder) { 2239 DecodeStatus S = MCDisassembler::Success; 2240 2241 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2242 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2243 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2244 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2245 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2246 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2247 2248 // First output register 2249 switch (Inst.getOpcode()) { 2250 case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8: 2251 case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register: 2252 case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register: 2253 case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register: 2254 case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register: 2255 case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8: 2256 case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register: 2257 case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register: 2258 case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register: 2259 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2260 return MCDisassembler::Fail; 2261 break; 2262 case ARM::VLD2b16: 2263 case ARM::VLD2b32: 2264 case ARM::VLD2b8: 2265 case ARM::VLD2b16wb_fixed: 2266 case ARM::VLD2b16wb_register: 2267 case ARM::VLD2b32wb_fixed: 2268 case ARM::VLD2b32wb_register: 2269 case ARM::VLD2b8wb_fixed: 2270 case ARM::VLD2b8wb_register: 2271 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2272 return MCDisassembler::Fail; 2273 break; 2274 default: 2275 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2276 return MCDisassembler::Fail; 2277 } 2278 2279 // Second output register 2280 switch (Inst.getOpcode()) { 2281 case ARM::VLD3d8: 2282 case ARM::VLD3d16: 2283 case ARM::VLD3d32: 2284 case ARM::VLD3d8_UPD: 2285 case ARM::VLD3d16_UPD: 2286 case ARM::VLD3d32_UPD: 2287 case ARM::VLD4d8: 2288 case ARM::VLD4d16: 2289 case ARM::VLD4d32: 2290 case ARM::VLD4d8_UPD: 2291 case ARM::VLD4d16_UPD: 2292 case ARM::VLD4d32_UPD: 2293 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2294 return MCDisassembler::Fail; 2295 break; 2296 case ARM::VLD3q8: 2297 case ARM::VLD3q16: 2298 case ARM::VLD3q32: 2299 case ARM::VLD3q8_UPD: 2300 case ARM::VLD3q16_UPD: 2301 case ARM::VLD3q32_UPD: 2302 case ARM::VLD4q8: 2303 case ARM::VLD4q16: 2304 case ARM::VLD4q32: 2305 case ARM::VLD4q8_UPD: 2306 case ARM::VLD4q16_UPD: 2307 case ARM::VLD4q32_UPD: 2308 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2309 return MCDisassembler::Fail; 2310 default: 2311 break; 2312 } 2313 2314 // Third output register 2315 switch(Inst.getOpcode()) { 2316 case ARM::VLD3d8: 2317 case ARM::VLD3d16: 2318 case ARM::VLD3d32: 2319 case ARM::VLD3d8_UPD: 2320 case ARM::VLD3d16_UPD: 2321 case ARM::VLD3d32_UPD: 2322 case ARM::VLD4d8: 2323 case ARM::VLD4d16: 2324 case ARM::VLD4d32: 2325 case ARM::VLD4d8_UPD: 2326 case ARM::VLD4d16_UPD: 2327 case ARM::VLD4d32_UPD: 2328 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2329 return MCDisassembler::Fail; 2330 break; 2331 case ARM::VLD3q8: 2332 case ARM::VLD3q16: 2333 case ARM::VLD3q32: 2334 case ARM::VLD3q8_UPD: 2335 case ARM::VLD3q16_UPD: 2336 case ARM::VLD3q32_UPD: 2337 case ARM::VLD4q8: 2338 case ARM::VLD4q16: 2339 case ARM::VLD4q32: 2340 case ARM::VLD4q8_UPD: 2341 case ARM::VLD4q16_UPD: 2342 case ARM::VLD4q32_UPD: 2343 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2344 return MCDisassembler::Fail; 2345 break; 2346 default: 2347 break; 2348 } 2349 2350 // Fourth output register 2351 switch (Inst.getOpcode()) { 2352 case ARM::VLD4d8: 2353 case ARM::VLD4d16: 2354 case ARM::VLD4d32: 2355 case ARM::VLD4d8_UPD: 2356 case ARM::VLD4d16_UPD: 2357 case ARM::VLD4d32_UPD: 2358 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2359 return MCDisassembler::Fail; 2360 break; 2361 case ARM::VLD4q8: 2362 case ARM::VLD4q16: 2363 case ARM::VLD4q32: 2364 case ARM::VLD4q8_UPD: 2365 case ARM::VLD4q16_UPD: 2366 case ARM::VLD4q32_UPD: 2367 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2368 return MCDisassembler::Fail; 2369 break; 2370 default: 2371 break; 2372 } 2373 2374 // Writeback operand 2375 switch (Inst.getOpcode()) { 2376 case ARM::VLD1d8wb_fixed: 2377 case ARM::VLD1d16wb_fixed: 2378 case ARM::VLD1d32wb_fixed: 2379 case ARM::VLD1d64wb_fixed: 2380 case ARM::VLD1d8wb_register: 2381 case ARM::VLD1d16wb_register: 2382 case ARM::VLD1d32wb_register: 2383 case ARM::VLD1d64wb_register: 2384 case ARM::VLD1q8wb_fixed: 2385 case ARM::VLD1q16wb_fixed: 2386 case ARM::VLD1q32wb_fixed: 2387 case ARM::VLD1q64wb_fixed: 2388 case ARM::VLD1q8wb_register: 2389 case ARM::VLD1q16wb_register: 2390 case ARM::VLD1q32wb_register: 2391 case ARM::VLD1q64wb_register: 2392 case ARM::VLD1d8Twb_fixed: 2393 case ARM::VLD1d8Twb_register: 2394 case ARM::VLD1d16Twb_fixed: 2395 case ARM::VLD1d16Twb_register: 2396 case ARM::VLD1d32Twb_fixed: 2397 case ARM::VLD1d32Twb_register: 2398 case ARM::VLD1d64Twb_fixed: 2399 case ARM::VLD1d64Twb_register: 2400 case ARM::VLD1d8Qwb_fixed: 2401 case ARM::VLD1d8Qwb_register: 2402 case ARM::VLD1d16Qwb_fixed: 2403 case ARM::VLD1d16Qwb_register: 2404 case ARM::VLD1d32Qwb_fixed: 2405 case ARM::VLD1d32Qwb_register: 2406 case ARM::VLD1d64Qwb_fixed: 2407 case ARM::VLD1d64Qwb_register: 2408 case ARM::VLD2d8wb_fixed: 2409 case ARM::VLD2d16wb_fixed: 2410 case ARM::VLD2d32wb_fixed: 2411 case ARM::VLD2q8wb_fixed: 2412 case ARM::VLD2q16wb_fixed: 2413 case ARM::VLD2q32wb_fixed: 2414 case ARM::VLD2d8wb_register: 2415 case ARM::VLD2d16wb_register: 2416 case ARM::VLD2d32wb_register: 2417 case ARM::VLD2q8wb_register: 2418 case ARM::VLD2q16wb_register: 2419 case ARM::VLD2q32wb_register: 2420 case ARM::VLD2b8wb_fixed: 2421 case ARM::VLD2b16wb_fixed: 2422 case ARM::VLD2b32wb_fixed: 2423 case ARM::VLD2b8wb_register: 2424 case ARM::VLD2b16wb_register: 2425 case ARM::VLD2b32wb_register: 2426 Inst.addOperand(MCOperand::CreateImm(0)); 2427 break; 2428 case ARM::VLD3d8_UPD: 2429 case ARM::VLD3d16_UPD: 2430 case ARM::VLD3d32_UPD: 2431 case ARM::VLD3q8_UPD: 2432 case ARM::VLD3q16_UPD: 2433 case ARM::VLD3q32_UPD: 2434 case ARM::VLD4d8_UPD: 2435 case ARM::VLD4d16_UPD: 2436 case ARM::VLD4d32_UPD: 2437 case ARM::VLD4q8_UPD: 2438 case ARM::VLD4q16_UPD: 2439 case ARM::VLD4q32_UPD: 2440 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2441 return MCDisassembler::Fail; 2442 break; 2443 default: 2444 break; 2445 } 2446 2447 // AddrMode6 Base (register+alignment) 2448 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2449 return MCDisassembler::Fail; 2450 2451 // AddrMode6 Offset (register) 2452 switch (Inst.getOpcode()) { 2453 default: 2454 // The below have been updated to have explicit am6offset split 2455 // between fixed and register offset. For those instructions not 2456 // yet updated, we need to add an additional reg0 operand for the 2457 // fixed variant. 2458 // 2459 // The fixed offset encodes as Rm == 0xd, so we check for that. 2460 if (Rm == 0xd) { 2461 Inst.addOperand(MCOperand::CreateReg(0)); 2462 break; 2463 } 2464 // Fall through to handle the register offset variant. 2465 case ARM::VLD1d8wb_fixed: 2466 case ARM::VLD1d16wb_fixed: 2467 case ARM::VLD1d32wb_fixed: 2468 case ARM::VLD1d64wb_fixed: 2469 case ARM::VLD1d8Twb_fixed: 2470 case ARM::VLD1d16Twb_fixed: 2471 case ARM::VLD1d32Twb_fixed: 2472 case ARM::VLD1d64Twb_fixed: 2473 case ARM::VLD1d8Qwb_fixed: 2474 case ARM::VLD1d16Qwb_fixed: 2475 case ARM::VLD1d32Qwb_fixed: 2476 case ARM::VLD1d64Qwb_fixed: 2477 case ARM::VLD1d8wb_register: 2478 case ARM::VLD1d16wb_register: 2479 case ARM::VLD1d32wb_register: 2480 case ARM::VLD1d64wb_register: 2481 case ARM::VLD1q8wb_fixed: 2482 case ARM::VLD1q16wb_fixed: 2483 case ARM::VLD1q32wb_fixed: 2484 case ARM::VLD1q64wb_fixed: 2485 case ARM::VLD1q8wb_register: 2486 case ARM::VLD1q16wb_register: 2487 case ARM::VLD1q32wb_register: 2488 case ARM::VLD1q64wb_register: 2489 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2490 // variant encodes Rm == 0xf. Anything else is a register offset post- 2491 // increment and we need to add the register operand to the instruction. 2492 if (Rm != 0xD && Rm != 0xF && 2493 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2494 return MCDisassembler::Fail; 2495 break; 2496 case ARM::VLD2d8wb_fixed: 2497 case ARM::VLD2d16wb_fixed: 2498 case ARM::VLD2d32wb_fixed: 2499 case ARM::VLD2b8wb_fixed: 2500 case ARM::VLD2b16wb_fixed: 2501 case ARM::VLD2b32wb_fixed: 2502 case ARM::VLD2q8wb_fixed: 2503 case ARM::VLD2q16wb_fixed: 2504 case ARM::VLD2q32wb_fixed: 2505 break; 2506 } 2507 2508 return S; 2509 } 2510 2511 static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn, 2512 uint64_t Address, const void *Decoder) { 2513 unsigned type = fieldFromInstruction(Insn, 8, 4); 2514 unsigned align = fieldFromInstruction(Insn, 4, 2); 2515 if (type == 6 && (align & 2)) return MCDisassembler::Fail; 2516 if (type == 7 && (align & 2)) return MCDisassembler::Fail; 2517 if (type == 10 && align == 3) return MCDisassembler::Fail; 2518 2519 unsigned load = fieldFromInstruction(Insn, 21, 1); 2520 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2521 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2522 } 2523 2524 static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn, 2525 uint64_t Address, const void *Decoder) { 2526 unsigned size = fieldFromInstruction(Insn, 6, 2); 2527 if (size == 3) return MCDisassembler::Fail; 2528 2529 unsigned type = fieldFromInstruction(Insn, 8, 4); 2530 unsigned align = fieldFromInstruction(Insn, 4, 2); 2531 if (type == 8 && align == 3) return MCDisassembler::Fail; 2532 if (type == 9 && align == 3) return MCDisassembler::Fail; 2533 2534 unsigned load = fieldFromInstruction(Insn, 21, 1); 2535 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2536 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2537 } 2538 2539 static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn, 2540 uint64_t Address, const void *Decoder) { 2541 unsigned size = fieldFromInstruction(Insn, 6, 2); 2542 if (size == 3) return MCDisassembler::Fail; 2543 2544 unsigned align = fieldFromInstruction(Insn, 4, 2); 2545 if (align & 2) return MCDisassembler::Fail; 2546 2547 unsigned load = fieldFromInstruction(Insn, 21, 1); 2548 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2549 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2550 } 2551 2552 static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn, 2553 uint64_t Address, const void *Decoder) { 2554 unsigned size = fieldFromInstruction(Insn, 6, 2); 2555 if (size == 3) return MCDisassembler::Fail; 2556 2557 unsigned load = fieldFromInstruction(Insn, 21, 1); 2558 return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder) 2559 : DecodeVSTInstruction(Inst, Insn, Address, Decoder); 2560 } 2561 2562 static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn, 2563 uint64_t Address, const void *Decoder) { 2564 DecodeStatus S = MCDisassembler::Success; 2565 2566 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2567 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2568 unsigned wb = fieldFromInstruction(Insn, 16, 4); 2569 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2570 Rn |= fieldFromInstruction(Insn, 4, 2) << 4; 2571 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2572 2573 // Writeback Operand 2574 switch (Inst.getOpcode()) { 2575 case ARM::VST1d8wb_fixed: 2576 case ARM::VST1d16wb_fixed: 2577 case ARM::VST1d32wb_fixed: 2578 case ARM::VST1d64wb_fixed: 2579 case ARM::VST1d8wb_register: 2580 case ARM::VST1d16wb_register: 2581 case ARM::VST1d32wb_register: 2582 case ARM::VST1d64wb_register: 2583 case ARM::VST1q8wb_fixed: 2584 case ARM::VST1q16wb_fixed: 2585 case ARM::VST1q32wb_fixed: 2586 case ARM::VST1q64wb_fixed: 2587 case ARM::VST1q8wb_register: 2588 case ARM::VST1q16wb_register: 2589 case ARM::VST1q32wb_register: 2590 case ARM::VST1q64wb_register: 2591 case ARM::VST1d8Twb_fixed: 2592 case ARM::VST1d16Twb_fixed: 2593 case ARM::VST1d32Twb_fixed: 2594 case ARM::VST1d64Twb_fixed: 2595 case ARM::VST1d8Twb_register: 2596 case ARM::VST1d16Twb_register: 2597 case ARM::VST1d32Twb_register: 2598 case ARM::VST1d64Twb_register: 2599 case ARM::VST1d8Qwb_fixed: 2600 case ARM::VST1d16Qwb_fixed: 2601 case ARM::VST1d32Qwb_fixed: 2602 case ARM::VST1d64Qwb_fixed: 2603 case ARM::VST1d8Qwb_register: 2604 case ARM::VST1d16Qwb_register: 2605 case ARM::VST1d32Qwb_register: 2606 case ARM::VST1d64Qwb_register: 2607 case ARM::VST2d8wb_fixed: 2608 case ARM::VST2d16wb_fixed: 2609 case ARM::VST2d32wb_fixed: 2610 case ARM::VST2d8wb_register: 2611 case ARM::VST2d16wb_register: 2612 case ARM::VST2d32wb_register: 2613 case ARM::VST2q8wb_fixed: 2614 case ARM::VST2q16wb_fixed: 2615 case ARM::VST2q32wb_fixed: 2616 case ARM::VST2q8wb_register: 2617 case ARM::VST2q16wb_register: 2618 case ARM::VST2q32wb_register: 2619 case ARM::VST2b8wb_fixed: 2620 case ARM::VST2b16wb_fixed: 2621 case ARM::VST2b32wb_fixed: 2622 case ARM::VST2b8wb_register: 2623 case ARM::VST2b16wb_register: 2624 case ARM::VST2b32wb_register: 2625 if (Rm == 0xF) 2626 return MCDisassembler::Fail; 2627 Inst.addOperand(MCOperand::CreateImm(0)); 2628 break; 2629 case ARM::VST3d8_UPD: 2630 case ARM::VST3d16_UPD: 2631 case ARM::VST3d32_UPD: 2632 case ARM::VST3q8_UPD: 2633 case ARM::VST3q16_UPD: 2634 case ARM::VST3q32_UPD: 2635 case ARM::VST4d8_UPD: 2636 case ARM::VST4d16_UPD: 2637 case ARM::VST4d32_UPD: 2638 case ARM::VST4q8_UPD: 2639 case ARM::VST4q16_UPD: 2640 case ARM::VST4q32_UPD: 2641 if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder))) 2642 return MCDisassembler::Fail; 2643 break; 2644 default: 2645 break; 2646 } 2647 2648 // AddrMode6 Base (register+alignment) 2649 if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder))) 2650 return MCDisassembler::Fail; 2651 2652 // AddrMode6 Offset (register) 2653 switch (Inst.getOpcode()) { 2654 default: 2655 if (Rm == 0xD) 2656 Inst.addOperand(MCOperand::CreateReg(0)); 2657 else if (Rm != 0xF) { 2658 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2659 return MCDisassembler::Fail; 2660 } 2661 break; 2662 case ARM::VST1d8wb_fixed: 2663 case ARM::VST1d16wb_fixed: 2664 case ARM::VST1d32wb_fixed: 2665 case ARM::VST1d64wb_fixed: 2666 case ARM::VST1q8wb_fixed: 2667 case ARM::VST1q16wb_fixed: 2668 case ARM::VST1q32wb_fixed: 2669 case ARM::VST1q64wb_fixed: 2670 case ARM::VST1d8Twb_fixed: 2671 case ARM::VST1d16Twb_fixed: 2672 case ARM::VST1d32Twb_fixed: 2673 case ARM::VST1d64Twb_fixed: 2674 case ARM::VST1d8Qwb_fixed: 2675 case ARM::VST1d16Qwb_fixed: 2676 case ARM::VST1d32Qwb_fixed: 2677 case ARM::VST1d64Qwb_fixed: 2678 case ARM::VST2d8wb_fixed: 2679 case ARM::VST2d16wb_fixed: 2680 case ARM::VST2d32wb_fixed: 2681 case ARM::VST2q8wb_fixed: 2682 case ARM::VST2q16wb_fixed: 2683 case ARM::VST2q32wb_fixed: 2684 case ARM::VST2b8wb_fixed: 2685 case ARM::VST2b16wb_fixed: 2686 case ARM::VST2b32wb_fixed: 2687 break; 2688 } 2689 2690 2691 // First input register 2692 switch (Inst.getOpcode()) { 2693 case ARM::VST1q16: 2694 case ARM::VST1q32: 2695 case ARM::VST1q64: 2696 case ARM::VST1q8: 2697 case ARM::VST1q16wb_fixed: 2698 case ARM::VST1q16wb_register: 2699 case ARM::VST1q32wb_fixed: 2700 case ARM::VST1q32wb_register: 2701 case ARM::VST1q64wb_fixed: 2702 case ARM::VST1q64wb_register: 2703 case ARM::VST1q8wb_fixed: 2704 case ARM::VST1q8wb_register: 2705 case ARM::VST2d16: 2706 case ARM::VST2d32: 2707 case ARM::VST2d8: 2708 case ARM::VST2d16wb_fixed: 2709 case ARM::VST2d16wb_register: 2710 case ARM::VST2d32wb_fixed: 2711 case ARM::VST2d32wb_register: 2712 case ARM::VST2d8wb_fixed: 2713 case ARM::VST2d8wb_register: 2714 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2715 return MCDisassembler::Fail; 2716 break; 2717 case ARM::VST2b16: 2718 case ARM::VST2b32: 2719 case ARM::VST2b8: 2720 case ARM::VST2b16wb_fixed: 2721 case ARM::VST2b16wb_register: 2722 case ARM::VST2b32wb_fixed: 2723 case ARM::VST2b32wb_register: 2724 case ARM::VST2b8wb_fixed: 2725 case ARM::VST2b8wb_register: 2726 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2727 return MCDisassembler::Fail; 2728 break; 2729 default: 2730 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2731 return MCDisassembler::Fail; 2732 } 2733 2734 // Second input register 2735 switch (Inst.getOpcode()) { 2736 case ARM::VST3d8: 2737 case ARM::VST3d16: 2738 case ARM::VST3d32: 2739 case ARM::VST3d8_UPD: 2740 case ARM::VST3d16_UPD: 2741 case ARM::VST3d32_UPD: 2742 case ARM::VST4d8: 2743 case ARM::VST4d16: 2744 case ARM::VST4d32: 2745 case ARM::VST4d8_UPD: 2746 case ARM::VST4d16_UPD: 2747 case ARM::VST4d32_UPD: 2748 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder))) 2749 return MCDisassembler::Fail; 2750 break; 2751 case ARM::VST3q8: 2752 case ARM::VST3q16: 2753 case ARM::VST3q32: 2754 case ARM::VST3q8_UPD: 2755 case ARM::VST3q16_UPD: 2756 case ARM::VST3q32_UPD: 2757 case ARM::VST4q8: 2758 case ARM::VST4q16: 2759 case ARM::VST4q32: 2760 case ARM::VST4q8_UPD: 2761 case ARM::VST4q16_UPD: 2762 case ARM::VST4q32_UPD: 2763 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2764 return MCDisassembler::Fail; 2765 break; 2766 default: 2767 break; 2768 } 2769 2770 // Third input register 2771 switch (Inst.getOpcode()) { 2772 case ARM::VST3d8: 2773 case ARM::VST3d16: 2774 case ARM::VST3d32: 2775 case ARM::VST3d8_UPD: 2776 case ARM::VST3d16_UPD: 2777 case ARM::VST3d32_UPD: 2778 case ARM::VST4d8: 2779 case ARM::VST4d16: 2780 case ARM::VST4d32: 2781 case ARM::VST4d8_UPD: 2782 case ARM::VST4d16_UPD: 2783 case ARM::VST4d32_UPD: 2784 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder))) 2785 return MCDisassembler::Fail; 2786 break; 2787 case ARM::VST3q8: 2788 case ARM::VST3q16: 2789 case ARM::VST3q32: 2790 case ARM::VST3q8_UPD: 2791 case ARM::VST3q16_UPD: 2792 case ARM::VST3q32_UPD: 2793 case ARM::VST4q8: 2794 case ARM::VST4q16: 2795 case ARM::VST4q32: 2796 case ARM::VST4q8_UPD: 2797 case ARM::VST4q16_UPD: 2798 case ARM::VST4q32_UPD: 2799 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder))) 2800 return MCDisassembler::Fail; 2801 break; 2802 default: 2803 break; 2804 } 2805 2806 // Fourth input register 2807 switch (Inst.getOpcode()) { 2808 case ARM::VST4d8: 2809 case ARM::VST4d16: 2810 case ARM::VST4d32: 2811 case ARM::VST4d8_UPD: 2812 case ARM::VST4d16_UPD: 2813 case ARM::VST4d32_UPD: 2814 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder))) 2815 return MCDisassembler::Fail; 2816 break; 2817 case ARM::VST4q8: 2818 case ARM::VST4q16: 2819 case ARM::VST4q32: 2820 case ARM::VST4q8_UPD: 2821 case ARM::VST4q16_UPD: 2822 case ARM::VST4q32_UPD: 2823 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder))) 2824 return MCDisassembler::Fail; 2825 break; 2826 default: 2827 break; 2828 } 2829 2830 return S; 2831 } 2832 2833 static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn, 2834 uint64_t Address, const void *Decoder) { 2835 DecodeStatus S = MCDisassembler::Success; 2836 2837 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2838 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2839 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2840 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2841 unsigned align = fieldFromInstruction(Insn, 4, 1); 2842 unsigned size = fieldFromInstruction(Insn, 6, 2); 2843 2844 if (size == 0 && align == 1) 2845 return MCDisassembler::Fail; 2846 align *= (1 << size); 2847 2848 switch (Inst.getOpcode()) { 2849 case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8: 2850 case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register: 2851 case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register: 2852 case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register: 2853 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2854 return MCDisassembler::Fail; 2855 break; 2856 default: 2857 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2858 return MCDisassembler::Fail; 2859 break; 2860 } 2861 if (Rm != 0xF) { 2862 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2863 return MCDisassembler::Fail; 2864 } 2865 2866 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2867 return MCDisassembler::Fail; 2868 Inst.addOperand(MCOperand::CreateImm(align)); 2869 2870 // The fixed offset post-increment encodes Rm == 0xd. The no-writeback 2871 // variant encodes Rm == 0xf. Anything else is a register offset post- 2872 // increment and we need to add the register operand to the instruction. 2873 if (Rm != 0xD && Rm != 0xF && 2874 !Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2875 return MCDisassembler::Fail; 2876 2877 return S; 2878 } 2879 2880 static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn, 2881 uint64_t Address, const void *Decoder) { 2882 DecodeStatus S = MCDisassembler::Success; 2883 2884 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2885 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2886 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2887 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2888 unsigned align = fieldFromInstruction(Insn, 4, 1); 2889 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2); 2890 align *= 2*size; 2891 2892 switch (Inst.getOpcode()) { 2893 case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8: 2894 case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register: 2895 case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register: 2896 case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register: 2897 if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder))) 2898 return MCDisassembler::Fail; 2899 break; 2900 case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2: 2901 case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register: 2902 case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register: 2903 case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register: 2904 if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder))) 2905 return MCDisassembler::Fail; 2906 break; 2907 default: 2908 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2909 return MCDisassembler::Fail; 2910 break; 2911 } 2912 2913 if (Rm != 0xF) 2914 Inst.addOperand(MCOperand::CreateImm(0)); 2915 2916 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2917 return MCDisassembler::Fail; 2918 Inst.addOperand(MCOperand::CreateImm(align)); 2919 2920 if (Rm != 0xD && Rm != 0xF) { 2921 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2922 return MCDisassembler::Fail; 2923 } 2924 2925 return S; 2926 } 2927 2928 static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn, 2929 uint64_t Address, const void *Decoder) { 2930 DecodeStatus S = MCDisassembler::Success; 2931 2932 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2933 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2934 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2935 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2936 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 2937 2938 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2939 return MCDisassembler::Fail; 2940 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2941 return MCDisassembler::Fail; 2942 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2943 return MCDisassembler::Fail; 2944 if (Rm != 0xF) { 2945 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2946 return MCDisassembler::Fail; 2947 } 2948 2949 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2950 return MCDisassembler::Fail; 2951 Inst.addOperand(MCOperand::CreateImm(0)); 2952 2953 if (Rm == 0xD) 2954 Inst.addOperand(MCOperand::CreateReg(0)); 2955 else if (Rm != 0xF) { 2956 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 2957 return MCDisassembler::Fail; 2958 } 2959 2960 return S; 2961 } 2962 2963 static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn, 2964 uint64_t Address, const void *Decoder) { 2965 DecodeStatus S = MCDisassembler::Success; 2966 2967 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 2968 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 2969 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 2970 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 2971 unsigned size = fieldFromInstruction(Insn, 6, 2); 2972 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1; 2973 unsigned align = fieldFromInstruction(Insn, 4, 1); 2974 2975 if (size == 0x3) { 2976 if (align == 0) 2977 return MCDisassembler::Fail; 2978 align = 16; 2979 } else { 2980 if (size == 2) { 2981 align *= 8; 2982 } else { 2983 size = 1 << size; 2984 align *= 4*size; 2985 } 2986 } 2987 2988 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 2989 return MCDisassembler::Fail; 2990 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder))) 2991 return MCDisassembler::Fail; 2992 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder))) 2993 return MCDisassembler::Fail; 2994 if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder))) 2995 return MCDisassembler::Fail; 2996 if (Rm != 0xF) { 2997 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 2998 return MCDisassembler::Fail; 2999 } 3000 3001 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3002 return MCDisassembler::Fail; 3003 Inst.addOperand(MCOperand::CreateImm(align)); 3004 3005 if (Rm == 0xD) 3006 Inst.addOperand(MCOperand::CreateReg(0)); 3007 else if (Rm != 0xF) { 3008 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3009 return MCDisassembler::Fail; 3010 } 3011 3012 return S; 3013 } 3014 3015 static DecodeStatus 3016 DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn, 3017 uint64_t Address, const void *Decoder) { 3018 DecodeStatus S = MCDisassembler::Success; 3019 3020 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3021 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3022 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3023 imm |= fieldFromInstruction(Insn, 16, 3) << 4; 3024 imm |= fieldFromInstruction(Insn, 24, 1) << 7; 3025 imm |= fieldFromInstruction(Insn, 8, 4) << 8; 3026 imm |= fieldFromInstruction(Insn, 5, 1) << 12; 3027 unsigned Q = fieldFromInstruction(Insn, 6, 1); 3028 3029 if (Q) { 3030 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3031 return MCDisassembler::Fail; 3032 } else { 3033 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3034 return MCDisassembler::Fail; 3035 } 3036 3037 Inst.addOperand(MCOperand::CreateImm(imm)); 3038 3039 switch (Inst.getOpcode()) { 3040 case ARM::VORRiv4i16: 3041 case ARM::VORRiv2i32: 3042 case ARM::VBICiv4i16: 3043 case ARM::VBICiv2i32: 3044 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3045 return MCDisassembler::Fail; 3046 break; 3047 case ARM::VORRiv8i16: 3048 case ARM::VORRiv4i32: 3049 case ARM::VBICiv8i16: 3050 case ARM::VBICiv4i32: 3051 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3052 return MCDisassembler::Fail; 3053 break; 3054 default: 3055 break; 3056 } 3057 3058 return S; 3059 } 3060 3061 static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn, 3062 uint64_t Address, const void *Decoder) { 3063 DecodeStatus S = MCDisassembler::Success; 3064 3065 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3066 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3067 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3068 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3069 unsigned size = fieldFromInstruction(Insn, 18, 2); 3070 3071 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder))) 3072 return MCDisassembler::Fail; 3073 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3074 return MCDisassembler::Fail; 3075 Inst.addOperand(MCOperand::CreateImm(8 << size)); 3076 3077 return S; 3078 } 3079 3080 static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val, 3081 uint64_t Address, const void *Decoder) { 3082 Inst.addOperand(MCOperand::CreateImm(8 - Val)); 3083 return MCDisassembler::Success; 3084 } 3085 3086 static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val, 3087 uint64_t Address, const void *Decoder) { 3088 Inst.addOperand(MCOperand::CreateImm(16 - Val)); 3089 return MCDisassembler::Success; 3090 } 3091 3092 static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val, 3093 uint64_t Address, const void *Decoder) { 3094 Inst.addOperand(MCOperand::CreateImm(32 - Val)); 3095 return MCDisassembler::Success; 3096 } 3097 3098 static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val, 3099 uint64_t Address, const void *Decoder) { 3100 Inst.addOperand(MCOperand::CreateImm(64 - Val)); 3101 return MCDisassembler::Success; 3102 } 3103 3104 static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn, 3105 uint64_t Address, const void *Decoder) { 3106 DecodeStatus S = MCDisassembler::Success; 3107 3108 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 3109 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 3110 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3111 Rn |= fieldFromInstruction(Insn, 7, 1) << 4; 3112 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3113 Rm |= fieldFromInstruction(Insn, 5, 1) << 4; 3114 unsigned op = fieldFromInstruction(Insn, 6, 1); 3115 3116 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3117 return MCDisassembler::Fail; 3118 if (op) { 3119 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 3120 return MCDisassembler::Fail; // Writeback 3121 } 3122 3123 switch (Inst.getOpcode()) { 3124 case ARM::VTBL2: 3125 case ARM::VTBX2: 3126 if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder))) 3127 return MCDisassembler::Fail; 3128 break; 3129 default: 3130 if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder))) 3131 return MCDisassembler::Fail; 3132 } 3133 3134 if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder))) 3135 return MCDisassembler::Fail; 3136 3137 return S; 3138 } 3139 3140 static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn, 3141 uint64_t Address, const void *Decoder) { 3142 DecodeStatus S = MCDisassembler::Success; 3143 3144 unsigned dst = fieldFromInstruction(Insn, 8, 3); 3145 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3146 3147 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder))) 3148 return MCDisassembler::Fail; 3149 3150 switch(Inst.getOpcode()) { 3151 default: 3152 return MCDisassembler::Fail; 3153 case ARM::tADR: 3154 break; // tADR does not explicitly represent the PC as an operand. 3155 case ARM::tADDrSPi: 3156 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3157 break; 3158 } 3159 3160 Inst.addOperand(MCOperand::CreateImm(imm)); 3161 return S; 3162 } 3163 3164 static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val, 3165 uint64_t Address, const void *Decoder) { 3166 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4, 3167 true, 2, Inst, Decoder)) 3168 Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1))); 3169 return MCDisassembler::Success; 3170 } 3171 3172 static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val, 3173 uint64_t Address, const void *Decoder) { 3174 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4, 3175 true, 4, Inst, Decoder)) 3176 Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val))); 3177 return MCDisassembler::Success; 3178 } 3179 3180 static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val, 3181 uint64_t Address, const void *Decoder) { 3182 if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4, 3183 true, 2, Inst, Decoder)) 3184 Inst.addOperand(MCOperand::CreateImm(Val << 1)); 3185 return MCDisassembler::Success; 3186 } 3187 3188 static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val, 3189 uint64_t Address, const void *Decoder) { 3190 DecodeStatus S = MCDisassembler::Success; 3191 3192 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3193 unsigned Rm = fieldFromInstruction(Val, 3, 3); 3194 3195 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3196 return MCDisassembler::Fail; 3197 if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder))) 3198 return MCDisassembler::Fail; 3199 3200 return S; 3201 } 3202 3203 static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val, 3204 uint64_t Address, const void *Decoder) { 3205 DecodeStatus S = MCDisassembler::Success; 3206 3207 unsigned Rn = fieldFromInstruction(Val, 0, 3); 3208 unsigned imm = fieldFromInstruction(Val, 3, 5); 3209 3210 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder))) 3211 return MCDisassembler::Fail; 3212 Inst.addOperand(MCOperand::CreateImm(imm)); 3213 3214 return S; 3215 } 3216 3217 static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val, 3218 uint64_t Address, const void *Decoder) { 3219 unsigned imm = Val << 2; 3220 3221 Inst.addOperand(MCOperand::CreateImm(imm)); 3222 tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder); 3223 3224 return MCDisassembler::Success; 3225 } 3226 3227 static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val, 3228 uint64_t Address, const void *Decoder) { 3229 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3230 Inst.addOperand(MCOperand::CreateImm(Val)); 3231 3232 return MCDisassembler::Success; 3233 } 3234 3235 static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val, 3236 uint64_t Address, const void *Decoder) { 3237 DecodeStatus S = MCDisassembler::Success; 3238 3239 unsigned Rn = fieldFromInstruction(Val, 6, 4); 3240 unsigned Rm = fieldFromInstruction(Val, 2, 4); 3241 unsigned imm = fieldFromInstruction(Val, 0, 2); 3242 3243 // Thumb stores cannot use PC as dest register. 3244 switch (Inst.getOpcode()) { 3245 case ARM::t2STRHs: 3246 case ARM::t2STRBs: 3247 case ARM::t2STRs: 3248 if (Rn == 15) 3249 return MCDisassembler::Fail; 3250 default: 3251 break; 3252 } 3253 3254 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3255 return MCDisassembler::Fail; 3256 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3257 return MCDisassembler::Fail; 3258 Inst.addOperand(MCOperand::CreateImm(imm)); 3259 3260 return S; 3261 } 3262 3263 static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn, 3264 uint64_t Address, const void *Decoder) { 3265 DecodeStatus S = MCDisassembler::Success; 3266 3267 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3268 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3269 3270 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() 3271 .getFeatureBits(); 3272 bool hasMP = featureBits & ARM::FeatureMP; 3273 bool hasV7Ops = featureBits & ARM::HasV7Ops; 3274 3275 if (Rn == 15) { 3276 switch (Inst.getOpcode()) { 3277 case ARM::t2LDRBs: 3278 Inst.setOpcode(ARM::t2LDRBpci); 3279 break; 3280 case ARM::t2LDRHs: 3281 Inst.setOpcode(ARM::t2LDRHpci); 3282 break; 3283 case ARM::t2LDRSHs: 3284 Inst.setOpcode(ARM::t2LDRSHpci); 3285 break; 3286 case ARM::t2LDRSBs: 3287 Inst.setOpcode(ARM::t2LDRSBpci); 3288 break; 3289 case ARM::t2LDRs: 3290 Inst.setOpcode(ARM::t2LDRpci); 3291 break; 3292 case ARM::t2PLDs: 3293 Inst.setOpcode(ARM::t2PLDpci); 3294 break; 3295 case ARM::t2PLIs: 3296 Inst.setOpcode(ARM::t2PLIpci); 3297 break; 3298 default: 3299 return MCDisassembler::Fail; 3300 } 3301 3302 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3303 } 3304 3305 if (Rt == 15) { 3306 switch (Inst.getOpcode()) { 3307 case ARM::t2LDRSHs: 3308 return MCDisassembler::Fail; 3309 case ARM::t2LDRHs: 3310 Inst.setOpcode(ARM::t2PLDWs); 3311 break; 3312 case ARM::t2LDRSBs: 3313 Inst.setOpcode(ARM::t2PLIs); 3314 default: 3315 break; 3316 } 3317 } 3318 3319 switch (Inst.getOpcode()) { 3320 case ARM::t2PLDs: 3321 break; 3322 case ARM::t2PLIs: 3323 if (!hasV7Ops) 3324 return MCDisassembler::Fail; 3325 break; 3326 case ARM::t2PLDWs: 3327 if (!hasV7Ops || !hasMP) 3328 return MCDisassembler::Fail; 3329 break; 3330 default: 3331 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3332 return MCDisassembler::Fail; 3333 } 3334 3335 unsigned addrmode = fieldFromInstruction(Insn, 4, 2); 3336 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2; 3337 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6; 3338 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder))) 3339 return MCDisassembler::Fail; 3340 3341 return S; 3342 } 3343 3344 static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn, 3345 uint64_t Address, const void* Decoder) { 3346 DecodeStatus S = MCDisassembler::Success; 3347 3348 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3349 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3350 unsigned U = fieldFromInstruction(Insn, 9, 1); 3351 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3352 imm |= (U << 8); 3353 imm |= (Rn << 9); 3354 unsigned add = fieldFromInstruction(Insn, 9, 1); 3355 3356 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() 3357 .getFeatureBits(); 3358 bool hasMP = featureBits & ARM::FeatureMP; 3359 bool hasV7Ops = featureBits & ARM::HasV7Ops; 3360 3361 if (Rn == 15) { 3362 switch (Inst.getOpcode()) { 3363 case ARM::t2LDRi8: 3364 Inst.setOpcode(ARM::t2LDRpci); 3365 break; 3366 case ARM::t2LDRBi8: 3367 Inst.setOpcode(ARM::t2LDRBpci); 3368 break; 3369 case ARM::t2LDRSBi8: 3370 Inst.setOpcode(ARM::t2LDRSBpci); 3371 break; 3372 case ARM::t2LDRHi8: 3373 Inst.setOpcode(ARM::t2LDRHpci); 3374 break; 3375 case ARM::t2LDRSHi8: 3376 Inst.setOpcode(ARM::t2LDRSHpci); 3377 break; 3378 case ARM::t2PLDi8: 3379 Inst.setOpcode(ARM::t2PLDpci); 3380 break; 3381 case ARM::t2PLIi8: 3382 Inst.setOpcode(ARM::t2PLIpci); 3383 break; 3384 default: 3385 return MCDisassembler::Fail; 3386 } 3387 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3388 } 3389 3390 if (Rt == 15) { 3391 switch (Inst.getOpcode()) { 3392 case ARM::t2LDRSHi8: 3393 return MCDisassembler::Fail; 3394 case ARM::t2LDRHi8: 3395 if (!add) 3396 Inst.setOpcode(ARM::t2PLDWi8); 3397 break; 3398 case ARM::t2LDRSBi8: 3399 Inst.setOpcode(ARM::t2PLIi8); 3400 break; 3401 default: 3402 break; 3403 } 3404 } 3405 3406 switch (Inst.getOpcode()) { 3407 case ARM::t2PLDi8: 3408 break; 3409 case ARM::t2PLIi8: 3410 if (!hasV7Ops) 3411 return MCDisassembler::Fail; 3412 break; 3413 case ARM::t2PLDWi8: 3414 if (!hasV7Ops || !hasMP) 3415 return MCDisassembler::Fail; 3416 break; 3417 default: 3418 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3419 return MCDisassembler::Fail; 3420 } 3421 3422 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3423 return MCDisassembler::Fail; 3424 return S; 3425 } 3426 3427 static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn, 3428 uint64_t Address, const void* Decoder) { 3429 DecodeStatus S = MCDisassembler::Success; 3430 3431 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3432 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3433 unsigned imm = fieldFromInstruction(Insn, 0, 12); 3434 imm |= (Rn << 13); 3435 3436 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() 3437 .getFeatureBits(); 3438 bool hasMP = (featureBits & ARM::FeatureMP); 3439 bool hasV7Ops = (featureBits & ARM::HasV7Ops); 3440 3441 if (Rn == 15) { 3442 switch (Inst.getOpcode()) { 3443 case ARM::t2LDRi12: 3444 Inst.setOpcode(ARM::t2LDRpci); 3445 break; 3446 case ARM::t2LDRHi12: 3447 Inst.setOpcode(ARM::t2LDRHpci); 3448 break; 3449 case ARM::t2LDRSHi12: 3450 Inst.setOpcode(ARM::t2LDRSHpci); 3451 break; 3452 case ARM::t2LDRBi12: 3453 Inst.setOpcode(ARM::t2LDRBpci); 3454 break; 3455 case ARM::t2LDRSBi12: 3456 Inst.setOpcode(ARM::t2LDRSBpci); 3457 break; 3458 case ARM::t2PLDi12: 3459 Inst.setOpcode(ARM::t2PLDpci); 3460 break; 3461 case ARM::t2PLIi12: 3462 Inst.setOpcode(ARM::t2PLIpci); 3463 break; 3464 default: 3465 return MCDisassembler::Fail; 3466 } 3467 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3468 } 3469 3470 if (Rt == 15) { 3471 switch (Inst.getOpcode()) { 3472 case ARM::t2LDRSHi12: 3473 return MCDisassembler::Fail; 3474 case ARM::t2LDRHi12: 3475 Inst.setOpcode(ARM::t2PLDWi12); 3476 break; 3477 case ARM::t2LDRSBi12: 3478 Inst.setOpcode(ARM::t2PLIi12); 3479 break; 3480 default: 3481 break; 3482 } 3483 } 3484 3485 switch (Inst.getOpcode()) { 3486 case ARM::t2PLDi12: 3487 break; 3488 case ARM::t2PLIi12: 3489 if (!hasV7Ops) 3490 return MCDisassembler::Fail; 3491 break; 3492 case ARM::t2PLDWi12: 3493 if (!hasV7Ops || !hasMP) 3494 return MCDisassembler::Fail; 3495 break; 3496 default: 3497 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3498 return MCDisassembler::Fail; 3499 } 3500 3501 if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder))) 3502 return MCDisassembler::Fail; 3503 return S; 3504 } 3505 3506 static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn, 3507 uint64_t Address, const void* Decoder) { 3508 DecodeStatus S = MCDisassembler::Success; 3509 3510 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3511 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3512 unsigned imm = fieldFromInstruction(Insn, 0, 8); 3513 imm |= (Rn << 9); 3514 3515 if (Rn == 15) { 3516 switch (Inst.getOpcode()) { 3517 case ARM::t2LDRT: 3518 Inst.setOpcode(ARM::t2LDRpci); 3519 break; 3520 case ARM::t2LDRBT: 3521 Inst.setOpcode(ARM::t2LDRBpci); 3522 break; 3523 case ARM::t2LDRHT: 3524 Inst.setOpcode(ARM::t2LDRHpci); 3525 break; 3526 case ARM::t2LDRSBT: 3527 Inst.setOpcode(ARM::t2LDRSBpci); 3528 break; 3529 case ARM::t2LDRSHT: 3530 Inst.setOpcode(ARM::t2LDRSHpci); 3531 break; 3532 default: 3533 return MCDisassembler::Fail; 3534 } 3535 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3536 } 3537 3538 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 3539 return MCDisassembler::Fail; 3540 if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder))) 3541 return MCDisassembler::Fail; 3542 return S; 3543 } 3544 3545 static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn, 3546 uint64_t Address, const void* Decoder) { 3547 DecodeStatus S = MCDisassembler::Success; 3548 3549 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3550 unsigned U = fieldFromInstruction(Insn, 23, 1); 3551 int imm = fieldFromInstruction(Insn, 0, 12); 3552 3553 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() 3554 .getFeatureBits(); 3555 bool hasV7Ops = (featureBits & ARM::HasV7Ops); 3556 3557 if (Rt == 15) { 3558 switch (Inst.getOpcode()) { 3559 case ARM::t2LDRBpci: 3560 case ARM::t2LDRHpci: 3561 Inst.setOpcode(ARM::t2PLDpci); 3562 break; 3563 case ARM::t2LDRSBpci: 3564 Inst.setOpcode(ARM::t2PLIpci); 3565 break; 3566 case ARM::t2LDRSHpci: 3567 return MCDisassembler::Fail; 3568 default: 3569 break; 3570 } 3571 } 3572 3573 switch(Inst.getOpcode()) { 3574 case ARM::t2PLDpci: 3575 break; 3576 case ARM::t2PLIpci: 3577 if (!hasV7Ops) 3578 return MCDisassembler::Fail; 3579 break; 3580 default: 3581 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3582 return MCDisassembler::Fail; 3583 } 3584 3585 if (!U) { 3586 // Special case for #-0. 3587 if (imm == 0) 3588 imm = INT32_MIN; 3589 else 3590 imm = -imm; 3591 } 3592 Inst.addOperand(MCOperand::CreateImm(imm)); 3593 3594 return S; 3595 } 3596 3597 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val, 3598 uint64_t Address, const void *Decoder) { 3599 if (Val == 0) 3600 Inst.addOperand(MCOperand::CreateImm(INT32_MIN)); 3601 else { 3602 int imm = Val & 0xFF; 3603 3604 if (!(Val & 0x100)) imm *= -1; 3605 Inst.addOperand(MCOperand::CreateImm(imm * 4)); 3606 } 3607 3608 return MCDisassembler::Success; 3609 } 3610 3611 static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val, 3612 uint64_t Address, const void *Decoder) { 3613 DecodeStatus S = MCDisassembler::Success; 3614 3615 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3616 unsigned imm = fieldFromInstruction(Val, 0, 9); 3617 3618 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3619 return MCDisassembler::Fail; 3620 if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder))) 3621 return MCDisassembler::Fail; 3622 3623 return S; 3624 } 3625 3626 static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val, 3627 uint64_t Address, const void *Decoder) { 3628 DecodeStatus S = MCDisassembler::Success; 3629 3630 unsigned Rn = fieldFromInstruction(Val, 8, 4); 3631 unsigned imm = fieldFromInstruction(Val, 0, 8); 3632 3633 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 3634 return MCDisassembler::Fail; 3635 3636 Inst.addOperand(MCOperand::CreateImm(imm)); 3637 3638 return S; 3639 } 3640 3641 static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val, 3642 uint64_t Address, const void *Decoder) { 3643 int imm = Val & 0xFF; 3644 if (Val == 0) 3645 imm = INT32_MIN; 3646 else if (!(Val & 0x100)) 3647 imm *= -1; 3648 Inst.addOperand(MCOperand::CreateImm(imm)); 3649 3650 return MCDisassembler::Success; 3651 } 3652 3653 3654 static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val, 3655 uint64_t Address, const void *Decoder) { 3656 DecodeStatus S = MCDisassembler::Success; 3657 3658 unsigned Rn = fieldFromInstruction(Val, 9, 4); 3659 unsigned imm = fieldFromInstruction(Val, 0, 9); 3660 3661 // Thumb stores cannot use PC as dest register. 3662 switch (Inst.getOpcode()) { 3663 case ARM::t2STRT: 3664 case ARM::t2STRBT: 3665 case ARM::t2STRHT: 3666 case ARM::t2STRi8: 3667 case ARM::t2STRHi8: 3668 case ARM::t2STRBi8: 3669 if (Rn == 15) 3670 return MCDisassembler::Fail; 3671 break; 3672 default: 3673 break; 3674 } 3675 3676 // Some instructions always use an additive offset. 3677 switch (Inst.getOpcode()) { 3678 case ARM::t2LDRT: 3679 case ARM::t2LDRBT: 3680 case ARM::t2LDRHT: 3681 case ARM::t2LDRSBT: 3682 case ARM::t2LDRSHT: 3683 case ARM::t2STRT: 3684 case ARM::t2STRBT: 3685 case ARM::t2STRHT: 3686 imm |= 0x100; 3687 break; 3688 default: 3689 break; 3690 } 3691 3692 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3693 return MCDisassembler::Fail; 3694 if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder))) 3695 return MCDisassembler::Fail; 3696 3697 return S; 3698 } 3699 3700 static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn, 3701 uint64_t Address, const void *Decoder) { 3702 DecodeStatus S = MCDisassembler::Success; 3703 3704 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 3705 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3706 unsigned addr = fieldFromInstruction(Insn, 0, 8); 3707 addr |= fieldFromInstruction(Insn, 9, 1) << 8; 3708 addr |= Rn << 9; 3709 unsigned load = fieldFromInstruction(Insn, 20, 1); 3710 3711 if (Rn == 15) { 3712 switch (Inst.getOpcode()) { 3713 case ARM::t2LDR_PRE: 3714 case ARM::t2LDR_POST: 3715 Inst.setOpcode(ARM::t2LDRpci); 3716 break; 3717 case ARM::t2LDRB_PRE: 3718 case ARM::t2LDRB_POST: 3719 Inst.setOpcode(ARM::t2LDRBpci); 3720 break; 3721 case ARM::t2LDRH_PRE: 3722 case ARM::t2LDRH_POST: 3723 Inst.setOpcode(ARM::t2LDRHpci); 3724 break; 3725 case ARM::t2LDRSB_PRE: 3726 case ARM::t2LDRSB_POST: 3727 if (Rt == 15) 3728 Inst.setOpcode(ARM::t2PLIpci); 3729 else 3730 Inst.setOpcode(ARM::t2LDRSBpci); 3731 break; 3732 case ARM::t2LDRSH_PRE: 3733 case ARM::t2LDRSH_POST: 3734 Inst.setOpcode(ARM::t2LDRSHpci); 3735 break; 3736 default: 3737 return MCDisassembler::Fail; 3738 } 3739 return DecodeT2LoadLabel(Inst, Insn, Address, Decoder); 3740 } 3741 3742 if (!load) { 3743 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3744 return MCDisassembler::Fail; 3745 } 3746 3747 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 3748 return MCDisassembler::Fail; 3749 3750 if (load) { 3751 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3752 return MCDisassembler::Fail; 3753 } 3754 3755 if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder))) 3756 return MCDisassembler::Fail; 3757 3758 return S; 3759 } 3760 3761 static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val, 3762 uint64_t Address, const void *Decoder) { 3763 DecodeStatus S = MCDisassembler::Success; 3764 3765 unsigned Rn = fieldFromInstruction(Val, 13, 4); 3766 unsigned imm = fieldFromInstruction(Val, 0, 12); 3767 3768 // Thumb stores cannot use PC as dest register. 3769 switch (Inst.getOpcode()) { 3770 case ARM::t2STRi12: 3771 case ARM::t2STRBi12: 3772 case ARM::t2STRHi12: 3773 if (Rn == 15) 3774 return MCDisassembler::Fail; 3775 default: 3776 break; 3777 } 3778 3779 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3780 return MCDisassembler::Fail; 3781 Inst.addOperand(MCOperand::CreateImm(imm)); 3782 3783 return S; 3784 } 3785 3786 3787 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn, 3788 uint64_t Address, const void *Decoder) { 3789 unsigned imm = fieldFromInstruction(Insn, 0, 7); 3790 3791 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3792 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3793 Inst.addOperand(MCOperand::CreateImm(imm)); 3794 3795 return MCDisassembler::Success; 3796 } 3797 3798 static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn, 3799 uint64_t Address, const void *Decoder) { 3800 DecodeStatus S = MCDisassembler::Success; 3801 3802 if (Inst.getOpcode() == ARM::tADDrSP) { 3803 unsigned Rdm = fieldFromInstruction(Insn, 0, 3); 3804 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3; 3805 3806 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3807 return MCDisassembler::Fail; 3808 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3809 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder))) 3810 return MCDisassembler::Fail; 3811 } else if (Inst.getOpcode() == ARM::tADDspr) { 3812 unsigned Rm = fieldFromInstruction(Insn, 3, 4); 3813 3814 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3815 Inst.addOperand(MCOperand::CreateReg(ARM::SP)); 3816 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 3817 return MCDisassembler::Fail; 3818 } 3819 3820 return S; 3821 } 3822 3823 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn, 3824 uint64_t Address, const void *Decoder) { 3825 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2; 3826 unsigned flags = fieldFromInstruction(Insn, 0, 3); 3827 3828 Inst.addOperand(MCOperand::CreateImm(imod)); 3829 Inst.addOperand(MCOperand::CreateImm(flags)); 3830 3831 return MCDisassembler::Success; 3832 } 3833 3834 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn, 3835 uint64_t Address, const void *Decoder) { 3836 DecodeStatus S = MCDisassembler::Success; 3837 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3838 unsigned add = fieldFromInstruction(Insn, 4, 1); 3839 3840 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) 3841 return MCDisassembler::Fail; 3842 Inst.addOperand(MCOperand::CreateImm(add)); 3843 3844 return S; 3845 } 3846 3847 static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val, 3848 uint64_t Address, const void *Decoder) { 3849 // Val is passed in as S:J1:J2:imm10H:imm10L:'0' 3850 // Note only one trailing zero not two. Also the J1 and J2 values are from 3851 // the encoded instruction. So here change to I1 and I2 values via: 3852 // I1 = NOT(J1 EOR S); 3853 // I2 = NOT(J2 EOR S); 3854 // and build the imm32 with two trailing zeros as documented: 3855 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32); 3856 unsigned S = (Val >> 23) & 1; 3857 unsigned J1 = (Val >> 22) & 1; 3858 unsigned J2 = (Val >> 21) & 1; 3859 unsigned I1 = !(J1 ^ S); 3860 unsigned I2 = !(J2 ^ S); 3861 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3862 int imm32 = SignExtend32<25>(tmp << 1); 3863 3864 if (!tryAddingSymbolicOperand(Address, 3865 (Address & ~2u) + imm32 + 4, 3866 true, 4, Inst, Decoder)) 3867 Inst.addOperand(MCOperand::CreateImm(imm32)); 3868 return MCDisassembler::Success; 3869 } 3870 3871 static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val, 3872 uint64_t Address, const void *Decoder) { 3873 if (Val == 0xA || Val == 0xB) 3874 return MCDisassembler::Fail; 3875 3876 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() 3877 .getFeatureBits(); 3878 if ((featureBits & ARM::HasV8Ops) && !(Val == 14 || Val == 15)) 3879 return MCDisassembler::Fail; 3880 3881 Inst.addOperand(MCOperand::CreateImm(Val)); 3882 return MCDisassembler::Success; 3883 } 3884 3885 static DecodeStatus 3886 DecodeThumbTableBranch(MCInst &Inst, unsigned Insn, 3887 uint64_t Address, const void *Decoder) { 3888 DecodeStatus S = MCDisassembler::Success; 3889 3890 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 3891 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 3892 3893 if (Rn == ARM::SP) S = MCDisassembler::SoftFail; 3894 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 3895 return MCDisassembler::Fail; 3896 if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder))) 3897 return MCDisassembler::Fail; 3898 return S; 3899 } 3900 3901 static DecodeStatus 3902 DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn, 3903 uint64_t Address, const void *Decoder) { 3904 DecodeStatus S = MCDisassembler::Success; 3905 3906 unsigned pred = fieldFromInstruction(Insn, 22, 4); 3907 if (pred == 0xE || pred == 0xF) { 3908 unsigned opc = fieldFromInstruction(Insn, 4, 28); 3909 switch (opc) { 3910 default: 3911 return MCDisassembler::Fail; 3912 case 0xf3bf8f4: 3913 Inst.setOpcode(ARM::t2DSB); 3914 break; 3915 case 0xf3bf8f5: 3916 Inst.setOpcode(ARM::t2DMB); 3917 break; 3918 case 0xf3bf8f6: 3919 Inst.setOpcode(ARM::t2ISB); 3920 break; 3921 } 3922 3923 unsigned imm = fieldFromInstruction(Insn, 0, 4); 3924 return DecodeMemBarrierOption(Inst, imm, Address, Decoder); 3925 } 3926 3927 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1; 3928 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19; 3929 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18; 3930 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12; 3931 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20; 3932 3933 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder))) 3934 return MCDisassembler::Fail; 3935 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 3936 return MCDisassembler::Fail; 3937 3938 return S; 3939 } 3940 3941 // Decode a shifted immediate operand. These basically consist 3942 // of an 8-bit value, and a 4-bit directive that specifies either 3943 // a splat operation or a rotation. 3944 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val, 3945 uint64_t Address, const void *Decoder) { 3946 unsigned ctrl = fieldFromInstruction(Val, 10, 2); 3947 if (ctrl == 0) { 3948 unsigned byte = fieldFromInstruction(Val, 8, 2); 3949 unsigned imm = fieldFromInstruction(Val, 0, 8); 3950 switch (byte) { 3951 case 0: 3952 Inst.addOperand(MCOperand::CreateImm(imm)); 3953 break; 3954 case 1: 3955 Inst.addOperand(MCOperand::CreateImm((imm << 16) | imm)); 3956 break; 3957 case 2: 3958 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 8))); 3959 break; 3960 case 3: 3961 Inst.addOperand(MCOperand::CreateImm((imm << 24) | (imm << 16) | 3962 (imm << 8) | imm)); 3963 break; 3964 } 3965 } else { 3966 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80; 3967 unsigned rot = fieldFromInstruction(Val, 7, 5); 3968 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31)); 3969 Inst.addOperand(MCOperand::CreateImm(imm)); 3970 } 3971 3972 return MCDisassembler::Success; 3973 } 3974 3975 static DecodeStatus 3976 DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val, 3977 uint64_t Address, const void *Decoder){ 3978 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4, 3979 true, 2, Inst, Decoder)) 3980 Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1))); 3981 return MCDisassembler::Success; 3982 } 3983 3984 static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, 3985 uint64_t Address, const void *Decoder){ 3986 // Val is passed in as S:J1:J2:imm10:imm11 3987 // Note no trailing zero after imm11. Also the J1 and J2 values are from 3988 // the encoded instruction. So here change to I1 and I2 values via: 3989 // I1 = NOT(J1 EOR S); 3990 // I2 = NOT(J2 EOR S); 3991 // and build the imm32 with one trailing zero as documented: 3992 // imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32); 3993 unsigned S = (Val >> 23) & 1; 3994 unsigned J1 = (Val >> 22) & 1; 3995 unsigned J2 = (Val >> 21) & 1; 3996 unsigned I1 = !(J1 ^ S); 3997 unsigned I2 = !(J2 ^ S); 3998 unsigned tmp = (Val & ~0x600000) | (I1 << 22) | (I2 << 21); 3999 int imm32 = SignExtend32<25>(tmp << 1); 4000 4001 if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4, 4002 true, 4, Inst, Decoder)) 4003 Inst.addOperand(MCOperand::CreateImm(imm32)); 4004 return MCDisassembler::Success; 4005 } 4006 4007 static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, 4008 uint64_t Address, const void *Decoder) { 4009 if (Val & ~0xf) 4010 return MCDisassembler::Fail; 4011 4012 Inst.addOperand(MCOperand::CreateImm(Val)); 4013 return MCDisassembler::Success; 4014 } 4015 4016 static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val, 4017 uint64_t Address, const void *Decoder) { 4018 if (Val & ~0xf) 4019 return MCDisassembler::Fail; 4020 4021 Inst.addOperand(MCOperand::CreateImm(Val)); 4022 return MCDisassembler::Success; 4023 } 4024 4025 static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val, 4026 uint64_t Address, const void *Decoder) { 4027 DecodeStatus S = MCDisassembler::Success; 4028 uint64_t FeatureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo() 4029 .getFeatureBits(); 4030 if (FeatureBits & ARM::FeatureMClass) { 4031 unsigned ValLow = Val & 0xff; 4032 4033 // Validate the SYSm value first. 4034 switch (ValLow) { 4035 case 0: // apsr 4036 case 1: // iapsr 4037 case 2: // eapsr 4038 case 3: // xpsr 4039 case 5: // ipsr 4040 case 6: // epsr 4041 case 7: // iepsr 4042 case 8: // msp 4043 case 9: // psp 4044 case 16: // primask 4045 case 20: // control 4046 break; 4047 case 17: // basepri 4048 case 18: // basepri_max 4049 case 19: // faultmask 4050 if (!(FeatureBits & ARM::HasV7Ops)) 4051 // Values basepri, basepri_max and faultmask are only valid for v7m. 4052 return MCDisassembler::Fail; 4053 break; 4054 default: 4055 return MCDisassembler::Fail; 4056 } 4057 4058 if (Inst.getOpcode() == ARM::t2MSR_M) { 4059 unsigned Mask = fieldFromInstruction(Val, 10, 2); 4060 if (!(FeatureBits & ARM::HasV7Ops)) { 4061 // The ARMv6-M MSR bits {11-10} can be only 0b10, other values are 4062 // unpredictable. 4063 if (Mask != 2) 4064 S = MCDisassembler::SoftFail; 4065 } 4066 else { 4067 // The ARMv7-M architecture stores an additional 2-bit mask value in 4068 // MSR bits {11-10}. The mask is used only with apsr, iapsr, eapsr and 4069 // xpsr, it has to be 0b10 in other cases. Bit mask{1} indicates if 4070 // the NZCVQ bits should be moved by the instruction. Bit mask{0} 4071 // indicates the move for the GE{3:0} bits, the mask{0} bit can be set 4072 // only if the processor includes the DSP extension. 4073 if (Mask == 0 || (Mask != 2 && ValLow > 3) || 4074 (!(FeatureBits & ARM::FeatureDSPThumb2) && (Mask & 1))) 4075 S = MCDisassembler::SoftFail; 4076 } 4077 } 4078 } else { 4079 // A/R class 4080 if (Val == 0) 4081 return MCDisassembler::Fail; 4082 } 4083 Inst.addOperand(MCOperand::CreateImm(Val)); 4084 return S; 4085 } 4086 4087 static DecodeStatus DecodeBankedReg(MCInst &Inst, unsigned Val, 4088 uint64_t Address, const void *Decoder) { 4089 4090 unsigned R = fieldFromInstruction(Val, 5, 1); 4091 unsigned SysM = fieldFromInstruction(Val, 0, 5); 4092 4093 // The table of encodings for these banked registers comes from B9.2.3 of the 4094 // ARM ARM. There are patterns, but nothing regular enough to make this logic 4095 // neater. So by fiat, these values are UNPREDICTABLE: 4096 if (!R) { 4097 if (SysM == 0x7 || SysM == 0xf || SysM == 0x18 || SysM == 0x19 || 4098 SysM == 0x1a || SysM == 0x1b) 4099 return MCDisassembler::SoftFail; 4100 } else { 4101 if (SysM != 0xe && SysM != 0x10 && SysM != 0x12 && SysM != 0x14 && 4102 SysM != 0x16 && SysM != 0x1c && SysM != 0x1e) 4103 return MCDisassembler::SoftFail; 4104 } 4105 4106 Inst.addOperand(MCOperand::CreateImm(Val)); 4107 return MCDisassembler::Success; 4108 } 4109 4110 static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn, 4111 uint64_t Address, const void *Decoder) { 4112 DecodeStatus S = MCDisassembler::Success; 4113 4114 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4115 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4116 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4117 4118 if (Rn == 0xF) 4119 S = MCDisassembler::SoftFail; 4120 4121 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4122 return MCDisassembler::Fail; 4123 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4124 return MCDisassembler::Fail; 4125 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4126 return MCDisassembler::Fail; 4127 4128 return S; 4129 } 4130 4131 static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn, 4132 uint64_t Address, const void *Decoder){ 4133 DecodeStatus S = MCDisassembler::Success; 4134 4135 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4136 unsigned Rt = fieldFromInstruction(Insn, 0, 4); 4137 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4138 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4139 4140 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder))) 4141 return MCDisassembler::Fail; 4142 4143 if (Rn == 0xF || Rd == Rn || Rd == Rt || Rd == Rt+1) 4144 S = MCDisassembler::SoftFail; 4145 4146 if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder))) 4147 return MCDisassembler::Fail; 4148 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4149 return MCDisassembler::Fail; 4150 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4151 return MCDisassembler::Fail; 4152 4153 return S; 4154 } 4155 4156 static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn, 4157 uint64_t Address, const void *Decoder) { 4158 DecodeStatus S = MCDisassembler::Success; 4159 4160 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4161 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4162 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4163 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4164 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4165 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4166 4167 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4168 4169 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4170 return MCDisassembler::Fail; 4171 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4172 return MCDisassembler::Fail; 4173 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4174 return MCDisassembler::Fail; 4175 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4176 return MCDisassembler::Fail; 4177 4178 return S; 4179 } 4180 4181 static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn, 4182 uint64_t Address, const void *Decoder) { 4183 DecodeStatus S = MCDisassembler::Success; 4184 4185 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4186 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4187 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4188 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4189 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4190 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4191 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4192 4193 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4194 if (Rm == 0xF) S = MCDisassembler::SoftFail; 4195 4196 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4197 return MCDisassembler::Fail; 4198 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4199 return MCDisassembler::Fail; 4200 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4201 return MCDisassembler::Fail; 4202 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4203 return MCDisassembler::Fail; 4204 4205 return S; 4206 } 4207 4208 4209 static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn, 4210 uint64_t Address, const void *Decoder) { 4211 DecodeStatus S = MCDisassembler::Success; 4212 4213 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4214 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4215 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4216 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4217 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4218 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4219 4220 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4221 4222 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4223 return MCDisassembler::Fail; 4224 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4225 return MCDisassembler::Fail; 4226 if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder))) 4227 return MCDisassembler::Fail; 4228 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4229 return MCDisassembler::Fail; 4230 4231 return S; 4232 } 4233 4234 static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn, 4235 uint64_t Address, const void *Decoder) { 4236 DecodeStatus S = MCDisassembler::Success; 4237 4238 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4239 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4240 unsigned imm = fieldFromInstruction(Insn, 0, 12); 4241 imm |= fieldFromInstruction(Insn, 16, 4) << 13; 4242 imm |= fieldFromInstruction(Insn, 23, 1) << 12; 4243 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4244 4245 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail; 4246 4247 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4248 return MCDisassembler::Fail; 4249 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder))) 4250 return MCDisassembler::Fail; 4251 if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder))) 4252 return MCDisassembler::Fail; 4253 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4254 return MCDisassembler::Fail; 4255 4256 return S; 4257 } 4258 4259 static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn, 4260 uint64_t Address, const void *Decoder) { 4261 DecodeStatus S = MCDisassembler::Success; 4262 4263 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4264 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4265 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4266 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4267 unsigned size = fieldFromInstruction(Insn, 10, 2); 4268 4269 unsigned align = 0; 4270 unsigned index = 0; 4271 switch (size) { 4272 default: 4273 return MCDisassembler::Fail; 4274 case 0: 4275 if (fieldFromInstruction(Insn, 4, 1)) 4276 return MCDisassembler::Fail; // UNDEFINED 4277 index = fieldFromInstruction(Insn, 5, 3); 4278 break; 4279 case 1: 4280 if (fieldFromInstruction(Insn, 5, 1)) 4281 return MCDisassembler::Fail; // UNDEFINED 4282 index = fieldFromInstruction(Insn, 6, 2); 4283 if (fieldFromInstruction(Insn, 4, 1)) 4284 align = 2; 4285 break; 4286 case 2: 4287 if (fieldFromInstruction(Insn, 6, 1)) 4288 return MCDisassembler::Fail; // UNDEFINED 4289 index = fieldFromInstruction(Insn, 7, 1); 4290 4291 switch (fieldFromInstruction(Insn, 4, 2)) { 4292 case 0 : 4293 align = 0; break; 4294 case 3: 4295 align = 4; break; 4296 default: 4297 return MCDisassembler::Fail; 4298 } 4299 break; 4300 } 4301 4302 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4303 return MCDisassembler::Fail; 4304 if (Rm != 0xF) { // Writeback 4305 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4306 return MCDisassembler::Fail; 4307 } 4308 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4309 return MCDisassembler::Fail; 4310 Inst.addOperand(MCOperand::CreateImm(align)); 4311 if (Rm != 0xF) { 4312 if (Rm != 0xD) { 4313 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4314 return MCDisassembler::Fail; 4315 } else 4316 Inst.addOperand(MCOperand::CreateReg(0)); 4317 } 4318 4319 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4320 return MCDisassembler::Fail; 4321 Inst.addOperand(MCOperand::CreateImm(index)); 4322 4323 return S; 4324 } 4325 4326 static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn, 4327 uint64_t Address, const void *Decoder) { 4328 DecodeStatus S = MCDisassembler::Success; 4329 4330 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4331 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4332 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4333 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4334 unsigned size = fieldFromInstruction(Insn, 10, 2); 4335 4336 unsigned align = 0; 4337 unsigned index = 0; 4338 switch (size) { 4339 default: 4340 return MCDisassembler::Fail; 4341 case 0: 4342 if (fieldFromInstruction(Insn, 4, 1)) 4343 return MCDisassembler::Fail; // UNDEFINED 4344 index = fieldFromInstruction(Insn, 5, 3); 4345 break; 4346 case 1: 4347 if (fieldFromInstruction(Insn, 5, 1)) 4348 return MCDisassembler::Fail; // UNDEFINED 4349 index = fieldFromInstruction(Insn, 6, 2); 4350 if (fieldFromInstruction(Insn, 4, 1)) 4351 align = 2; 4352 break; 4353 case 2: 4354 if (fieldFromInstruction(Insn, 6, 1)) 4355 return MCDisassembler::Fail; // UNDEFINED 4356 index = fieldFromInstruction(Insn, 7, 1); 4357 4358 switch (fieldFromInstruction(Insn, 4, 2)) { 4359 case 0: 4360 align = 0; break; 4361 case 3: 4362 align = 4; break; 4363 default: 4364 return MCDisassembler::Fail; 4365 } 4366 break; 4367 } 4368 4369 if (Rm != 0xF) { // Writeback 4370 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4371 return MCDisassembler::Fail; 4372 } 4373 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4374 return MCDisassembler::Fail; 4375 Inst.addOperand(MCOperand::CreateImm(align)); 4376 if (Rm != 0xF) { 4377 if (Rm != 0xD) { 4378 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4379 return MCDisassembler::Fail; 4380 } else 4381 Inst.addOperand(MCOperand::CreateReg(0)); 4382 } 4383 4384 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4385 return MCDisassembler::Fail; 4386 Inst.addOperand(MCOperand::CreateImm(index)); 4387 4388 return S; 4389 } 4390 4391 4392 static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn, 4393 uint64_t Address, const void *Decoder) { 4394 DecodeStatus S = MCDisassembler::Success; 4395 4396 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4397 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4398 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4399 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4400 unsigned size = fieldFromInstruction(Insn, 10, 2); 4401 4402 unsigned align = 0; 4403 unsigned index = 0; 4404 unsigned inc = 1; 4405 switch (size) { 4406 default: 4407 return MCDisassembler::Fail; 4408 case 0: 4409 index = fieldFromInstruction(Insn, 5, 3); 4410 if (fieldFromInstruction(Insn, 4, 1)) 4411 align = 2; 4412 break; 4413 case 1: 4414 index = fieldFromInstruction(Insn, 6, 2); 4415 if (fieldFromInstruction(Insn, 4, 1)) 4416 align = 4; 4417 if (fieldFromInstruction(Insn, 5, 1)) 4418 inc = 2; 4419 break; 4420 case 2: 4421 if (fieldFromInstruction(Insn, 5, 1)) 4422 return MCDisassembler::Fail; // UNDEFINED 4423 index = fieldFromInstruction(Insn, 7, 1); 4424 if (fieldFromInstruction(Insn, 4, 1) != 0) 4425 align = 8; 4426 if (fieldFromInstruction(Insn, 6, 1)) 4427 inc = 2; 4428 break; 4429 } 4430 4431 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4432 return MCDisassembler::Fail; 4433 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4434 return MCDisassembler::Fail; 4435 if (Rm != 0xF) { // Writeback 4436 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4437 return MCDisassembler::Fail; 4438 } 4439 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4440 return MCDisassembler::Fail; 4441 Inst.addOperand(MCOperand::CreateImm(align)); 4442 if (Rm != 0xF) { 4443 if (Rm != 0xD) { 4444 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4445 return MCDisassembler::Fail; 4446 } else 4447 Inst.addOperand(MCOperand::CreateReg(0)); 4448 } 4449 4450 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4451 return MCDisassembler::Fail; 4452 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4453 return MCDisassembler::Fail; 4454 Inst.addOperand(MCOperand::CreateImm(index)); 4455 4456 return S; 4457 } 4458 4459 static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn, 4460 uint64_t Address, const void *Decoder) { 4461 DecodeStatus S = MCDisassembler::Success; 4462 4463 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4464 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4465 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4466 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4467 unsigned size = fieldFromInstruction(Insn, 10, 2); 4468 4469 unsigned align = 0; 4470 unsigned index = 0; 4471 unsigned inc = 1; 4472 switch (size) { 4473 default: 4474 return MCDisassembler::Fail; 4475 case 0: 4476 index = fieldFromInstruction(Insn, 5, 3); 4477 if (fieldFromInstruction(Insn, 4, 1)) 4478 align = 2; 4479 break; 4480 case 1: 4481 index = fieldFromInstruction(Insn, 6, 2); 4482 if (fieldFromInstruction(Insn, 4, 1)) 4483 align = 4; 4484 if (fieldFromInstruction(Insn, 5, 1)) 4485 inc = 2; 4486 break; 4487 case 2: 4488 if (fieldFromInstruction(Insn, 5, 1)) 4489 return MCDisassembler::Fail; // UNDEFINED 4490 index = fieldFromInstruction(Insn, 7, 1); 4491 if (fieldFromInstruction(Insn, 4, 1) != 0) 4492 align = 8; 4493 if (fieldFromInstruction(Insn, 6, 1)) 4494 inc = 2; 4495 break; 4496 } 4497 4498 if (Rm != 0xF) { // Writeback 4499 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4500 return MCDisassembler::Fail; 4501 } 4502 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4503 return MCDisassembler::Fail; 4504 Inst.addOperand(MCOperand::CreateImm(align)); 4505 if (Rm != 0xF) { 4506 if (Rm != 0xD) { 4507 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4508 return MCDisassembler::Fail; 4509 } else 4510 Inst.addOperand(MCOperand::CreateReg(0)); 4511 } 4512 4513 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4514 return MCDisassembler::Fail; 4515 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4516 return MCDisassembler::Fail; 4517 Inst.addOperand(MCOperand::CreateImm(index)); 4518 4519 return S; 4520 } 4521 4522 4523 static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn, 4524 uint64_t Address, const void *Decoder) { 4525 DecodeStatus S = MCDisassembler::Success; 4526 4527 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4528 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4529 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4530 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4531 unsigned size = fieldFromInstruction(Insn, 10, 2); 4532 4533 unsigned align = 0; 4534 unsigned index = 0; 4535 unsigned inc = 1; 4536 switch (size) { 4537 default: 4538 return MCDisassembler::Fail; 4539 case 0: 4540 if (fieldFromInstruction(Insn, 4, 1)) 4541 return MCDisassembler::Fail; // UNDEFINED 4542 index = fieldFromInstruction(Insn, 5, 3); 4543 break; 4544 case 1: 4545 if (fieldFromInstruction(Insn, 4, 1)) 4546 return MCDisassembler::Fail; // UNDEFINED 4547 index = fieldFromInstruction(Insn, 6, 2); 4548 if (fieldFromInstruction(Insn, 5, 1)) 4549 inc = 2; 4550 break; 4551 case 2: 4552 if (fieldFromInstruction(Insn, 4, 2)) 4553 return MCDisassembler::Fail; // UNDEFINED 4554 index = fieldFromInstruction(Insn, 7, 1); 4555 if (fieldFromInstruction(Insn, 6, 1)) 4556 inc = 2; 4557 break; 4558 } 4559 4560 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4561 return MCDisassembler::Fail; 4562 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4563 return MCDisassembler::Fail; 4564 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4565 return MCDisassembler::Fail; 4566 4567 if (Rm != 0xF) { // Writeback 4568 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4569 return MCDisassembler::Fail; 4570 } 4571 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4572 return MCDisassembler::Fail; 4573 Inst.addOperand(MCOperand::CreateImm(align)); 4574 if (Rm != 0xF) { 4575 if (Rm != 0xD) { 4576 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4577 return MCDisassembler::Fail; 4578 } else 4579 Inst.addOperand(MCOperand::CreateReg(0)); 4580 } 4581 4582 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4583 return MCDisassembler::Fail; 4584 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4585 return MCDisassembler::Fail; 4586 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4587 return MCDisassembler::Fail; 4588 Inst.addOperand(MCOperand::CreateImm(index)); 4589 4590 return S; 4591 } 4592 4593 static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn, 4594 uint64_t Address, const void *Decoder) { 4595 DecodeStatus S = MCDisassembler::Success; 4596 4597 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4598 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4599 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4600 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4601 unsigned size = fieldFromInstruction(Insn, 10, 2); 4602 4603 unsigned align = 0; 4604 unsigned index = 0; 4605 unsigned inc = 1; 4606 switch (size) { 4607 default: 4608 return MCDisassembler::Fail; 4609 case 0: 4610 if (fieldFromInstruction(Insn, 4, 1)) 4611 return MCDisassembler::Fail; // UNDEFINED 4612 index = fieldFromInstruction(Insn, 5, 3); 4613 break; 4614 case 1: 4615 if (fieldFromInstruction(Insn, 4, 1)) 4616 return MCDisassembler::Fail; // UNDEFINED 4617 index = fieldFromInstruction(Insn, 6, 2); 4618 if (fieldFromInstruction(Insn, 5, 1)) 4619 inc = 2; 4620 break; 4621 case 2: 4622 if (fieldFromInstruction(Insn, 4, 2)) 4623 return MCDisassembler::Fail; // UNDEFINED 4624 index = fieldFromInstruction(Insn, 7, 1); 4625 if (fieldFromInstruction(Insn, 6, 1)) 4626 inc = 2; 4627 break; 4628 } 4629 4630 if (Rm != 0xF) { // Writeback 4631 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4632 return MCDisassembler::Fail; 4633 } 4634 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4635 return MCDisassembler::Fail; 4636 Inst.addOperand(MCOperand::CreateImm(align)); 4637 if (Rm != 0xF) { 4638 if (Rm != 0xD) { 4639 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4640 return MCDisassembler::Fail; 4641 } else 4642 Inst.addOperand(MCOperand::CreateReg(0)); 4643 } 4644 4645 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4646 return MCDisassembler::Fail; 4647 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4648 return MCDisassembler::Fail; 4649 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4650 return MCDisassembler::Fail; 4651 Inst.addOperand(MCOperand::CreateImm(index)); 4652 4653 return S; 4654 } 4655 4656 4657 static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn, 4658 uint64_t Address, const void *Decoder) { 4659 DecodeStatus S = MCDisassembler::Success; 4660 4661 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4662 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4663 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4664 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4665 unsigned size = fieldFromInstruction(Insn, 10, 2); 4666 4667 unsigned align = 0; 4668 unsigned index = 0; 4669 unsigned inc = 1; 4670 switch (size) { 4671 default: 4672 return MCDisassembler::Fail; 4673 case 0: 4674 if (fieldFromInstruction(Insn, 4, 1)) 4675 align = 4; 4676 index = fieldFromInstruction(Insn, 5, 3); 4677 break; 4678 case 1: 4679 if (fieldFromInstruction(Insn, 4, 1)) 4680 align = 8; 4681 index = fieldFromInstruction(Insn, 6, 2); 4682 if (fieldFromInstruction(Insn, 5, 1)) 4683 inc = 2; 4684 break; 4685 case 2: 4686 switch (fieldFromInstruction(Insn, 4, 2)) { 4687 case 0: 4688 align = 0; break; 4689 case 3: 4690 return MCDisassembler::Fail; 4691 default: 4692 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4693 } 4694 4695 index = fieldFromInstruction(Insn, 7, 1); 4696 if (fieldFromInstruction(Insn, 6, 1)) 4697 inc = 2; 4698 break; 4699 } 4700 4701 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4702 return MCDisassembler::Fail; 4703 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4704 return MCDisassembler::Fail; 4705 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4706 return MCDisassembler::Fail; 4707 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4708 return MCDisassembler::Fail; 4709 4710 if (Rm != 0xF) { // Writeback 4711 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4712 return MCDisassembler::Fail; 4713 } 4714 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4715 return MCDisassembler::Fail; 4716 Inst.addOperand(MCOperand::CreateImm(align)); 4717 if (Rm != 0xF) { 4718 if (Rm != 0xD) { 4719 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4720 return MCDisassembler::Fail; 4721 } else 4722 Inst.addOperand(MCOperand::CreateReg(0)); 4723 } 4724 4725 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4726 return MCDisassembler::Fail; 4727 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4728 return MCDisassembler::Fail; 4729 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4730 return MCDisassembler::Fail; 4731 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4732 return MCDisassembler::Fail; 4733 Inst.addOperand(MCOperand::CreateImm(index)); 4734 4735 return S; 4736 } 4737 4738 static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn, 4739 uint64_t Address, const void *Decoder) { 4740 DecodeStatus S = MCDisassembler::Success; 4741 4742 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4743 unsigned Rm = fieldFromInstruction(Insn, 0, 4); 4744 unsigned Rd = fieldFromInstruction(Insn, 12, 4); 4745 Rd |= fieldFromInstruction(Insn, 22, 1) << 4; 4746 unsigned size = fieldFromInstruction(Insn, 10, 2); 4747 4748 unsigned align = 0; 4749 unsigned index = 0; 4750 unsigned inc = 1; 4751 switch (size) { 4752 default: 4753 return MCDisassembler::Fail; 4754 case 0: 4755 if (fieldFromInstruction(Insn, 4, 1)) 4756 align = 4; 4757 index = fieldFromInstruction(Insn, 5, 3); 4758 break; 4759 case 1: 4760 if (fieldFromInstruction(Insn, 4, 1)) 4761 align = 8; 4762 index = fieldFromInstruction(Insn, 6, 2); 4763 if (fieldFromInstruction(Insn, 5, 1)) 4764 inc = 2; 4765 break; 4766 case 2: 4767 switch (fieldFromInstruction(Insn, 4, 2)) { 4768 case 0: 4769 align = 0; break; 4770 case 3: 4771 return MCDisassembler::Fail; 4772 default: 4773 align = 4 << fieldFromInstruction(Insn, 4, 2); break; 4774 } 4775 4776 index = fieldFromInstruction(Insn, 7, 1); 4777 if (fieldFromInstruction(Insn, 6, 1)) 4778 inc = 2; 4779 break; 4780 } 4781 4782 if (Rm != 0xF) { // Writeback 4783 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4784 return MCDisassembler::Fail; 4785 } 4786 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder))) 4787 return MCDisassembler::Fail; 4788 Inst.addOperand(MCOperand::CreateImm(align)); 4789 if (Rm != 0xF) { 4790 if (Rm != 0xD) { 4791 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) 4792 return MCDisassembler::Fail; 4793 } else 4794 Inst.addOperand(MCOperand::CreateReg(0)); 4795 } 4796 4797 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder))) 4798 return MCDisassembler::Fail; 4799 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder))) 4800 return MCDisassembler::Fail; 4801 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder))) 4802 return MCDisassembler::Fail; 4803 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder))) 4804 return MCDisassembler::Fail; 4805 Inst.addOperand(MCOperand::CreateImm(index)); 4806 4807 return S; 4808 } 4809 4810 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn, 4811 uint64_t Address, const void *Decoder) { 4812 DecodeStatus S = MCDisassembler::Success; 4813 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4814 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4815 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4816 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4817 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4818 4819 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4820 S = MCDisassembler::SoftFail; 4821 4822 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4823 return MCDisassembler::Fail; 4824 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4825 return MCDisassembler::Fail; 4826 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4827 return MCDisassembler::Fail; 4828 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4829 return MCDisassembler::Fail; 4830 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4831 return MCDisassembler::Fail; 4832 4833 return S; 4834 } 4835 4836 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, 4837 uint64_t Address, const void *Decoder) { 4838 DecodeStatus S = MCDisassembler::Success; 4839 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4840 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4); 4841 unsigned Rm = fieldFromInstruction(Insn, 5, 1); 4842 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4843 Rm |= fieldFromInstruction(Insn, 0, 4) << 1; 4844 4845 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) 4846 S = MCDisassembler::SoftFail; 4847 4848 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder))) 4849 return MCDisassembler::Fail; 4850 if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder))) 4851 return MCDisassembler::Fail; 4852 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder))) 4853 return MCDisassembler::Fail; 4854 if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder))) 4855 return MCDisassembler::Fail; 4856 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 4857 return MCDisassembler::Fail; 4858 4859 return S; 4860 } 4861 4862 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn, 4863 uint64_t Address, const void *Decoder) { 4864 DecodeStatus S = MCDisassembler::Success; 4865 unsigned pred = fieldFromInstruction(Insn, 4, 4); 4866 unsigned mask = fieldFromInstruction(Insn, 0, 4); 4867 4868 if (pred == 0xF) { 4869 pred = 0xE; 4870 S = MCDisassembler::SoftFail; 4871 } 4872 4873 if (mask == 0x0) 4874 return MCDisassembler::Fail; 4875 4876 Inst.addOperand(MCOperand::CreateImm(pred)); 4877 Inst.addOperand(MCOperand::CreateImm(mask)); 4878 return S; 4879 } 4880 4881 static DecodeStatus 4882 DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn, 4883 uint64_t Address, const void *Decoder) { 4884 DecodeStatus S = MCDisassembler::Success; 4885 4886 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4887 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 4888 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4889 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4890 unsigned W = fieldFromInstruction(Insn, 21, 1); 4891 unsigned U = fieldFromInstruction(Insn, 23, 1); 4892 unsigned P = fieldFromInstruction(Insn, 24, 1); 4893 bool writeback = (W == 1) | (P == 0); 4894 4895 addr |= (U << 8) | (Rn << 9); 4896 4897 if (writeback && (Rn == Rt || Rn == Rt2)) 4898 Check(S, MCDisassembler::SoftFail); 4899 if (Rt == Rt2) 4900 Check(S, MCDisassembler::SoftFail); 4901 4902 // Rt 4903 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4904 return MCDisassembler::Fail; 4905 // Rt2 4906 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4907 return MCDisassembler::Fail; 4908 // Writeback operand 4909 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4910 return MCDisassembler::Fail; 4911 // addr 4912 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4913 return MCDisassembler::Fail; 4914 4915 return S; 4916 } 4917 4918 static DecodeStatus 4919 DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn, 4920 uint64_t Address, const void *Decoder) { 4921 DecodeStatus S = MCDisassembler::Success; 4922 4923 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4924 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4); 4925 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4926 unsigned addr = fieldFromInstruction(Insn, 0, 8); 4927 unsigned W = fieldFromInstruction(Insn, 21, 1); 4928 unsigned U = fieldFromInstruction(Insn, 23, 1); 4929 unsigned P = fieldFromInstruction(Insn, 24, 1); 4930 bool writeback = (W == 1) | (P == 0); 4931 4932 addr |= (U << 8) | (Rn << 9); 4933 4934 if (writeback && (Rn == Rt || Rn == Rt2)) 4935 Check(S, MCDisassembler::SoftFail); 4936 4937 // Writeback operand 4938 if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder))) 4939 return MCDisassembler::Fail; 4940 // Rt 4941 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder))) 4942 return MCDisassembler::Fail; 4943 // Rt2 4944 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder))) 4945 return MCDisassembler::Fail; 4946 // addr 4947 if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder))) 4948 return MCDisassembler::Fail; 4949 4950 return S; 4951 } 4952 4953 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn, 4954 uint64_t Address, const void *Decoder) { 4955 unsigned sign1 = fieldFromInstruction(Insn, 21, 1); 4956 unsigned sign2 = fieldFromInstruction(Insn, 23, 1); 4957 if (sign1 != sign2) return MCDisassembler::Fail; 4958 4959 unsigned Val = fieldFromInstruction(Insn, 0, 8); 4960 Val |= fieldFromInstruction(Insn, 12, 3) << 8; 4961 Val |= fieldFromInstruction(Insn, 26, 1) << 11; 4962 Val |= sign1 << 12; 4963 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val))); 4964 4965 return MCDisassembler::Success; 4966 } 4967 4968 static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val, 4969 uint64_t Address, 4970 const void *Decoder) { 4971 DecodeStatus S = MCDisassembler::Success; 4972 4973 // Shift of "asr #32" is not allowed in Thumb2 mode. 4974 if (Val == 0x20) S = MCDisassembler::SoftFail; 4975 Inst.addOperand(MCOperand::CreateImm(Val)); 4976 return S; 4977 } 4978 4979 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn, 4980 uint64_t Address, const void *Decoder) { 4981 unsigned Rt = fieldFromInstruction(Insn, 12, 4); 4982 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4); 4983 unsigned Rn = fieldFromInstruction(Insn, 16, 4); 4984 unsigned pred = fieldFromInstruction(Insn, 28, 4); 4985 4986 if (pred == 0xF) 4987 return DecodeCPSInstruction(Inst, Insn, Address, Decoder); 4988 4989 DecodeStatus S = MCDisassembler::Success; 4990 4991 if (Rt == Rn || Rn == Rt2) 4992 S = MCDisassembler::SoftFail; 4993 4994 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 4995 return MCDisassembler::Fail; 4996 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 4997 return MCDisassembler::Fail; 4998 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 4999 return MCDisassembler::Fail; 5000 if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder))) 5001 return MCDisassembler::Fail; 5002 5003 return S; 5004 } 5005 5006 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn, 5007 uint64_t Address, const void *Decoder) { 5008 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5009 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5010 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5011 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5012 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5013 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5014 unsigned op = fieldFromInstruction(Insn, 5, 1); 5015 5016 DecodeStatus S = MCDisassembler::Success; 5017 5018 // VMOVv2f32 is ambiguous with these decodings. 5019 if (!(imm & 0x38) && cmode == 0xF) { 5020 if (op == 1) return MCDisassembler::Fail; 5021 Inst.setOpcode(ARM::VMOVv2f32); 5022 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 5023 } 5024 5025 if (!(imm & 0x20)) return MCDisassembler::Fail; 5026 5027 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) 5028 return MCDisassembler::Fail; 5029 if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder))) 5030 return MCDisassembler::Fail; 5031 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 5032 5033 return S; 5034 } 5035 5036 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn, 5037 uint64_t Address, const void *Decoder) { 5038 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0); 5039 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4); 5040 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0); 5041 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4); 5042 unsigned imm = fieldFromInstruction(Insn, 16, 6); 5043 unsigned cmode = fieldFromInstruction(Insn, 8, 4); 5044 unsigned op = fieldFromInstruction(Insn, 5, 1); 5045 5046 DecodeStatus S = MCDisassembler::Success; 5047 5048 // VMOVv4f32 is ambiguous with these decodings. 5049 if (!(imm & 0x38) && cmode == 0xF) { 5050 if (op == 1) return MCDisassembler::Fail; 5051 Inst.setOpcode(ARM::VMOVv4f32); 5052 return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder); 5053 } 5054 5055 if (!(imm & 0x20)) return MCDisassembler::Fail; 5056 5057 if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder))) 5058 return MCDisassembler::Fail; 5059 if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder))) 5060 return MCDisassembler::Fail; 5061 Inst.addOperand(MCOperand::CreateImm(64 - imm)); 5062 5063 return S; 5064 } 5065 5066 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val, 5067 uint64_t Address, const void *Decoder) { 5068 DecodeStatus S = MCDisassembler::Success; 5069 5070 unsigned Rn = fieldFromInstruction(Val, 16, 4); 5071 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5072 unsigned Rm = fieldFromInstruction(Val, 0, 4); 5073 Rm |= (fieldFromInstruction(Val, 23, 1) << 4); 5074 unsigned Cond = fieldFromInstruction(Val, 28, 4); 5075 5076 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt) 5077 S = MCDisassembler::SoftFail; 5078 5079 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5080 return MCDisassembler::Fail; 5081 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder))) 5082 return MCDisassembler::Fail; 5083 if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder))) 5084 return MCDisassembler::Fail; 5085 if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder))) 5086 return MCDisassembler::Fail; 5087 if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder))) 5088 return MCDisassembler::Fail; 5089 5090 return S; 5091 } 5092 5093 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val, 5094 uint64_t Address, const void *Decoder) { 5095 5096 DecodeStatus S = MCDisassembler::Success; 5097 5098 unsigned CRm = fieldFromInstruction(Val, 0, 4); 5099 unsigned opc1 = fieldFromInstruction(Val, 4, 4); 5100 unsigned cop = fieldFromInstruction(Val, 8, 4); 5101 unsigned Rt = fieldFromInstruction(Val, 12, 4); 5102 unsigned Rt2 = fieldFromInstruction(Val, 16, 4); 5103 5104 if ((cop & ~0x1) == 0xa) 5105 return MCDisassembler::Fail; 5106 5107 if (Rt == Rt2) 5108 S = MCDisassembler::SoftFail; 5109 5110 Inst.addOperand(MCOperand::CreateImm(cop)); 5111 Inst.addOperand(MCOperand::CreateImm(opc1)); 5112 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder))) 5113 return MCDisassembler::Fail; 5114 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder))) 5115 return MCDisassembler::Fail; 5116 Inst.addOperand(MCOperand::CreateImm(CRm)); 5117 5118 return S; 5119 } 5120 5121