1*f4a2713aSLionel Sambuc // RUN: %clang -target mipsel-unknown-linux -S -o - -emit-llvm %s \ 2*f4a2713aSLionel Sambuc // RUN: | FileCheck %s 3*f4a2713aSLionel Sambuc 4*f4a2713aSLionel Sambuc // This checks that the frontend will accept inline asm memory constraints. 5*f4a2713aSLionel Sambuc 6*f4a2713aSLionel Sambuc int foo() 7*f4a2713aSLionel Sambuc { 8*f4a2713aSLionel Sambuc 9*f4a2713aSLionel Sambuc // 'R': An address that can be used in a non-macro load or stor' 10*f4a2713aSLionel Sambuc // This test will result in the higher and lower nibbles being 11*f4a2713aSLionel Sambuc // switched due to the lwl/lwr instruction pairs. 12*f4a2713aSLionel Sambuc // CHECK: %{{[0-9]+}} = call i32 asm sideeffect "lwl $0, 1 + $1\0A\09lwr $0, 2 + $1\0A\09", "=r,*R"(i32* %{{[0-9,a-f]+}}) #1, 13*f4a2713aSLionel Sambuc 14*f4a2713aSLionel Sambuc int c = 0xffbbccdd; 15*f4a2713aSLionel Sambuc 16*f4a2713aSLionel Sambuc int *p = &c; 17*f4a2713aSLionel Sambuc int out = 0; 18*f4a2713aSLionel Sambuc 19*f4a2713aSLionel Sambuc __asm volatile ( 20*f4a2713aSLionel Sambuc "lwl %0, 1 + %1\n\t" 21*f4a2713aSLionel Sambuc "lwr %0, 2 + %1\n\t" 22*f4a2713aSLionel Sambuc : "=r"(out) 23*f4a2713aSLionel Sambuc : "R"(*p) 24*f4a2713aSLionel Sambuc ); 25*f4a2713aSLionel Sambuc return 0; 26*f4a2713aSLionel Sambuc } 27