1*0a6a1f1dSLionel Sambuc // REQUIRES: aarch64-registered-target
2*0a6a1f1dSLionel Sambuc // RUN: %clang_cc1 -triple aarch64_be-linux-gnu -ffreestanding -emit-llvm -O0 -o - %s | FileCheck --check-prefix IR %s
3*0a6a1f1dSLionel Sambuc // RUN: %clang_cc1 -triple aarch64_be-linux-gnu -ffreestanding -S -O1 -o - %s | FileCheck --check-prefix ARM %s
4*0a6a1f1dSLionel Sambuc
5*0a6a1f1dSLionel Sambuc struct bt3 { signed b2:10; signed b3:10; } b16;
6*0a6a1f1dSLionel Sambuc
7*0a6a1f1dSLionel Sambuc // Get the high 32-bits and then shift appropriately for big-endian.
callee_b0f(struct bt3 bp11)8*0a6a1f1dSLionel Sambuc signed callee_b0f(struct bt3 bp11) {
9*0a6a1f1dSLionel Sambuc // IR: callee_b0f(i64 [[ARG:%.*]])
10*0a6a1f1dSLionel Sambuc // IR: store i64 [[ARG]], i64* [[PTR:%.*]]
11*0a6a1f1dSLionel Sambuc // IR: [[BITCAST:%.*]] = bitcast i64* [[PTR]] to i8*
12*0a6a1f1dSLionel Sambuc // IR: call void @llvm.memcpy.p0i8.p0i8.i64(i8* {{.*}}, i8* [[BITCAST]], i64 4
13*0a6a1f1dSLionel Sambuc // ARM: asr x0, x0, #54
14*0a6a1f1dSLionel Sambuc return bp11.b2;
15*0a6a1f1dSLionel Sambuc }
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