1 //===--- Targets.cpp - Implement -arch option and targets -----------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements construction of a TargetInfo object from a 11 // target triple. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "clang/Basic/TargetInfo.h" 16 #include "clang/Basic/Builtins.h" 17 #include "clang/Basic/Diagnostic.h" 18 #include "clang/Basic/LangOptions.h" 19 #include "clang/Basic/MacroBuilder.h" 20 #include "clang/Basic/TargetBuiltins.h" 21 #include "clang/Basic/TargetOptions.h" 22 #include "llvm/ADT/APFloat.h" 23 #include "llvm/ADT/OwningPtr.h" 24 #include "llvm/ADT/STLExtras.h" 25 #include "llvm/ADT/StringRef.h" 26 #include "llvm/ADT/StringSwitch.h" 27 #include "llvm/ADT/Triple.h" 28 #include "llvm/IR/Type.h" 29 #include "llvm/MC/MCSectionMachO.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include <algorithm> 32 using namespace clang; 33 34 //===----------------------------------------------------------------------===// 35 // Common code shared among targets. 36 //===----------------------------------------------------------------------===// 37 38 /// DefineStd - Define a macro name and standard variants. For example if 39 /// MacroName is "unix", then this will define "__unix", "__unix__", and "unix" 40 /// when in GNU mode. 41 static void DefineStd(MacroBuilder &Builder, StringRef MacroName, 42 const LangOptions &Opts) { 43 assert(MacroName[0] != '_' && "Identifier should be in the user's namespace"); 44 45 // If in GNU mode (e.g. -std=gnu99 but not -std=c99) define the raw identifier 46 // in the user's namespace. 47 if (Opts.GNUMode) 48 Builder.defineMacro(MacroName); 49 50 // Define __unix. 51 Builder.defineMacro("__" + MacroName); 52 53 // Define __unix__. 54 Builder.defineMacro("__" + MacroName + "__"); 55 } 56 57 static void defineCPUMacros(MacroBuilder &Builder, StringRef CPUName, 58 bool Tuning = true) { 59 Builder.defineMacro("__" + CPUName); 60 Builder.defineMacro("__" + CPUName + "__"); 61 if (Tuning) 62 Builder.defineMacro("__tune_" + CPUName + "__"); 63 } 64 65 //===----------------------------------------------------------------------===// 66 // Defines specific to certain operating systems. 67 //===----------------------------------------------------------------------===// 68 69 namespace { 70 template<typename TgtInfo> 71 class OSTargetInfo : public TgtInfo { 72 protected: 73 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 74 MacroBuilder &Builder) const=0; 75 public: 76 OSTargetInfo(const llvm::Triple &Triple) : TgtInfo(Triple) {} 77 virtual void getTargetDefines(const LangOptions &Opts, 78 MacroBuilder &Builder) const { 79 TgtInfo::getTargetDefines(Opts, Builder); 80 getOSDefines(Opts, TgtInfo::getTriple(), Builder); 81 } 82 83 }; 84 } // end anonymous namespace 85 86 87 static void getDarwinDefines(MacroBuilder &Builder, const LangOptions &Opts, 88 const llvm::Triple &Triple, 89 StringRef &PlatformName, 90 VersionTuple &PlatformMinVersion) { 91 Builder.defineMacro("__APPLE_CC__", "6000"); 92 Builder.defineMacro("__APPLE__"); 93 Builder.defineMacro("__MACH__"); 94 Builder.defineMacro("OBJC_NEW_PROPERTIES"); 95 // AddressSanitizer doesn't play well with source fortification, which is on 96 // by default on Darwin. 97 if (Opts.Sanitize.Address) Builder.defineMacro("_FORTIFY_SOURCE", "0"); 98 99 if (!Opts.ObjCAutoRefCount) { 100 // __weak is always defined, for use in blocks and with objc pointers. 101 Builder.defineMacro("__weak", "__attribute__((objc_gc(weak)))"); 102 103 // Darwin defines __strong even in C mode (just to nothing). 104 if (Opts.getGC() != LangOptions::NonGC) 105 Builder.defineMacro("__strong", "__attribute__((objc_gc(strong)))"); 106 else 107 Builder.defineMacro("__strong", ""); 108 109 // __unsafe_unretained is defined to nothing in non-ARC mode. We even 110 // allow this in C, since one might have block pointers in structs that 111 // are used in pure C code and in Objective-C ARC. 112 Builder.defineMacro("__unsafe_unretained", ""); 113 } 114 115 if (Opts.Static) 116 Builder.defineMacro("__STATIC__"); 117 else 118 Builder.defineMacro("__DYNAMIC__"); 119 120 if (Opts.POSIXThreads) 121 Builder.defineMacro("_REENTRANT"); 122 123 // Get the platform type and version number from the triple. 124 unsigned Maj, Min, Rev; 125 if (Triple.isMacOSX()) { 126 Triple.getMacOSXVersion(Maj, Min, Rev); 127 PlatformName = "macosx"; 128 } else { 129 Triple.getOSVersion(Maj, Min, Rev); 130 PlatformName = llvm::Triple::getOSTypeName(Triple.getOS()); 131 } 132 133 // If -target arch-pc-win32-macho option specified, we're 134 // generating code for Win32 ABI. No need to emit 135 // __ENVIRONMENT_XX_OS_VERSION_MIN_REQUIRED__. 136 if (PlatformName == "win32") { 137 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 138 return; 139 } 140 141 // If there's an environment specified in the triple, that means we're dealing 142 // with an embedded variant of some sort and don't want the platform 143 // version-min defines, so only add them if there's not one. 144 if (Triple.getEnvironmentName().empty()) { 145 // Set the appropriate OS version define. 146 if (Triple.isiOS()) { 147 assert(Maj < 10 && Min < 100 && Rev < 100 && "Invalid version!"); 148 char Str[6]; 149 Str[0] = '0' + Maj; 150 Str[1] = '0' + (Min / 10); 151 Str[2] = '0' + (Min % 10); 152 Str[3] = '0' + (Rev / 10); 153 Str[4] = '0' + (Rev % 10); 154 Str[5] = '\0'; 155 Builder.defineMacro("__ENVIRONMENT_IPHONE_OS_VERSION_MIN_REQUIRED__", 156 Str); 157 } else { 158 // Note that the Driver allows versions which aren't representable in the 159 // define (because we only get a single digit for the minor and micro 160 // revision numbers). So, we limit them to the maximum representable 161 // version. 162 assert(Triple.getEnvironmentName().empty() && "Invalid environment!"); 163 assert(Maj < 100 && Min < 100 && Rev < 100 && "Invalid version!"); 164 char Str[5]; 165 Str[0] = '0' + (Maj / 10); 166 Str[1] = '0' + (Maj % 10); 167 Str[2] = '0' + std::min(Min, 9U); 168 Str[3] = '0' + std::min(Rev, 9U); 169 Str[4] = '\0'; 170 Builder.defineMacro("__ENVIRONMENT_MAC_OS_X_VERSION_MIN_REQUIRED__", Str); 171 } 172 } 173 174 PlatformMinVersion = VersionTuple(Maj, Min, Rev); 175 } 176 177 namespace { 178 template<typename Target> 179 class DarwinTargetInfo : public OSTargetInfo<Target> { 180 protected: 181 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 182 MacroBuilder &Builder) const { 183 getDarwinDefines(Builder, Opts, Triple, this->PlatformName, 184 this->PlatformMinVersion); 185 } 186 187 public: 188 DarwinTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 189 this->TLSSupported = Triple.isMacOSX() && !Triple.isMacOSXVersionLT(10, 7); 190 this->MCountName = "\01mcount"; 191 } 192 193 virtual std::string isValidSectionSpecifier(StringRef SR) const { 194 // Let MCSectionMachO validate this. 195 StringRef Segment, Section; 196 unsigned TAA, StubSize; 197 bool HasTAA; 198 return llvm::MCSectionMachO::ParseSectionSpecifier(SR, Segment, Section, 199 TAA, HasTAA, StubSize); 200 } 201 202 virtual const char *getStaticInitSectionSpecifier() const { 203 // FIXME: We should return 0 when building kexts. 204 return "__TEXT,__StaticInit,regular,pure_instructions"; 205 } 206 207 /// Darwin does not support protected visibility. Darwin's "default" 208 /// is very similar to ELF's "protected"; Darwin requires a "weak" 209 /// attribute on declarations that can be dynamically replaced. 210 virtual bool hasProtectedVisibility() const { 211 return false; 212 } 213 }; 214 215 216 // DragonFlyBSD Target 217 template<typename Target> 218 class DragonFlyBSDTargetInfo : public OSTargetInfo<Target> { 219 protected: 220 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 221 MacroBuilder &Builder) const { 222 // DragonFly defines; list based off of gcc output 223 Builder.defineMacro("__DragonFly__"); 224 Builder.defineMacro("__DragonFly_cc_version", "100001"); 225 Builder.defineMacro("__ELF__"); 226 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 227 Builder.defineMacro("__tune_i386__"); 228 DefineStd(Builder, "unix", Opts); 229 } 230 public: 231 DragonFlyBSDTargetInfo(const llvm::Triple &Triple) 232 : OSTargetInfo<Target>(Triple) { 233 this->UserLabelPrefix = ""; 234 235 switch (Triple.getArch()) { 236 default: 237 case llvm::Triple::x86: 238 case llvm::Triple::x86_64: 239 this->MCountName = ".mcount"; 240 break; 241 } 242 } 243 }; 244 245 // FreeBSD Target 246 template<typename Target> 247 class FreeBSDTargetInfo : public OSTargetInfo<Target> { 248 protected: 249 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 250 MacroBuilder &Builder) const { 251 // FreeBSD defines; list based off of gcc output 252 253 unsigned Release = Triple.getOSMajorVersion(); 254 if (Release == 0U) 255 Release = 8; 256 257 Builder.defineMacro("__FreeBSD__", Twine(Release)); 258 Builder.defineMacro("__FreeBSD_cc_version", Twine(Release * 100000U + 1U)); 259 Builder.defineMacro("__KPRINTF_ATTRIBUTE__"); 260 DefineStd(Builder, "unix", Opts); 261 Builder.defineMacro("__ELF__"); 262 263 // On FreeBSD, wchar_t contains the number of the code point as 264 // used by the character set of the locale. These character sets are 265 // not necessarily a superset of ASCII. 266 Builder.defineMacro("__STDC_MB_MIGHT_NEQ_WC__", "1"); 267 } 268 public: 269 FreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 270 this->UserLabelPrefix = ""; 271 272 switch (Triple.getArch()) { 273 default: 274 case llvm::Triple::x86: 275 case llvm::Triple::x86_64: 276 this->MCountName = ".mcount"; 277 break; 278 case llvm::Triple::mips: 279 case llvm::Triple::mipsel: 280 case llvm::Triple::ppc: 281 case llvm::Triple::ppc64: 282 case llvm::Triple::ppc64le: 283 this->MCountName = "_mcount"; 284 break; 285 case llvm::Triple::arm: 286 this->MCountName = "__mcount"; 287 break; 288 } 289 } 290 }; 291 292 // GNU/kFreeBSD Target 293 template<typename Target> 294 class KFreeBSDTargetInfo : public OSTargetInfo<Target> { 295 protected: 296 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 297 MacroBuilder &Builder) const { 298 // GNU/kFreeBSD defines; list based off of gcc output 299 300 DefineStd(Builder, "unix", Opts); 301 Builder.defineMacro("__FreeBSD_kernel__"); 302 Builder.defineMacro("__GLIBC__"); 303 Builder.defineMacro("__ELF__"); 304 if (Opts.POSIXThreads) 305 Builder.defineMacro("_REENTRANT"); 306 if (Opts.CPlusPlus) 307 Builder.defineMacro("_GNU_SOURCE"); 308 } 309 public: 310 KFreeBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 311 this->UserLabelPrefix = ""; 312 } 313 }; 314 315 // Minix Target 316 template<typename Target> 317 class MinixTargetInfo : public OSTargetInfo<Target> { 318 protected: 319 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 320 MacroBuilder &Builder) const { 321 // Minix defines 322 323 Builder.defineMacro("__minix", "3"); 324 Builder.defineMacro("__minix__", "3"); 325 Builder.defineMacro("__unix__"); 326 Builder.defineMacro("__ELF__"); 327 if (Opts.POSIXThreads) 328 Builder.defineMacro("_POSIX_THREADS"); 329 } 330 public: 331 MinixTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 332 this->UserLabelPrefix = ""; 333 } 334 }; 335 336 // Linux target 337 template<typename Target> 338 class LinuxTargetInfo : public OSTargetInfo<Target> { 339 protected: 340 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 341 MacroBuilder &Builder) const { 342 // Linux defines; list based off of gcc output 343 DefineStd(Builder, "unix", Opts); 344 DefineStd(Builder, "linux", Opts); 345 Builder.defineMacro("__gnu_linux__"); 346 Builder.defineMacro("__ELF__"); 347 if (Triple.getEnvironment() == llvm::Triple::Android) 348 Builder.defineMacro("__ANDROID__", "1"); 349 if (Opts.POSIXThreads) 350 Builder.defineMacro("_REENTRANT"); 351 if (Opts.CPlusPlus) 352 Builder.defineMacro("_GNU_SOURCE"); 353 } 354 public: 355 LinuxTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 356 this->UserLabelPrefix = ""; 357 this->WIntType = TargetInfo::UnsignedInt; 358 } 359 360 virtual const char *getStaticInitSectionSpecifier() const { 361 return ".text.startup"; 362 } 363 }; 364 365 // NetBSD Target 366 template<typename Target> 367 class NetBSDTargetInfo : public OSTargetInfo<Target> { 368 protected: 369 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 370 MacroBuilder &Builder) const { 371 // NetBSD defines; list based off of gcc output 372 Builder.defineMacro("__NetBSD__"); 373 Builder.defineMacro("__unix__"); 374 Builder.defineMacro("__ELF__"); 375 if (Opts.POSIXThreads) 376 Builder.defineMacro("_POSIX_THREADS"); 377 } 378 public: 379 NetBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 380 this->UserLabelPrefix = ""; 381 } 382 }; 383 384 // OpenBSD Target 385 template<typename Target> 386 class OpenBSDTargetInfo : public OSTargetInfo<Target> { 387 protected: 388 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 389 MacroBuilder &Builder) const { 390 // OpenBSD defines; list based off of gcc output 391 392 Builder.defineMacro("__OpenBSD__"); 393 DefineStd(Builder, "unix", Opts); 394 Builder.defineMacro("__ELF__"); 395 if (Opts.POSIXThreads) 396 Builder.defineMacro("_REENTRANT"); 397 } 398 public: 399 OpenBSDTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 400 this->UserLabelPrefix = ""; 401 this->TLSSupported = false; 402 403 switch (Triple.getArch()) { 404 default: 405 case llvm::Triple::x86: 406 case llvm::Triple::x86_64: 407 case llvm::Triple::arm: 408 case llvm::Triple::sparc: 409 this->MCountName = "__mcount"; 410 break; 411 case llvm::Triple::mips64: 412 case llvm::Triple::mips64el: 413 case llvm::Triple::ppc: 414 case llvm::Triple::sparcv9: 415 this->MCountName = "_mcount"; 416 break; 417 } 418 } 419 }; 420 421 // Bitrig Target 422 template<typename Target> 423 class BitrigTargetInfo : public OSTargetInfo<Target> { 424 protected: 425 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 426 MacroBuilder &Builder) const { 427 // Bitrig defines; list based off of gcc output 428 429 Builder.defineMacro("__Bitrig__"); 430 DefineStd(Builder, "unix", Opts); 431 Builder.defineMacro("__ELF__"); 432 if (Opts.POSIXThreads) 433 Builder.defineMacro("_REENTRANT"); 434 } 435 public: 436 BitrigTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 437 this->UserLabelPrefix = ""; 438 this->TLSSupported = false; 439 this->MCountName = "__mcount"; 440 } 441 }; 442 443 // PSP Target 444 template<typename Target> 445 class PSPTargetInfo : public OSTargetInfo<Target> { 446 protected: 447 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 448 MacroBuilder &Builder) const { 449 // PSP defines; list based on the output of the pspdev gcc toolchain. 450 Builder.defineMacro("PSP"); 451 Builder.defineMacro("_PSP"); 452 Builder.defineMacro("__psp__"); 453 Builder.defineMacro("__ELF__"); 454 } 455 public: 456 PSPTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 457 this->UserLabelPrefix = ""; 458 } 459 }; 460 461 // PS3 PPU Target 462 template<typename Target> 463 class PS3PPUTargetInfo : public OSTargetInfo<Target> { 464 protected: 465 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 466 MacroBuilder &Builder) const { 467 // PS3 PPU defines. 468 Builder.defineMacro("__PPC__"); 469 Builder.defineMacro("__PPU__"); 470 Builder.defineMacro("__CELLOS_LV2__"); 471 Builder.defineMacro("__ELF__"); 472 Builder.defineMacro("__LP32__"); 473 Builder.defineMacro("_ARCH_PPC64"); 474 Builder.defineMacro("__powerpc64__"); 475 } 476 public: 477 PS3PPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 478 this->UserLabelPrefix = ""; 479 this->LongWidth = this->LongAlign = 32; 480 this->PointerWidth = this->PointerAlign = 32; 481 this->IntMaxType = TargetInfo::SignedLongLong; 482 this->UIntMaxType = TargetInfo::UnsignedLongLong; 483 this->Int64Type = TargetInfo::SignedLongLong; 484 this->SizeType = TargetInfo::UnsignedInt; 485 this->DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 486 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32"; 487 } 488 }; 489 490 // FIXME: Need a real SPU target. 491 // PS3 SPU Target 492 template<typename Target> 493 class PS3SPUTargetInfo : public OSTargetInfo<Target> { 494 protected: 495 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 496 MacroBuilder &Builder) const { 497 // PS3 PPU defines. 498 Builder.defineMacro("__SPU__"); 499 Builder.defineMacro("__ELF__"); 500 } 501 public: 502 PS3SPUTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 503 this->UserLabelPrefix = ""; 504 } 505 }; 506 507 // AuroraUX target 508 template<typename Target> 509 class AuroraUXTargetInfo : public OSTargetInfo<Target> { 510 protected: 511 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 512 MacroBuilder &Builder) const { 513 DefineStd(Builder, "sun", Opts); 514 DefineStd(Builder, "unix", Opts); 515 Builder.defineMacro("__ELF__"); 516 Builder.defineMacro("__svr4__"); 517 Builder.defineMacro("__SVR4"); 518 } 519 public: 520 AuroraUXTargetInfo(const llvm::Triple &Triple) 521 : OSTargetInfo<Target>(Triple) { 522 this->UserLabelPrefix = ""; 523 this->WCharType = this->SignedLong; 524 // FIXME: WIntType should be SignedLong 525 } 526 }; 527 528 // Solaris target 529 template<typename Target> 530 class SolarisTargetInfo : public OSTargetInfo<Target> { 531 protected: 532 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 533 MacroBuilder &Builder) const { 534 DefineStd(Builder, "sun", Opts); 535 DefineStd(Builder, "unix", Opts); 536 Builder.defineMacro("__ELF__"); 537 Builder.defineMacro("__svr4__"); 538 Builder.defineMacro("__SVR4"); 539 // Solaris headers require _XOPEN_SOURCE to be set to 600 for C99 and 540 // newer, but to 500 for everything else. feature_test.h has a check to 541 // ensure that you are not using C99 with an old version of X/Open or C89 542 // with a new version. 543 if (Opts.C99 || Opts.C11) 544 Builder.defineMacro("_XOPEN_SOURCE", "600"); 545 else 546 Builder.defineMacro("_XOPEN_SOURCE", "500"); 547 if (Opts.CPlusPlus) 548 Builder.defineMacro("__C99FEATURES__"); 549 Builder.defineMacro("_LARGEFILE_SOURCE"); 550 Builder.defineMacro("_LARGEFILE64_SOURCE"); 551 Builder.defineMacro("__EXTENSIONS__"); 552 Builder.defineMacro("_REENTRANT"); 553 } 554 public: 555 SolarisTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 556 this->UserLabelPrefix = ""; 557 this->WCharType = this->SignedInt; 558 // FIXME: WIntType should be SignedLong 559 } 560 }; 561 562 // Windows target 563 template<typename Target> 564 class WindowsTargetInfo : public OSTargetInfo<Target> { 565 protected: 566 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 567 MacroBuilder &Builder) const { 568 Builder.defineMacro("_WIN32"); 569 } 570 void getVisualStudioDefines(const LangOptions &Opts, 571 MacroBuilder &Builder) const { 572 if (Opts.CPlusPlus) { 573 if (Opts.RTTI) 574 Builder.defineMacro("_CPPRTTI"); 575 576 if (Opts.Exceptions) 577 Builder.defineMacro("_CPPUNWIND"); 578 } 579 580 if (!Opts.CharIsSigned) 581 Builder.defineMacro("_CHAR_UNSIGNED"); 582 583 // FIXME: POSIXThreads isn't exactly the option this should be defined for, 584 // but it works for now. 585 if (Opts.POSIXThreads) 586 Builder.defineMacro("_MT"); 587 588 if (Opts.MSCVersion != 0) 589 Builder.defineMacro("_MSC_VER", Twine(Opts.MSCVersion)); 590 591 if (Opts.MicrosoftExt) { 592 Builder.defineMacro("_MSC_EXTENSIONS"); 593 594 if (Opts.CPlusPlus11) { 595 Builder.defineMacro("_RVALUE_REFERENCES_V2_SUPPORTED"); 596 Builder.defineMacro("_RVALUE_REFERENCES_SUPPORTED"); 597 Builder.defineMacro("_NATIVE_NULLPTR_SUPPORTED"); 598 } 599 } 600 601 Builder.defineMacro("_INTEGRAL_MAX_BITS", "64"); 602 } 603 604 public: 605 WindowsTargetInfo(const llvm::Triple &Triple) 606 : OSTargetInfo<Target>(Triple) {} 607 }; 608 609 template <typename Target> 610 class NaClTargetInfo : public OSTargetInfo<Target> { 611 protected: 612 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 613 MacroBuilder &Builder) const { 614 if (Opts.POSIXThreads) 615 Builder.defineMacro("_REENTRANT"); 616 if (Opts.CPlusPlus) 617 Builder.defineMacro("_GNU_SOURCE"); 618 619 DefineStd(Builder, "unix", Opts); 620 Builder.defineMacro("__ELF__"); 621 Builder.defineMacro("__native_client__"); 622 } 623 624 public: 625 NaClTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 626 this->UserLabelPrefix = ""; 627 this->LongAlign = 32; 628 this->LongWidth = 32; 629 this->PointerAlign = 32; 630 this->PointerWidth = 32; 631 this->IntMaxType = TargetInfo::SignedLongLong; 632 this->UIntMaxType = TargetInfo::UnsignedLongLong; 633 this->Int64Type = TargetInfo::SignedLongLong; 634 this->DoubleAlign = 64; 635 this->LongDoubleWidth = 64; 636 this->LongDoubleAlign = 64; 637 this->SizeType = TargetInfo::UnsignedInt; 638 this->PtrDiffType = TargetInfo::SignedInt; 639 this->IntPtrType = TargetInfo::SignedInt; 640 // RegParmMax is inherited from the underlying architecture 641 this->LongDoubleFormat = &llvm::APFloat::IEEEdouble; 642 this->DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 643 "f32:32:32-f64:64:64-p:32:32:32-v128:32:32"; 644 } 645 virtual typename Target::CallingConvCheckResult checkCallingConvention( 646 CallingConv CC) const { 647 return CC == CC_PnaclCall ? Target::CCCR_OK : 648 Target::checkCallingConvention(CC); 649 } 650 }; 651 } // end anonymous namespace. 652 653 //===----------------------------------------------------------------------===// 654 // Specific target implementations. 655 //===----------------------------------------------------------------------===// 656 657 namespace { 658 // PPC abstract base class 659 class PPCTargetInfo : public TargetInfo { 660 static const Builtin::Info BuiltinInfo[]; 661 static const char * const GCCRegNames[]; 662 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 663 std::string CPU; 664 665 // Target cpu features. 666 bool HasVSX; 667 668 public: 669 PPCTargetInfo(const llvm::Triple &Triple) 670 : TargetInfo(Triple), HasVSX(false) { 671 BigEndian = (Triple.getArch() != llvm::Triple::ppc64le); 672 LongDoubleWidth = LongDoubleAlign = 128; 673 LongDoubleFormat = &llvm::APFloat::PPCDoubleDouble; 674 } 675 676 /// \brief Flags for architecture specific defines. 677 typedef enum { 678 ArchDefineNone = 0, 679 ArchDefineName = 1 << 0, // <name> is substituted for arch name. 680 ArchDefinePpcgr = 1 << 1, 681 ArchDefinePpcsq = 1 << 2, 682 ArchDefine440 = 1 << 3, 683 ArchDefine603 = 1 << 4, 684 ArchDefine604 = 1 << 5, 685 ArchDefinePwr4 = 1 << 6, 686 ArchDefinePwr5 = 1 << 7, 687 ArchDefinePwr5x = 1 << 8, 688 ArchDefinePwr6 = 1 << 9, 689 ArchDefinePwr6x = 1 << 10, 690 ArchDefinePwr7 = 1 << 11, 691 ArchDefineA2 = 1 << 12, 692 ArchDefineA2q = 1 << 13 693 } ArchDefineTypes; 694 695 // Note: GCC recognizes the following additional cpus: 696 // 401, 403, 405, 405fp, 440fp, 464, 464fp, 476, 476fp, 505, 740, 801, 697 // 821, 823, 8540, 8548, e300c2, e300c3, e500mc64, e6500, 860, cell, 698 // titan, rs64. 699 virtual bool setCPU(const std::string &Name) { 700 bool CPUKnown = llvm::StringSwitch<bool>(Name) 701 .Case("generic", true) 702 .Case("440", true) 703 .Case("450", true) 704 .Case("601", true) 705 .Case("602", true) 706 .Case("603", true) 707 .Case("603e", true) 708 .Case("603ev", true) 709 .Case("604", true) 710 .Case("604e", true) 711 .Case("620", true) 712 .Case("630", true) 713 .Case("g3", true) 714 .Case("7400", true) 715 .Case("g4", true) 716 .Case("7450", true) 717 .Case("g4+", true) 718 .Case("750", true) 719 .Case("970", true) 720 .Case("g5", true) 721 .Case("a2", true) 722 .Case("a2q", true) 723 .Case("e500mc", true) 724 .Case("e5500", true) 725 .Case("power3", true) 726 .Case("pwr3", true) 727 .Case("power4", true) 728 .Case("pwr4", true) 729 .Case("power5", true) 730 .Case("pwr5", true) 731 .Case("power5x", true) 732 .Case("pwr5x", true) 733 .Case("power6", true) 734 .Case("pwr6", true) 735 .Case("power6x", true) 736 .Case("pwr6x", true) 737 .Case("power7", true) 738 .Case("pwr7", true) 739 .Case("powerpc", true) 740 .Case("ppc", true) 741 .Case("powerpc64", true) 742 .Case("ppc64", true) 743 .Case("powerpc64le", true) 744 .Case("ppc64le", true) 745 .Default(false); 746 747 if (CPUKnown) 748 CPU = Name; 749 750 return CPUKnown; 751 } 752 753 virtual void getTargetBuiltins(const Builtin::Info *&Records, 754 unsigned &NumRecords) const { 755 Records = BuiltinInfo; 756 NumRecords = clang::PPC::LastTSBuiltin-Builtin::FirstTSBuiltin; 757 } 758 759 virtual bool isCLZForZeroUndef() const { return false; } 760 761 virtual void getTargetDefines(const LangOptions &Opts, 762 MacroBuilder &Builder) const; 763 764 virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const; 765 766 virtual bool handleTargetFeatures(std::vector<std::string> &Features, 767 DiagnosticsEngine &Diags); 768 virtual bool hasFeature(StringRef Feature) const; 769 770 virtual void getGCCRegNames(const char * const *&Names, 771 unsigned &NumNames) const; 772 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 773 unsigned &NumAliases) const; 774 virtual bool validateAsmConstraint(const char *&Name, 775 TargetInfo::ConstraintInfo &Info) const { 776 switch (*Name) { 777 default: return false; 778 case 'O': // Zero 779 break; 780 case 'b': // Base register 781 case 'f': // Floating point register 782 Info.setAllowsRegister(); 783 break; 784 // FIXME: The following are added to allow parsing. 785 // I just took a guess at what the actions should be. 786 // Also, is more specific checking needed? I.e. specific registers? 787 case 'd': // Floating point register (containing 64-bit value) 788 case 'v': // Altivec vector register 789 Info.setAllowsRegister(); 790 break; 791 case 'w': 792 switch (Name[1]) { 793 case 'd':// VSX vector register to hold vector double data 794 case 'f':// VSX vector register to hold vector float data 795 case 's':// VSX vector register to hold scalar float data 796 case 'a':// Any VSX register 797 break; 798 default: 799 return false; 800 } 801 Info.setAllowsRegister(); 802 Name++; // Skip over 'w'. 803 break; 804 case 'h': // `MQ', `CTR', or `LINK' register 805 case 'q': // `MQ' register 806 case 'c': // `CTR' register 807 case 'l': // `LINK' register 808 case 'x': // `CR' register (condition register) number 0 809 case 'y': // `CR' register (condition register) 810 case 'z': // `XER[CA]' carry bit (part of the XER register) 811 Info.setAllowsRegister(); 812 break; 813 case 'I': // Signed 16-bit constant 814 case 'J': // Unsigned 16-bit constant shifted left 16 bits 815 // (use `L' instead for SImode constants) 816 case 'K': // Unsigned 16-bit constant 817 case 'L': // Signed 16-bit constant shifted left 16 bits 818 case 'M': // Constant larger than 31 819 case 'N': // Exact power of 2 820 case 'P': // Constant whose negation is a signed 16-bit constant 821 case 'G': // Floating point constant that can be loaded into a 822 // register with one instruction per word 823 case 'H': // Integer/Floating point constant that can be loaded 824 // into a register using three instructions 825 break; 826 case 'm': // Memory operand. Note that on PowerPC targets, m can 827 // include addresses that update the base register. It 828 // is therefore only safe to use `m' in an asm statement 829 // if that asm statement accesses the operand exactly once. 830 // The asm statement must also use `%U<opno>' as a 831 // placeholder for the "update" flag in the corresponding 832 // load or store instruction. For example: 833 // asm ("st%U0 %1,%0" : "=m" (mem) : "r" (val)); 834 // is correct but: 835 // asm ("st %1,%0" : "=m" (mem) : "r" (val)); 836 // is not. Use es rather than m if you don't want the base 837 // register to be updated. 838 case 'e': 839 if (Name[1] != 's') 840 return false; 841 // es: A "stable" memory operand; that is, one which does not 842 // include any automodification of the base register. Unlike 843 // `m', this constraint can be used in asm statements that 844 // might access the operand several times, or that might not 845 // access it at all. 846 Info.setAllowsMemory(); 847 Name++; // Skip over 'e'. 848 break; 849 case 'Q': // Memory operand that is an offset from a register (it is 850 // usually better to use `m' or `es' in asm statements) 851 case 'Z': // Memory operand that is an indexed or indirect from a 852 // register (it is usually better to use `m' or `es' in 853 // asm statements) 854 Info.setAllowsMemory(); 855 Info.setAllowsRegister(); 856 break; 857 case 'R': // AIX TOC entry 858 case 'a': // Address operand that is an indexed or indirect from a 859 // register (`p' is preferable for asm statements) 860 case 'S': // Constant suitable as a 64-bit mask operand 861 case 'T': // Constant suitable as a 32-bit mask operand 862 case 'U': // System V Release 4 small data area reference 863 case 't': // AND masks that can be performed by two rldic{l, r} 864 // instructions 865 case 'W': // Vector constant that does not require memory 866 case 'j': // Vector constant that is all zeros. 867 break; 868 // End FIXME. 869 } 870 return true; 871 } 872 virtual const char *getClobbers() const { 873 return ""; 874 } 875 int getEHDataRegisterNumber(unsigned RegNo) const { 876 if (RegNo == 0) return 3; 877 if (RegNo == 1) return 4; 878 return -1; 879 } 880 }; 881 882 const Builtin::Info PPCTargetInfo::BuiltinInfo[] = { 883 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 884 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 885 ALL_LANGUAGES }, 886 #include "clang/Basic/BuiltinsPPC.def" 887 }; 888 889 /// handleTargetFeatures - Perform initialization based on the user 890 /// configured set of features. 891 bool PPCTargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 892 DiagnosticsEngine &Diags) { 893 // Remember the maximum enabled sselevel. 894 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 895 // Ignore disabled features. 896 if (Features[i][0] == '-') 897 continue; 898 899 StringRef Feature = StringRef(Features[i]).substr(1); 900 901 if (Feature == "vsx") { 902 HasVSX = true; 903 continue; 904 } 905 906 // TODO: Finish this list and add an assert that we've handled them 907 // all. 908 } 909 910 return true; 911 } 912 913 /// PPCTargetInfo::getTargetDefines - Return a set of the PowerPC-specific 914 /// #defines that are not tied to a specific subtarget. 915 void PPCTargetInfo::getTargetDefines(const LangOptions &Opts, 916 MacroBuilder &Builder) const { 917 // Target identification. 918 Builder.defineMacro("__ppc__"); 919 Builder.defineMacro("__PPC__"); 920 Builder.defineMacro("_ARCH_PPC"); 921 Builder.defineMacro("__powerpc__"); 922 Builder.defineMacro("__POWERPC__"); 923 if (PointerWidth == 64) { 924 Builder.defineMacro("_ARCH_PPC64"); 925 Builder.defineMacro("__powerpc64__"); 926 Builder.defineMacro("__ppc64__"); 927 Builder.defineMacro("__PPC64__"); 928 } 929 930 // Target properties. 931 if (getTriple().getArch() == llvm::Triple::ppc64le) { 932 Builder.defineMacro("_LITTLE_ENDIAN"); 933 Builder.defineMacro("__LITTLE_ENDIAN__"); 934 } else { 935 if (getTriple().getOS() != llvm::Triple::NetBSD && 936 getTriple().getOS() != llvm::Triple::OpenBSD) 937 Builder.defineMacro("_BIG_ENDIAN"); 938 Builder.defineMacro("__BIG_ENDIAN__"); 939 } 940 941 // Subtarget options. 942 Builder.defineMacro("__NATURAL_ALIGNMENT__"); 943 Builder.defineMacro("__REGISTER_PREFIX__", ""); 944 945 // FIXME: Should be controlled by command line option. 946 if (LongDoubleWidth == 128) 947 Builder.defineMacro("__LONG_DOUBLE_128__"); 948 949 if (Opts.AltiVec) { 950 Builder.defineMacro("__VEC__", "10206"); 951 Builder.defineMacro("__ALTIVEC__"); 952 } 953 954 // CPU identification. 955 ArchDefineTypes defs = (ArchDefineTypes)llvm::StringSwitch<int>(CPU) 956 .Case("440", ArchDefineName) 957 .Case("450", ArchDefineName | ArchDefine440) 958 .Case("601", ArchDefineName) 959 .Case("602", ArchDefineName | ArchDefinePpcgr) 960 .Case("603", ArchDefineName | ArchDefinePpcgr) 961 .Case("603e", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 962 .Case("603ev", ArchDefineName | ArchDefine603 | ArchDefinePpcgr) 963 .Case("604", ArchDefineName | ArchDefinePpcgr) 964 .Case("604e", ArchDefineName | ArchDefine604 | ArchDefinePpcgr) 965 .Case("620", ArchDefineName | ArchDefinePpcgr) 966 .Case("630", ArchDefineName | ArchDefinePpcgr) 967 .Case("7400", ArchDefineName | ArchDefinePpcgr) 968 .Case("7450", ArchDefineName | ArchDefinePpcgr) 969 .Case("750", ArchDefineName | ArchDefinePpcgr) 970 .Case("970", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 971 | ArchDefinePpcsq) 972 .Case("a2", ArchDefineA2) 973 .Case("a2q", ArchDefineName | ArchDefineA2 | ArchDefineA2q) 974 .Case("pwr3", ArchDefinePpcgr) 975 .Case("pwr4", ArchDefineName | ArchDefinePpcgr | ArchDefinePpcsq) 976 .Case("pwr5", ArchDefineName | ArchDefinePwr4 | ArchDefinePpcgr 977 | ArchDefinePpcsq) 978 .Case("pwr5x", ArchDefineName | ArchDefinePwr5 | ArchDefinePwr4 979 | ArchDefinePpcgr | ArchDefinePpcsq) 980 .Case("pwr6", ArchDefineName | ArchDefinePwr5x | ArchDefinePwr5 981 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 982 .Case("pwr6x", ArchDefineName | ArchDefinePwr6 | ArchDefinePwr5x 983 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 984 | ArchDefinePpcsq) 985 .Case("pwr7", ArchDefineName | ArchDefinePwr6x | ArchDefinePwr6 986 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 987 | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq) 988 .Case("power3", ArchDefinePpcgr) 989 .Case("power4", ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 990 .Case("power5", ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 991 | ArchDefinePpcsq) 992 .Case("power5x", ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 993 | ArchDefinePpcgr | ArchDefinePpcsq) 994 .Case("power6", ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 995 | ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq) 996 .Case("power6x", ArchDefinePwr6x | ArchDefinePwr6 | ArchDefinePwr5x 997 | ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr 998 | ArchDefinePpcsq) 999 .Case("power7", ArchDefinePwr7 | ArchDefinePwr6x | ArchDefinePwr6 1000 | ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 1001 | ArchDefinePwr6 | ArchDefinePpcgr | ArchDefinePpcsq) 1002 .Default(ArchDefineNone); 1003 1004 if (defs & ArchDefineName) 1005 Builder.defineMacro(Twine("_ARCH_", StringRef(CPU).upper())); 1006 if (defs & ArchDefinePpcgr) 1007 Builder.defineMacro("_ARCH_PPCGR"); 1008 if (defs & ArchDefinePpcsq) 1009 Builder.defineMacro("_ARCH_PPCSQ"); 1010 if (defs & ArchDefine440) 1011 Builder.defineMacro("_ARCH_440"); 1012 if (defs & ArchDefine603) 1013 Builder.defineMacro("_ARCH_603"); 1014 if (defs & ArchDefine604) 1015 Builder.defineMacro("_ARCH_604"); 1016 if (defs & ArchDefinePwr4) 1017 Builder.defineMacro("_ARCH_PWR4"); 1018 if (defs & ArchDefinePwr5) 1019 Builder.defineMacro("_ARCH_PWR5"); 1020 if (defs & ArchDefinePwr5x) 1021 Builder.defineMacro("_ARCH_PWR5X"); 1022 if (defs & ArchDefinePwr6) 1023 Builder.defineMacro("_ARCH_PWR6"); 1024 if (defs & ArchDefinePwr6x) 1025 Builder.defineMacro("_ARCH_PWR6X"); 1026 if (defs & ArchDefinePwr7) 1027 Builder.defineMacro("_ARCH_PWR7"); 1028 if (defs & ArchDefineA2) 1029 Builder.defineMacro("_ARCH_A2"); 1030 if (defs & ArchDefineA2q) { 1031 Builder.defineMacro("_ARCH_A2Q"); 1032 Builder.defineMacro("_ARCH_QP"); 1033 } 1034 1035 if (getTriple().getVendor() == llvm::Triple::BGQ) { 1036 Builder.defineMacro("__bg__"); 1037 Builder.defineMacro("__THW_BLUEGENE__"); 1038 Builder.defineMacro("__bgq__"); 1039 Builder.defineMacro("__TOS_BGQ__"); 1040 } 1041 1042 if (HasVSX) 1043 Builder.defineMacro("__VSX__"); 1044 1045 // FIXME: The following are not yet generated here by Clang, but are 1046 // generated by GCC: 1047 // 1048 // _SOFT_FLOAT_ 1049 // __RECIP_PRECISION__ 1050 // __APPLE_ALTIVEC__ 1051 // __RECIP__ 1052 // __RECIPF__ 1053 // __RSQRTE__ 1054 // __RSQRTEF__ 1055 // _SOFT_DOUBLE_ 1056 // __NO_LWSYNC__ 1057 // __HAVE_BSWAP__ 1058 // __LONGDOUBLE128 1059 // __CMODEL_MEDIUM__ 1060 // __CMODEL_LARGE__ 1061 // _CALL_SYSV 1062 // _CALL_DARWIN 1063 // __NO_FPRS__ 1064 } 1065 1066 void PPCTargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 1067 Features["altivec"] = llvm::StringSwitch<bool>(CPU) 1068 .Case("7400", true) 1069 .Case("g4", true) 1070 .Case("7450", true) 1071 .Case("g4+", true) 1072 .Case("970", true) 1073 .Case("g5", true) 1074 .Case("pwr6", true) 1075 .Case("pwr7", true) 1076 .Case("ppc64", true) 1077 .Case("ppc64le", true) 1078 .Default(false); 1079 1080 Features["qpx"] = (CPU == "a2q"); 1081 } 1082 1083 bool PPCTargetInfo::hasFeature(StringRef Feature) const { 1084 return Feature == "powerpc"; 1085 } 1086 1087 1088 const char * const PPCTargetInfo::GCCRegNames[] = { 1089 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 1090 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1091 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 1092 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 1093 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", 1094 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", 1095 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", 1096 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", 1097 "mq", "lr", "ctr", "ap", 1098 "cr0", "cr1", "cr2", "cr3", "cr4", "cr5", "cr6", "cr7", 1099 "xer", 1100 "v0", "v1", "v2", "v3", "v4", "v5", "v6", "v7", 1101 "v8", "v9", "v10", "v11", "v12", "v13", "v14", "v15", 1102 "v16", "v17", "v18", "v19", "v20", "v21", "v22", "v23", 1103 "v24", "v25", "v26", "v27", "v28", "v29", "v30", "v31", 1104 "vrsave", "vscr", 1105 "spe_acc", "spefscr", 1106 "sfp" 1107 }; 1108 1109 void PPCTargetInfo::getGCCRegNames(const char * const *&Names, 1110 unsigned &NumNames) const { 1111 Names = GCCRegNames; 1112 NumNames = llvm::array_lengthof(GCCRegNames); 1113 } 1114 1115 const TargetInfo::GCCRegAlias PPCTargetInfo::GCCRegAliases[] = { 1116 // While some of these aliases do map to different registers 1117 // they still share the same register name. 1118 { { "0" }, "r0" }, 1119 { { "1"}, "r1" }, 1120 { { "2" }, "r2" }, 1121 { { "3" }, "r3" }, 1122 { { "4" }, "r4" }, 1123 { { "5" }, "r5" }, 1124 { { "6" }, "r6" }, 1125 { { "7" }, "r7" }, 1126 { { "8" }, "r8" }, 1127 { { "9" }, "r9" }, 1128 { { "10" }, "r10" }, 1129 { { "11" }, "r11" }, 1130 { { "12" }, "r12" }, 1131 { { "13" }, "r13" }, 1132 { { "14" }, "r14" }, 1133 { { "15" }, "r15" }, 1134 { { "16" }, "r16" }, 1135 { { "17" }, "r17" }, 1136 { { "18" }, "r18" }, 1137 { { "19" }, "r19" }, 1138 { { "20" }, "r20" }, 1139 { { "21" }, "r21" }, 1140 { { "22" }, "r22" }, 1141 { { "23" }, "r23" }, 1142 { { "24" }, "r24" }, 1143 { { "25" }, "r25" }, 1144 { { "26" }, "r26" }, 1145 { { "27" }, "r27" }, 1146 { { "28" }, "r28" }, 1147 { { "29" }, "r29" }, 1148 { { "30" }, "r30" }, 1149 { { "31" }, "r31" }, 1150 { { "fr0" }, "f0" }, 1151 { { "fr1" }, "f1" }, 1152 { { "fr2" }, "f2" }, 1153 { { "fr3" }, "f3" }, 1154 { { "fr4" }, "f4" }, 1155 { { "fr5" }, "f5" }, 1156 { { "fr6" }, "f6" }, 1157 { { "fr7" }, "f7" }, 1158 { { "fr8" }, "f8" }, 1159 { { "fr9" }, "f9" }, 1160 { { "fr10" }, "f10" }, 1161 { { "fr11" }, "f11" }, 1162 { { "fr12" }, "f12" }, 1163 { { "fr13" }, "f13" }, 1164 { { "fr14" }, "f14" }, 1165 { { "fr15" }, "f15" }, 1166 { { "fr16" }, "f16" }, 1167 { { "fr17" }, "f17" }, 1168 { { "fr18" }, "f18" }, 1169 { { "fr19" }, "f19" }, 1170 { { "fr20" }, "f20" }, 1171 { { "fr21" }, "f21" }, 1172 { { "fr22" }, "f22" }, 1173 { { "fr23" }, "f23" }, 1174 { { "fr24" }, "f24" }, 1175 { { "fr25" }, "f25" }, 1176 { { "fr26" }, "f26" }, 1177 { { "fr27" }, "f27" }, 1178 { { "fr28" }, "f28" }, 1179 { { "fr29" }, "f29" }, 1180 { { "fr30" }, "f30" }, 1181 { { "fr31" }, "f31" }, 1182 { { "cc" }, "cr0" }, 1183 }; 1184 1185 void PPCTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 1186 unsigned &NumAliases) const { 1187 Aliases = GCCRegAliases; 1188 NumAliases = llvm::array_lengthof(GCCRegAliases); 1189 } 1190 } // end anonymous namespace. 1191 1192 namespace { 1193 class PPC32TargetInfo : public PPCTargetInfo { 1194 public: 1195 PPC32TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1196 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 1197 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32"; 1198 1199 switch (getTriple().getOS()) { 1200 case llvm::Triple::Linux: 1201 case llvm::Triple::FreeBSD: 1202 case llvm::Triple::NetBSD: 1203 SizeType = UnsignedInt; 1204 PtrDiffType = SignedInt; 1205 IntPtrType = SignedInt; 1206 break; 1207 default: 1208 break; 1209 } 1210 1211 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1212 LongDoubleWidth = LongDoubleAlign = 64; 1213 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1214 } 1215 1216 // PPC32 supports atomics up to 4 bytes. 1217 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 1218 } 1219 1220 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1221 // This is the ELF definition, and is overridden by the Darwin sub-target 1222 return TargetInfo::PowerABIBuiltinVaList; 1223 } 1224 }; 1225 } // end anonymous namespace. 1226 1227 // Note: ABI differences may eventually require us to have a separate 1228 // TargetInfo for little endian. 1229 namespace { 1230 class PPC64TargetInfo : public PPCTargetInfo { 1231 public: 1232 PPC64TargetInfo(const llvm::Triple &Triple) : PPCTargetInfo(Triple) { 1233 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 1234 IntMaxType = SignedLong; 1235 UIntMaxType = UnsignedLong; 1236 Int64Type = SignedLong; 1237 1238 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 1239 LongDoubleWidth = LongDoubleAlign = 64; 1240 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 1241 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 1242 "i64:64:64-f32:32:32-f64:64:64-" 1243 "v128:128:128-n32:64"; 1244 } else 1245 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 1246 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" 1247 "v128:128:128-n32:64"; 1248 1249 // PPC64 supports atomics up to 8 bytes. 1250 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 1251 } 1252 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1253 return TargetInfo::CharPtrBuiltinVaList; 1254 } 1255 }; 1256 } // end anonymous namespace. 1257 1258 1259 namespace { 1260 class DarwinPPC32TargetInfo : 1261 public DarwinTargetInfo<PPC32TargetInfo> { 1262 public: 1263 DarwinPPC32TargetInfo(const llvm::Triple &Triple) 1264 : DarwinTargetInfo<PPC32TargetInfo>(Triple) { 1265 HasAlignMac68kSupport = true; 1266 BoolWidth = BoolAlign = 32; //XXX support -mone-byte-bool? 1267 PtrDiffType = SignedInt; // for http://llvm.org/bugs/show_bug.cgi?id=15726 1268 LongLongAlign = 32; 1269 SuitableAlign = 128; 1270 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 1271 "i64:32:64-f32:32:32-f64:64:64-v128:128:128-n32"; 1272 } 1273 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1274 return TargetInfo::CharPtrBuiltinVaList; 1275 } 1276 }; 1277 1278 class DarwinPPC64TargetInfo : 1279 public DarwinTargetInfo<PPC64TargetInfo> { 1280 public: 1281 DarwinPPC64TargetInfo(const llvm::Triple &Triple) 1282 : DarwinTargetInfo<PPC64TargetInfo>(Triple) { 1283 HasAlignMac68kSupport = true; 1284 SuitableAlign = 128; 1285 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 1286 "i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"; 1287 } 1288 }; 1289 } // end anonymous namespace. 1290 1291 namespace { 1292 static const unsigned NVPTXAddrSpaceMap[] = { 1293 1, // opencl_global 1294 3, // opencl_local 1295 4, // opencl_constant 1296 1, // cuda_device 1297 4, // cuda_constant 1298 3, // cuda_shared 1299 }; 1300 class NVPTXTargetInfo : public TargetInfo { 1301 static const char * const GCCRegNames[]; 1302 static const Builtin::Info BuiltinInfo[]; 1303 public: 1304 NVPTXTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 1305 BigEndian = false; 1306 TLSSupported = false; 1307 LongWidth = LongAlign = 64; 1308 AddrSpaceMap = &NVPTXAddrSpaceMap; 1309 UseAddrSpaceMapMangling = true; 1310 // Define available target features 1311 // These must be defined in sorted order! 1312 NoAsmVariants = true; 1313 } 1314 virtual void getTargetDefines(const LangOptions &Opts, 1315 MacroBuilder &Builder) const { 1316 Builder.defineMacro("__PTX__"); 1317 Builder.defineMacro("__NVPTX__"); 1318 } 1319 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1320 unsigned &NumRecords) const { 1321 Records = BuiltinInfo; 1322 NumRecords = clang::NVPTX::LastTSBuiltin-Builtin::FirstTSBuiltin; 1323 } 1324 virtual bool hasFeature(StringRef Feature) const { 1325 return Feature == "ptx" || Feature == "nvptx"; 1326 } 1327 1328 virtual void getGCCRegNames(const char * const *&Names, 1329 unsigned &NumNames) const; 1330 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1331 unsigned &NumAliases) const { 1332 // No aliases. 1333 Aliases = 0; 1334 NumAliases = 0; 1335 } 1336 virtual bool validateAsmConstraint(const char *&Name, 1337 TargetInfo::ConstraintInfo &Info) const { 1338 switch (*Name) { 1339 default: return false; 1340 case 'c': 1341 case 'h': 1342 case 'r': 1343 case 'l': 1344 case 'f': 1345 case 'd': 1346 Info.setAllowsRegister(); 1347 return true; 1348 } 1349 } 1350 virtual const char *getClobbers() const { 1351 // FIXME: Is this really right? 1352 return ""; 1353 } 1354 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1355 // FIXME: implement 1356 return TargetInfo::CharPtrBuiltinVaList; 1357 } 1358 virtual bool setCPU(const std::string &Name) { 1359 bool Valid = llvm::StringSwitch<bool>(Name) 1360 .Case("sm_20", true) 1361 .Case("sm_21", true) 1362 .Case("sm_30", true) 1363 .Case("sm_35", true) 1364 .Default(false); 1365 1366 return Valid; 1367 } 1368 }; 1369 1370 const Builtin::Info NVPTXTargetInfo::BuiltinInfo[] = { 1371 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1372 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1373 ALL_LANGUAGES }, 1374 #include "clang/Basic/BuiltinsNVPTX.def" 1375 }; 1376 1377 const char * const NVPTXTargetInfo::GCCRegNames[] = { 1378 "r0" 1379 }; 1380 1381 void NVPTXTargetInfo::getGCCRegNames(const char * const *&Names, 1382 unsigned &NumNames) const { 1383 Names = GCCRegNames; 1384 NumNames = llvm::array_lengthof(GCCRegNames); 1385 } 1386 1387 class NVPTX32TargetInfo : public NVPTXTargetInfo { 1388 public: 1389 NVPTX32TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1390 PointerWidth = PointerAlign = 32; 1391 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedInt; 1392 DescriptionString 1393 = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 1394 "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-" 1395 "n16:32:64"; 1396 } 1397 }; 1398 1399 class NVPTX64TargetInfo : public NVPTXTargetInfo { 1400 public: 1401 NVPTX64TargetInfo(const llvm::Triple &Triple) : NVPTXTargetInfo(Triple) { 1402 PointerWidth = PointerAlign = 64; 1403 SizeType = PtrDiffType = IntPtrType = TargetInfo::UnsignedLongLong; 1404 DescriptionString 1405 = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 1406 "f32:32:32-f64:64:64-v16:16:16-v32:32:32-v64:64:64-v128:128:128-" 1407 "n16:32:64"; 1408 } 1409 }; 1410 } 1411 1412 namespace { 1413 1414 static const unsigned R600AddrSpaceMap[] = { 1415 1, // opencl_global 1416 3, // opencl_local 1417 2, // opencl_constant 1418 1, // cuda_device 1419 2, // cuda_constant 1420 3 // cuda_shared 1421 }; 1422 1423 static const char *DescriptionStringR600 = 1424 "e" 1425 "-p:32:32:32" 1426 "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32" 1427 "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128" 1428 "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048" 1429 "-n32:64"; 1430 1431 static const char *DescriptionStringR600DoubleOps = 1432 "e" 1433 "-p:32:32:32" 1434 "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64" 1435 "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128" 1436 "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048" 1437 "-n32:64"; 1438 1439 static const char *DescriptionStringSI = 1440 "e" 1441 "-p:64:64:64" 1442 "-p3:32:32:32" 1443 "-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64" 1444 "-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128" 1445 "-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-v2048:2048:2048" 1446 "-n32:64"; 1447 1448 class R600TargetInfo : public TargetInfo { 1449 /// \brief The GPU profiles supported by the R600 target. 1450 enum GPUKind { 1451 GK_NONE, 1452 GK_R600, 1453 GK_R600_DOUBLE_OPS, 1454 GK_R700, 1455 GK_R700_DOUBLE_OPS, 1456 GK_EVERGREEN, 1457 GK_EVERGREEN_DOUBLE_OPS, 1458 GK_NORTHERN_ISLANDS, 1459 GK_CAYMAN, 1460 GK_SOUTHERN_ISLANDS, 1461 GK_SEA_ISLANDS 1462 } GPU; 1463 1464 public: 1465 R600TargetInfo(const llvm::Triple &Triple) 1466 : TargetInfo(Triple), GPU(GK_R600) { 1467 DescriptionString = DescriptionStringR600; 1468 AddrSpaceMap = &R600AddrSpaceMap; 1469 UseAddrSpaceMapMangling = true; 1470 } 1471 1472 virtual const char * getClobbers() const { 1473 return ""; 1474 } 1475 1476 virtual void getGCCRegNames(const char * const *&Names, 1477 unsigned &numNames) const { 1478 Names = NULL; 1479 numNames = 0; 1480 } 1481 1482 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1483 unsigned &NumAliases) const { 1484 Aliases = NULL; 1485 NumAliases = 0; 1486 } 1487 1488 virtual bool validateAsmConstraint(const char *&Name, 1489 TargetInfo::ConstraintInfo &info) const { 1490 return true; 1491 } 1492 1493 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1494 unsigned &NumRecords) const { 1495 Records = NULL; 1496 NumRecords = 0; 1497 } 1498 1499 1500 virtual void getTargetDefines(const LangOptions &Opts, 1501 MacroBuilder &Builder) const { 1502 Builder.defineMacro("__R600__"); 1503 } 1504 1505 virtual BuiltinVaListKind getBuiltinVaListKind() const { 1506 return TargetInfo::CharPtrBuiltinVaList; 1507 } 1508 1509 virtual bool setCPU(const std::string &Name) { 1510 GPU = llvm::StringSwitch<GPUKind>(Name) 1511 .Case("r600" , GK_R600) 1512 .Case("rv610", GK_R600) 1513 .Case("rv620", GK_R600) 1514 .Case("rv630", GK_R600) 1515 .Case("rv635", GK_R600) 1516 .Case("rs780", GK_R600) 1517 .Case("rs880", GK_R600) 1518 .Case("rv670", GK_R600_DOUBLE_OPS) 1519 .Case("rv710", GK_R700) 1520 .Case("rv730", GK_R700) 1521 .Case("rv740", GK_R700_DOUBLE_OPS) 1522 .Case("rv770", GK_R700_DOUBLE_OPS) 1523 .Case("palm", GK_EVERGREEN) 1524 .Case("cedar", GK_EVERGREEN) 1525 .Case("sumo", GK_EVERGREEN) 1526 .Case("sumo2", GK_EVERGREEN) 1527 .Case("redwood", GK_EVERGREEN) 1528 .Case("juniper", GK_EVERGREEN) 1529 .Case("hemlock", GK_EVERGREEN_DOUBLE_OPS) 1530 .Case("cypress", GK_EVERGREEN_DOUBLE_OPS) 1531 .Case("barts", GK_NORTHERN_ISLANDS) 1532 .Case("turks", GK_NORTHERN_ISLANDS) 1533 .Case("caicos", GK_NORTHERN_ISLANDS) 1534 .Case("cayman", GK_CAYMAN) 1535 .Case("aruba", GK_CAYMAN) 1536 .Case("tahiti", GK_SOUTHERN_ISLANDS) 1537 .Case("pitcairn", GK_SOUTHERN_ISLANDS) 1538 .Case("verde", GK_SOUTHERN_ISLANDS) 1539 .Case("oland", GK_SOUTHERN_ISLANDS) 1540 .Case("bonaire", GK_SEA_ISLANDS) 1541 .Case("kabini", GK_SEA_ISLANDS) 1542 .Case("kaveri", GK_SEA_ISLANDS) 1543 .Case("hawaii", GK_SEA_ISLANDS) 1544 .Default(GK_NONE); 1545 1546 if (GPU == GK_NONE) { 1547 return false; 1548 } 1549 1550 // Set the correct data layout 1551 switch (GPU) { 1552 case GK_NONE: 1553 case GK_R600: 1554 case GK_R700: 1555 case GK_EVERGREEN: 1556 case GK_NORTHERN_ISLANDS: 1557 DescriptionString = DescriptionStringR600; 1558 break; 1559 case GK_R600_DOUBLE_OPS: 1560 case GK_R700_DOUBLE_OPS: 1561 case GK_EVERGREEN_DOUBLE_OPS: 1562 case GK_CAYMAN: 1563 DescriptionString = DescriptionStringR600DoubleOps; 1564 break; 1565 case GK_SOUTHERN_ISLANDS: 1566 case GK_SEA_ISLANDS: 1567 DescriptionString = DescriptionStringSI; 1568 break; 1569 } 1570 1571 return true; 1572 } 1573 }; 1574 1575 } // end anonymous namespace 1576 1577 namespace { 1578 // Namespace for x86 abstract base class 1579 const Builtin::Info BuiltinInfo[] = { 1580 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 1581 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 1582 ALL_LANGUAGES }, 1583 #include "clang/Basic/BuiltinsX86.def" 1584 }; 1585 1586 static const char* const GCCRegNames[] = { 1587 "ax", "dx", "cx", "bx", "si", "di", "bp", "sp", 1588 "st", "st(1)", "st(2)", "st(3)", "st(4)", "st(5)", "st(6)", "st(7)", 1589 "argp", "flags", "fpcr", "fpsr", "dirflag", "frame", 1590 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 1591 "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7", 1592 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 1593 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 1594 "ymm0", "ymm1", "ymm2", "ymm3", "ymm4", "ymm5", "ymm6", "ymm7", 1595 "ymm8", "ymm9", "ymm10", "ymm11", "ymm12", "ymm13", "ymm14", "ymm15", 1596 }; 1597 1598 const TargetInfo::AddlRegName AddlRegNames[] = { 1599 { { "al", "ah", "eax", "rax" }, 0 }, 1600 { { "bl", "bh", "ebx", "rbx" }, 3 }, 1601 { { "cl", "ch", "ecx", "rcx" }, 2 }, 1602 { { "dl", "dh", "edx", "rdx" }, 1 }, 1603 { { "esi", "rsi" }, 4 }, 1604 { { "edi", "rdi" }, 5 }, 1605 { { "esp", "rsp" }, 7 }, 1606 { { "ebp", "rbp" }, 6 }, 1607 }; 1608 1609 // X86 target abstract base class; x86-32 and x86-64 are very close, so 1610 // most of the implementation can be shared. 1611 class X86TargetInfo : public TargetInfo { 1612 enum X86SSEEnum { 1613 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 1614 } SSELevel; 1615 enum MMX3DNowEnum { 1616 NoMMX3DNow, MMX, AMD3DNow, AMD3DNowAthlon 1617 } MMX3DNowLevel; 1618 enum XOPEnum { 1619 NoXOP, 1620 SSE4A, 1621 FMA4, 1622 XOP 1623 } XOPLevel; 1624 1625 bool HasAES; 1626 bool HasPCLMUL; 1627 bool HasLZCNT; 1628 bool HasRDRND; 1629 bool HasBMI; 1630 bool HasBMI2; 1631 bool HasPOPCNT; 1632 bool HasRTM; 1633 bool HasPRFCHW; 1634 bool HasRDSEED; 1635 bool HasTBM; 1636 bool HasFMA; 1637 bool HasF16C; 1638 bool HasAVX512CD, HasAVX512ER, HasAVX512PF; 1639 bool HasSHA; 1640 bool HasCX16; 1641 1642 /// \brief Enumeration of all of the X86 CPUs supported by Clang. 1643 /// 1644 /// Each enumeration represents a particular CPU supported by Clang. These 1645 /// loosely correspond to the options passed to '-march' or '-mtune' flags. 1646 enum CPUKind { 1647 CK_Generic, 1648 1649 /// \name i386 1650 /// i386-generation processors. 1651 //@{ 1652 CK_i386, 1653 //@} 1654 1655 /// \name i486 1656 /// i486-generation processors. 1657 //@{ 1658 CK_i486, 1659 CK_WinChipC6, 1660 CK_WinChip2, 1661 CK_C3, 1662 //@} 1663 1664 /// \name i586 1665 /// i586-generation processors, P5 microarchitecture based. 1666 //@{ 1667 CK_i586, 1668 CK_Pentium, 1669 CK_PentiumMMX, 1670 //@} 1671 1672 /// \name i686 1673 /// i686-generation processors, P6 / Pentium M microarchitecture based. 1674 //@{ 1675 CK_i686, 1676 CK_PentiumPro, 1677 CK_Pentium2, 1678 CK_Pentium3, 1679 CK_Pentium3M, 1680 CK_PentiumM, 1681 CK_C3_2, 1682 1683 /// This enumerator is a bit odd, as GCC no longer accepts -march=yonah. 1684 /// Clang however has some logic to suport this. 1685 // FIXME: Warn, deprecate, and potentially remove this. 1686 CK_Yonah, 1687 //@} 1688 1689 /// \name Netburst 1690 /// Netburst microarchitecture based processors. 1691 //@{ 1692 CK_Pentium4, 1693 CK_Pentium4M, 1694 CK_Prescott, 1695 CK_Nocona, 1696 //@} 1697 1698 /// \name Core 1699 /// Core microarchitecture based processors. 1700 //@{ 1701 CK_Core2, 1702 1703 /// This enumerator, like \see CK_Yonah, is a bit odd. It is another 1704 /// codename which GCC no longer accepts as an option to -march, but Clang 1705 /// has some logic for recognizing it. 1706 // FIXME: Warn, deprecate, and potentially remove this. 1707 CK_Penryn, 1708 //@} 1709 1710 /// \name Atom 1711 /// Atom processors 1712 //@{ 1713 CK_Atom, 1714 CK_Silvermont, 1715 //@} 1716 1717 /// \name Nehalem 1718 /// Nehalem microarchitecture based processors. 1719 //@{ 1720 CK_Corei7, 1721 CK_Corei7AVX, 1722 CK_CoreAVXi, 1723 CK_CoreAVX2, 1724 //@} 1725 1726 /// \name Knights Landing 1727 /// Knights Landing processor. 1728 CK_KNL, 1729 1730 /// \name K6 1731 /// K6 architecture processors. 1732 //@{ 1733 CK_K6, 1734 CK_K6_2, 1735 CK_K6_3, 1736 //@} 1737 1738 /// \name K7 1739 /// K7 architecture processors. 1740 //@{ 1741 CK_Athlon, 1742 CK_AthlonThunderbird, 1743 CK_Athlon4, 1744 CK_AthlonXP, 1745 CK_AthlonMP, 1746 //@} 1747 1748 /// \name K8 1749 /// K8 architecture processors. 1750 //@{ 1751 CK_Athlon64, 1752 CK_Athlon64SSE3, 1753 CK_AthlonFX, 1754 CK_K8, 1755 CK_K8SSE3, 1756 CK_Opteron, 1757 CK_OpteronSSE3, 1758 CK_AMDFAM10, 1759 //@} 1760 1761 /// \name Bobcat 1762 /// Bobcat architecture processors. 1763 //@{ 1764 CK_BTVER1, 1765 CK_BTVER2, 1766 //@} 1767 1768 /// \name Bulldozer 1769 /// Bulldozer architecture processors. 1770 //@{ 1771 CK_BDVER1, 1772 CK_BDVER2, 1773 CK_BDVER3, 1774 //@} 1775 1776 /// This specification is deprecated and will be removed in the future. 1777 /// Users should prefer \see CK_K8. 1778 // FIXME: Warn on this when the CPU is set to it. 1779 CK_x86_64, 1780 //@} 1781 1782 /// \name Geode 1783 /// Geode processors. 1784 //@{ 1785 CK_Geode 1786 //@} 1787 } CPU; 1788 1789 enum FPMathKind { 1790 FP_Default, 1791 FP_SSE, 1792 FP_387 1793 } FPMath; 1794 1795 public: 1796 X86TargetInfo(const llvm::Triple &Triple) 1797 : TargetInfo(Triple), SSELevel(NoSSE), MMX3DNowLevel(NoMMX3DNow), 1798 XOPLevel(NoXOP), HasAES(false), HasPCLMUL(false), HasLZCNT(false), 1799 HasRDRND(false), HasBMI(false), HasBMI2(false), HasPOPCNT(false), 1800 HasRTM(false), HasPRFCHW(false), HasRDSEED(false), HasTBM(false), 1801 HasFMA(false), HasF16C(false), HasAVX512CD(false), HasAVX512ER(false), 1802 HasAVX512PF(false), HasSHA(false), HasCX16(false), CPU(CK_Generic), 1803 FPMath(FP_Default) { 1804 BigEndian = false; 1805 LongDoubleFormat = &llvm::APFloat::x87DoubleExtended; 1806 } 1807 virtual unsigned getFloatEvalMethod() const { 1808 // X87 evaluates with 80 bits "long double" precision. 1809 return SSELevel == NoSSE ? 2 : 0; 1810 } 1811 virtual void getTargetBuiltins(const Builtin::Info *&Records, 1812 unsigned &NumRecords) const { 1813 Records = BuiltinInfo; 1814 NumRecords = clang::X86::LastTSBuiltin-Builtin::FirstTSBuiltin; 1815 } 1816 virtual void getGCCRegNames(const char * const *&Names, 1817 unsigned &NumNames) const { 1818 Names = GCCRegNames; 1819 NumNames = llvm::array_lengthof(GCCRegNames); 1820 } 1821 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 1822 unsigned &NumAliases) const { 1823 Aliases = 0; 1824 NumAliases = 0; 1825 } 1826 virtual void getGCCAddlRegNames(const AddlRegName *&Names, 1827 unsigned &NumNames) const { 1828 Names = AddlRegNames; 1829 NumNames = llvm::array_lengthof(AddlRegNames); 1830 } 1831 virtual bool validateAsmConstraint(const char *&Name, 1832 TargetInfo::ConstraintInfo &info) const; 1833 virtual std::string convertConstraint(const char *&Constraint) const; 1834 virtual const char *getClobbers() const { 1835 return "~{dirflag},~{fpsr},~{flags}"; 1836 } 1837 virtual void getTargetDefines(const LangOptions &Opts, 1838 MacroBuilder &Builder) const; 1839 static void setSSELevel(llvm::StringMap<bool> &Features, X86SSEEnum Level, 1840 bool Enabled); 1841 static void setMMXLevel(llvm::StringMap<bool> &Features, MMX3DNowEnum Level, 1842 bool Enabled); 1843 static void setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 1844 bool Enabled); 1845 virtual void setFeatureEnabled(llvm::StringMap<bool> &Features, 1846 StringRef Name, bool Enabled) const { 1847 setFeatureEnabledImpl(Features, Name, Enabled); 1848 } 1849 // This exists purely to cut down on the number of virtual calls in 1850 // getDefaultFeatures which calls this repeatedly. 1851 static void setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 1852 StringRef Name, bool Enabled); 1853 virtual void getDefaultFeatures(llvm::StringMap<bool> &Features) const; 1854 virtual bool hasFeature(StringRef Feature) const; 1855 virtual bool handleTargetFeatures(std::vector<std::string> &Features, 1856 DiagnosticsEngine &Diags); 1857 virtual const char* getABI() const { 1858 if (getTriple().getArch() == llvm::Triple::x86_64 && SSELevel >= AVX) 1859 return "avx"; 1860 else if (getTriple().getArch() == llvm::Triple::x86 && 1861 MMX3DNowLevel == NoMMX3DNow) 1862 return "no-mmx"; 1863 return ""; 1864 } 1865 virtual bool setCPU(const std::string &Name) { 1866 CPU = llvm::StringSwitch<CPUKind>(Name) 1867 .Case("i386", CK_i386) 1868 .Case("i486", CK_i486) 1869 .Case("winchip-c6", CK_WinChipC6) 1870 .Case("winchip2", CK_WinChip2) 1871 .Case("c3", CK_C3) 1872 .Case("i586", CK_i586) 1873 .Case("pentium", CK_Pentium) 1874 .Case("pentium-mmx", CK_PentiumMMX) 1875 .Case("i686", CK_i686) 1876 .Case("pentiumpro", CK_PentiumPro) 1877 .Case("pentium2", CK_Pentium2) 1878 .Case("pentium3", CK_Pentium3) 1879 .Case("pentium3m", CK_Pentium3M) 1880 .Case("pentium-m", CK_PentiumM) 1881 .Case("c3-2", CK_C3_2) 1882 .Case("yonah", CK_Yonah) 1883 .Case("pentium4", CK_Pentium4) 1884 .Case("pentium4m", CK_Pentium4M) 1885 .Case("prescott", CK_Prescott) 1886 .Case("nocona", CK_Nocona) 1887 .Case("core2", CK_Core2) 1888 .Case("penryn", CK_Penryn) 1889 .Case("atom", CK_Atom) 1890 .Case("slm", CK_Silvermont) 1891 .Case("corei7", CK_Corei7) 1892 .Case("corei7-avx", CK_Corei7AVX) 1893 .Case("core-avx-i", CK_CoreAVXi) 1894 .Case("core-avx2", CK_CoreAVX2) 1895 .Case("knl", CK_KNL) 1896 .Case("k6", CK_K6) 1897 .Case("k6-2", CK_K6_2) 1898 .Case("k6-3", CK_K6_3) 1899 .Case("athlon", CK_Athlon) 1900 .Case("athlon-tbird", CK_AthlonThunderbird) 1901 .Case("athlon-4", CK_Athlon4) 1902 .Case("athlon-xp", CK_AthlonXP) 1903 .Case("athlon-mp", CK_AthlonMP) 1904 .Case("athlon64", CK_Athlon64) 1905 .Case("athlon64-sse3", CK_Athlon64SSE3) 1906 .Case("athlon-fx", CK_AthlonFX) 1907 .Case("k8", CK_K8) 1908 .Case("k8-sse3", CK_K8SSE3) 1909 .Case("opteron", CK_Opteron) 1910 .Case("opteron-sse3", CK_OpteronSSE3) 1911 .Case("amdfam10", CK_AMDFAM10) 1912 .Case("btver1", CK_BTVER1) 1913 .Case("btver2", CK_BTVER2) 1914 .Case("bdver1", CK_BDVER1) 1915 .Case("bdver2", CK_BDVER2) 1916 .Case("bdver3", CK_BDVER3) 1917 .Case("x86-64", CK_x86_64) 1918 .Case("geode", CK_Geode) 1919 .Default(CK_Generic); 1920 1921 // Perform any per-CPU checks necessary to determine if this CPU is 1922 // acceptable. 1923 // FIXME: This results in terrible diagnostics. Clang just says the CPU is 1924 // invalid without explaining *why*. 1925 switch (CPU) { 1926 case CK_Generic: 1927 // No processor selected! 1928 return false; 1929 1930 case CK_i386: 1931 case CK_i486: 1932 case CK_WinChipC6: 1933 case CK_WinChip2: 1934 case CK_C3: 1935 case CK_i586: 1936 case CK_Pentium: 1937 case CK_PentiumMMX: 1938 case CK_i686: 1939 case CK_PentiumPro: 1940 case CK_Pentium2: 1941 case CK_Pentium3: 1942 case CK_Pentium3M: 1943 case CK_PentiumM: 1944 case CK_Yonah: 1945 case CK_C3_2: 1946 case CK_Pentium4: 1947 case CK_Pentium4M: 1948 case CK_Prescott: 1949 case CK_K6: 1950 case CK_K6_2: 1951 case CK_K6_3: 1952 case CK_Athlon: 1953 case CK_AthlonThunderbird: 1954 case CK_Athlon4: 1955 case CK_AthlonXP: 1956 case CK_AthlonMP: 1957 case CK_Geode: 1958 // Only accept certain architectures when compiling in 32-bit mode. 1959 if (getTriple().getArch() != llvm::Triple::x86) 1960 return false; 1961 1962 // Fallthrough 1963 case CK_Nocona: 1964 case CK_Core2: 1965 case CK_Penryn: 1966 case CK_Atom: 1967 case CK_Silvermont: 1968 case CK_Corei7: 1969 case CK_Corei7AVX: 1970 case CK_CoreAVXi: 1971 case CK_CoreAVX2: 1972 case CK_KNL: 1973 case CK_Athlon64: 1974 case CK_Athlon64SSE3: 1975 case CK_AthlonFX: 1976 case CK_K8: 1977 case CK_K8SSE3: 1978 case CK_Opteron: 1979 case CK_OpteronSSE3: 1980 case CK_AMDFAM10: 1981 case CK_BTVER1: 1982 case CK_BTVER2: 1983 case CK_BDVER1: 1984 case CK_BDVER2: 1985 case CK_BDVER3: 1986 case CK_x86_64: 1987 return true; 1988 } 1989 llvm_unreachable("Unhandled CPU kind"); 1990 } 1991 1992 virtual bool setFPMath(StringRef Name); 1993 1994 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 1995 // We accept all non-ARM calling conventions 1996 return (CC == CC_X86ThisCall || 1997 CC == CC_X86FastCall || 1998 CC == CC_X86StdCall || 1999 CC == CC_C || 2000 CC == CC_X86Pascal || 2001 CC == CC_IntelOclBicc) ? CCCR_OK : CCCR_Warning; 2002 } 2003 2004 virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const { 2005 return MT == CCMT_Member ? CC_X86ThisCall : CC_C; 2006 } 2007 }; 2008 2009 bool X86TargetInfo::setFPMath(StringRef Name) { 2010 if (Name == "387") { 2011 FPMath = FP_387; 2012 return true; 2013 } 2014 if (Name == "sse") { 2015 FPMath = FP_SSE; 2016 return true; 2017 } 2018 return false; 2019 } 2020 2021 void X86TargetInfo::getDefaultFeatures(llvm::StringMap<bool> &Features) const { 2022 // FIXME: This *really* should not be here. 2023 2024 // X86_64 always has SSE2. 2025 if (getTriple().getArch() == llvm::Triple::x86_64) 2026 setFeatureEnabledImpl(Features, "sse2", true); 2027 2028 switch (CPU) { 2029 case CK_Generic: 2030 case CK_i386: 2031 case CK_i486: 2032 case CK_i586: 2033 case CK_Pentium: 2034 case CK_i686: 2035 case CK_PentiumPro: 2036 break; 2037 case CK_PentiumMMX: 2038 case CK_Pentium2: 2039 setFeatureEnabledImpl(Features, "mmx", true); 2040 break; 2041 case CK_Pentium3: 2042 case CK_Pentium3M: 2043 setFeatureEnabledImpl(Features, "sse", true); 2044 break; 2045 case CK_PentiumM: 2046 case CK_Pentium4: 2047 case CK_Pentium4M: 2048 case CK_x86_64: 2049 setFeatureEnabledImpl(Features, "sse2", true); 2050 break; 2051 case CK_Yonah: 2052 case CK_Prescott: 2053 case CK_Nocona: 2054 setFeatureEnabledImpl(Features, "sse3", true); 2055 setFeatureEnabledImpl(Features, "cx16", true); 2056 break; 2057 case CK_Core2: 2058 setFeatureEnabledImpl(Features, "ssse3", true); 2059 setFeatureEnabledImpl(Features, "cx16", true); 2060 break; 2061 case CK_Penryn: 2062 setFeatureEnabledImpl(Features, "sse4.1", true); 2063 setFeatureEnabledImpl(Features, "cx16", true); 2064 break; 2065 case CK_Atom: 2066 setFeatureEnabledImpl(Features, "ssse3", true); 2067 setFeatureEnabledImpl(Features, "cx16", true); 2068 break; 2069 case CK_Silvermont: 2070 setFeatureEnabledImpl(Features, "sse4.2", true); 2071 setFeatureEnabledImpl(Features, "aes", true); 2072 setFeatureEnabledImpl(Features, "cx16", true); 2073 setFeatureEnabledImpl(Features, "pclmul", true); 2074 break; 2075 case CK_Corei7: 2076 setFeatureEnabledImpl(Features, "sse4.2", true); 2077 setFeatureEnabledImpl(Features, "cx16", true); 2078 break; 2079 case CK_Corei7AVX: 2080 setFeatureEnabledImpl(Features, "avx", true); 2081 setFeatureEnabledImpl(Features, "aes", true); 2082 setFeatureEnabledImpl(Features, "cx16", true); 2083 setFeatureEnabledImpl(Features, "pclmul", true); 2084 break; 2085 case CK_CoreAVXi: 2086 setFeatureEnabledImpl(Features, "avx", true); 2087 setFeatureEnabledImpl(Features, "aes", true); 2088 setFeatureEnabledImpl(Features, "pclmul", true); 2089 setFeatureEnabledImpl(Features, "rdrnd", true); 2090 setFeatureEnabledImpl(Features, "f16c", true); 2091 break; 2092 case CK_CoreAVX2: 2093 setFeatureEnabledImpl(Features, "avx2", true); 2094 setFeatureEnabledImpl(Features, "aes", true); 2095 setFeatureEnabledImpl(Features, "pclmul", true); 2096 setFeatureEnabledImpl(Features, "lzcnt", true); 2097 setFeatureEnabledImpl(Features, "rdrnd", true); 2098 setFeatureEnabledImpl(Features, "f16c", true); 2099 setFeatureEnabledImpl(Features, "bmi", true); 2100 setFeatureEnabledImpl(Features, "bmi2", true); 2101 setFeatureEnabledImpl(Features, "rtm", true); 2102 setFeatureEnabledImpl(Features, "fma", true); 2103 setFeatureEnabledImpl(Features, "cx16", true); 2104 break; 2105 case CK_KNL: 2106 setFeatureEnabledImpl(Features, "avx512f", true); 2107 setFeatureEnabledImpl(Features, "avx512cd", true); 2108 setFeatureEnabledImpl(Features, "avx512er", true); 2109 setFeatureEnabledImpl(Features, "avx512pf", true); 2110 setFeatureEnabledImpl(Features, "aes", true); 2111 setFeatureEnabledImpl(Features, "pclmul", true); 2112 setFeatureEnabledImpl(Features, "lzcnt", true); 2113 setFeatureEnabledImpl(Features, "rdrnd", true); 2114 setFeatureEnabledImpl(Features, "f16c", true); 2115 setFeatureEnabledImpl(Features, "bmi", true); 2116 setFeatureEnabledImpl(Features, "bmi2", true); 2117 setFeatureEnabledImpl(Features, "rtm", true); 2118 setFeatureEnabledImpl(Features, "fma", true); 2119 break; 2120 case CK_K6: 2121 case CK_WinChipC6: 2122 setFeatureEnabledImpl(Features, "mmx", true); 2123 break; 2124 case CK_K6_2: 2125 case CK_K6_3: 2126 case CK_WinChip2: 2127 case CK_C3: 2128 setFeatureEnabledImpl(Features, "3dnow", true); 2129 break; 2130 case CK_Athlon: 2131 case CK_AthlonThunderbird: 2132 case CK_Geode: 2133 setFeatureEnabledImpl(Features, "3dnowa", true); 2134 break; 2135 case CK_Athlon4: 2136 case CK_AthlonXP: 2137 case CK_AthlonMP: 2138 setFeatureEnabledImpl(Features, "sse", true); 2139 setFeatureEnabledImpl(Features, "3dnowa", true); 2140 break; 2141 case CK_K8: 2142 case CK_Opteron: 2143 case CK_Athlon64: 2144 case CK_AthlonFX: 2145 setFeatureEnabledImpl(Features, "sse2", true); 2146 setFeatureEnabledImpl(Features, "3dnowa", true); 2147 break; 2148 case CK_K8SSE3: 2149 case CK_OpteronSSE3: 2150 case CK_Athlon64SSE3: 2151 setFeatureEnabledImpl(Features, "sse3", true); 2152 setFeatureEnabledImpl(Features, "3dnowa", true); 2153 break; 2154 case CK_AMDFAM10: 2155 setFeatureEnabledImpl(Features, "sse3", true); 2156 setFeatureEnabledImpl(Features, "sse4a", true); 2157 setFeatureEnabledImpl(Features, "3dnowa", true); 2158 setFeatureEnabledImpl(Features, "lzcnt", true); 2159 setFeatureEnabledImpl(Features, "popcnt", true); 2160 break; 2161 case CK_BTVER1: 2162 setFeatureEnabledImpl(Features, "ssse3", true); 2163 setFeatureEnabledImpl(Features, "sse4a", true); 2164 setFeatureEnabledImpl(Features, "cx16", true); 2165 setFeatureEnabledImpl(Features, "lzcnt", true); 2166 setFeatureEnabledImpl(Features, "popcnt", true); 2167 setFeatureEnabledImpl(Features, "prfchw", true); 2168 break; 2169 case CK_BTVER2: 2170 setFeatureEnabledImpl(Features, "avx", true); 2171 setFeatureEnabledImpl(Features, "sse4a", true); 2172 setFeatureEnabledImpl(Features, "lzcnt", true); 2173 setFeatureEnabledImpl(Features, "aes", true); 2174 setFeatureEnabledImpl(Features, "pclmul", true); 2175 setFeatureEnabledImpl(Features, "prfchw", true); 2176 setFeatureEnabledImpl(Features, "bmi", true); 2177 setFeatureEnabledImpl(Features, "f16c", true); 2178 setFeatureEnabledImpl(Features, "cx16", true); 2179 break; 2180 case CK_BDVER1: 2181 setFeatureEnabledImpl(Features, "xop", true); 2182 setFeatureEnabledImpl(Features, "lzcnt", true); 2183 setFeatureEnabledImpl(Features, "aes", true); 2184 setFeatureEnabledImpl(Features, "pclmul", true); 2185 setFeatureEnabledImpl(Features, "prfchw", true); 2186 setFeatureEnabledImpl(Features, "cx16", true); 2187 break; 2188 case CK_BDVER2: 2189 case CK_BDVER3: 2190 setFeatureEnabledImpl(Features, "xop", true); 2191 setFeatureEnabledImpl(Features, "lzcnt", true); 2192 setFeatureEnabledImpl(Features, "aes", true); 2193 setFeatureEnabledImpl(Features, "pclmul", true); 2194 setFeatureEnabledImpl(Features, "prfchw", true); 2195 setFeatureEnabledImpl(Features, "bmi", true); 2196 setFeatureEnabledImpl(Features, "fma", true); 2197 setFeatureEnabledImpl(Features, "f16c", true); 2198 setFeatureEnabledImpl(Features, "tbm", true); 2199 setFeatureEnabledImpl(Features, "cx16", true); 2200 break; 2201 case CK_C3_2: 2202 setFeatureEnabledImpl(Features, "sse", true); 2203 break; 2204 } 2205 } 2206 2207 void X86TargetInfo::setSSELevel(llvm::StringMap<bool> &Features, 2208 X86SSEEnum Level, bool Enabled) { 2209 if (Enabled) { 2210 switch (Level) { 2211 case AVX512F: 2212 Features["avx512f"] = true; 2213 case AVX2: 2214 Features["avx2"] = true; 2215 case AVX: 2216 Features["avx"] = true; 2217 case SSE42: 2218 Features["sse4.2"] = true; 2219 case SSE41: 2220 Features["sse4.1"] = true; 2221 case SSSE3: 2222 Features["ssse3"] = true; 2223 case SSE3: 2224 Features["sse3"] = true; 2225 case SSE2: 2226 Features["sse2"] = true; 2227 case SSE1: 2228 Features["sse"] = true; 2229 case NoSSE: 2230 break; 2231 } 2232 return; 2233 } 2234 2235 switch (Level) { 2236 case NoSSE: 2237 case SSE1: 2238 Features["sse"] = false; 2239 case SSE2: 2240 Features["sse2"] = Features["pclmul"] = Features["aes"] = 2241 Features["sha"] = false; 2242 case SSE3: 2243 Features["sse3"] = false; 2244 setXOPLevel(Features, NoXOP, false); 2245 case SSSE3: 2246 Features["ssse3"] = false; 2247 case SSE41: 2248 Features["sse4.1"] = false; 2249 case SSE42: 2250 Features["sse4.2"] = false; 2251 case AVX: 2252 Features["fma"] = Features["avx"] = Features["f16c"] = false; 2253 setXOPLevel(Features, FMA4, false); 2254 case AVX2: 2255 Features["avx2"] = false; 2256 case AVX512F: 2257 Features["avx512f"] = Features["avx512cd"] = Features["avx512er"] = 2258 Features["avx512pf"] = false; 2259 } 2260 } 2261 2262 void X86TargetInfo::setMMXLevel(llvm::StringMap<bool> &Features, 2263 MMX3DNowEnum Level, bool Enabled) { 2264 if (Enabled) { 2265 switch (Level) { 2266 case AMD3DNowAthlon: 2267 Features["3dnowa"] = true; 2268 case AMD3DNow: 2269 Features["3dnow"] = true; 2270 case MMX: 2271 Features["mmx"] = true; 2272 case NoMMX3DNow: 2273 break; 2274 } 2275 return; 2276 } 2277 2278 switch (Level) { 2279 case NoMMX3DNow: 2280 case MMX: 2281 Features["mmx"] = false; 2282 case AMD3DNow: 2283 Features["3dnow"] = false; 2284 case AMD3DNowAthlon: 2285 Features["3dnowa"] = false; 2286 } 2287 } 2288 2289 void X86TargetInfo::setXOPLevel(llvm::StringMap<bool> &Features, XOPEnum Level, 2290 bool Enabled) { 2291 if (Enabled) { 2292 switch (Level) { 2293 case XOP: 2294 Features["xop"] = true; 2295 case FMA4: 2296 Features["fma4"] = true; 2297 setSSELevel(Features, AVX, true); 2298 case SSE4A: 2299 Features["sse4a"] = true; 2300 setSSELevel(Features, SSE3, true); 2301 case NoXOP: 2302 break; 2303 } 2304 return; 2305 } 2306 2307 switch (Level) { 2308 case NoXOP: 2309 case SSE4A: 2310 Features["sse4a"] = false; 2311 case FMA4: 2312 Features["fma4"] = false; 2313 case XOP: 2314 Features["xop"] = false; 2315 } 2316 } 2317 2318 void X86TargetInfo::setFeatureEnabledImpl(llvm::StringMap<bool> &Features, 2319 StringRef Name, bool Enabled) { 2320 // FIXME: This *really* should not be here. We need some way of translating 2321 // options into llvm subtarget features. 2322 if (Name == "sse4") 2323 Name = "sse4.2"; 2324 2325 Features[Name] = Enabled; 2326 2327 if (Name == "mmx") { 2328 setMMXLevel(Features, MMX, Enabled); 2329 } else if (Name == "sse") { 2330 setSSELevel(Features, SSE1, Enabled); 2331 } else if (Name == "sse2") { 2332 setSSELevel(Features, SSE2, Enabled); 2333 } else if (Name == "sse3") { 2334 setSSELevel(Features, SSE3, Enabled); 2335 } else if (Name == "ssse3") { 2336 setSSELevel(Features, SSSE3, Enabled); 2337 } else if (Name == "sse4.2") { 2338 setSSELevel(Features, SSE42, Enabled); 2339 } else if (Name == "sse4.1") { 2340 setSSELevel(Features, SSE41, Enabled); 2341 } else if (Name == "3dnow") { 2342 setMMXLevel(Features, AMD3DNow, Enabled); 2343 } else if (Name == "3dnowa") { 2344 setMMXLevel(Features, AMD3DNowAthlon, Enabled); 2345 } else if (Name == "aes") { 2346 if (Enabled) 2347 setSSELevel(Features, SSE2, Enabled); 2348 } else if (Name == "pclmul") { 2349 if (Enabled) 2350 setSSELevel(Features, SSE2, Enabled); 2351 } else if (Name == "avx") { 2352 setSSELevel(Features, AVX, Enabled); 2353 } else if (Name == "avx2") { 2354 setSSELevel(Features, AVX2, Enabled); 2355 } else if (Name == "avx512f") { 2356 setSSELevel(Features, AVX512F, Enabled); 2357 } else if (Name == "avx512cd" || Name == "avx512er" || Name == "avx512pf") { 2358 if (Enabled) 2359 setSSELevel(Features, AVX512F, Enabled); 2360 } else if (Name == "fma") { 2361 if (Enabled) 2362 setSSELevel(Features, AVX, Enabled); 2363 } else if (Name == "fma4") { 2364 setXOPLevel(Features, FMA4, Enabled); 2365 } else if (Name == "xop") { 2366 setXOPLevel(Features, XOP, Enabled); 2367 } else if (Name == "sse4a") { 2368 setXOPLevel(Features, SSE4A, Enabled); 2369 } else if (Name == "f16c") { 2370 if (Enabled) 2371 setSSELevel(Features, AVX, Enabled); 2372 } else if (Name == "sha") { 2373 if (Enabled) 2374 setSSELevel(Features, SSE2, Enabled); 2375 } 2376 } 2377 2378 /// handleTargetFeatures - Perform initialization based on the user 2379 /// configured set of features. 2380 bool X86TargetInfo::handleTargetFeatures(std::vector<std::string> &Features, 2381 DiagnosticsEngine &Diags) { 2382 // Remember the maximum enabled sselevel. 2383 for (unsigned i = 0, e = Features.size(); i !=e; ++i) { 2384 // Ignore disabled features. 2385 if (Features[i][0] == '-') 2386 continue; 2387 2388 StringRef Feature = StringRef(Features[i]).substr(1); 2389 2390 if (Feature == "aes") { 2391 HasAES = true; 2392 continue; 2393 } 2394 2395 if (Feature == "pclmul") { 2396 HasPCLMUL = true; 2397 continue; 2398 } 2399 2400 if (Feature == "lzcnt") { 2401 HasLZCNT = true; 2402 continue; 2403 } 2404 2405 if (Feature == "rdrnd") { 2406 HasRDRND = true; 2407 continue; 2408 } 2409 2410 if (Feature == "bmi") { 2411 HasBMI = true; 2412 continue; 2413 } 2414 2415 if (Feature == "bmi2") { 2416 HasBMI2 = true; 2417 continue; 2418 } 2419 2420 if (Feature == "popcnt") { 2421 HasPOPCNT = true; 2422 continue; 2423 } 2424 2425 if (Feature == "rtm") { 2426 HasRTM = true; 2427 continue; 2428 } 2429 2430 if (Feature == "prfchw") { 2431 HasPRFCHW = true; 2432 continue; 2433 } 2434 2435 if (Feature == "rdseed") { 2436 HasRDSEED = true; 2437 continue; 2438 } 2439 2440 if (Feature == "tbm") { 2441 HasTBM = true; 2442 continue; 2443 } 2444 2445 if (Feature == "fma") { 2446 HasFMA = true; 2447 continue; 2448 } 2449 2450 if (Feature == "f16c") { 2451 HasF16C = true; 2452 continue; 2453 } 2454 2455 if (Feature == "avx512cd") { 2456 HasAVX512CD = true; 2457 continue; 2458 } 2459 2460 if (Feature == "avx512er") { 2461 HasAVX512ER = true; 2462 continue; 2463 } 2464 2465 if (Feature == "avx512pf") { 2466 HasAVX512PF = true; 2467 continue; 2468 } 2469 2470 if (Feature == "sha") { 2471 HasSHA = true; 2472 continue; 2473 } 2474 2475 if (Feature == "cx16") { 2476 HasCX16 = true; 2477 continue; 2478 } 2479 2480 assert(Features[i][0] == '+' && "Invalid target feature!"); 2481 X86SSEEnum Level = llvm::StringSwitch<X86SSEEnum>(Feature) 2482 .Case("avx512f", AVX512F) 2483 .Case("avx2", AVX2) 2484 .Case("avx", AVX) 2485 .Case("sse4.2", SSE42) 2486 .Case("sse4.1", SSE41) 2487 .Case("ssse3", SSSE3) 2488 .Case("sse3", SSE3) 2489 .Case("sse2", SSE2) 2490 .Case("sse", SSE1) 2491 .Default(NoSSE); 2492 SSELevel = std::max(SSELevel, Level); 2493 2494 MMX3DNowEnum ThreeDNowLevel = 2495 llvm::StringSwitch<MMX3DNowEnum>(Feature) 2496 .Case("3dnowa", AMD3DNowAthlon) 2497 .Case("3dnow", AMD3DNow) 2498 .Case("mmx", MMX) 2499 .Default(NoMMX3DNow); 2500 MMX3DNowLevel = std::max(MMX3DNowLevel, ThreeDNowLevel); 2501 2502 XOPEnum XLevel = llvm::StringSwitch<XOPEnum>(Feature) 2503 .Case("xop", XOP) 2504 .Case("fma4", FMA4) 2505 .Case("sse4a", SSE4A) 2506 .Default(NoXOP); 2507 XOPLevel = std::max(XOPLevel, XLevel); 2508 } 2509 2510 // Enable popcnt if sse4.2 is enabled and popcnt is not explicitly disabled. 2511 // Can't do this earlier because we need to be able to explicitly enable 2512 // popcnt and still disable sse4.2. 2513 if (!HasPOPCNT && SSELevel >= SSE42 && 2514 std::find(Features.begin(), Features.end(), "-popcnt") == Features.end()){ 2515 HasPOPCNT = true; 2516 Features.push_back("+popcnt"); 2517 } 2518 2519 // Enable prfchw if 3DNow! is enabled and prfchw is not explicitly disabled. 2520 if (!HasPRFCHW && MMX3DNowLevel >= AMD3DNow && 2521 std::find(Features.begin(), Features.end(), "-prfchw") == Features.end()){ 2522 HasPRFCHW = true; 2523 Features.push_back("+prfchw"); 2524 } 2525 2526 // LLVM doesn't have a separate switch for fpmath, so only accept it if it 2527 // matches the selected sse level. 2528 if (FPMath == FP_SSE && SSELevel < SSE1) { 2529 Diags.Report(diag::err_target_unsupported_fpmath) << "sse"; 2530 return false; 2531 } else if (FPMath == FP_387 && SSELevel >= SSE1) { 2532 Diags.Report(diag::err_target_unsupported_fpmath) << "387"; 2533 return false; 2534 } 2535 2536 // Don't tell the backend if we're turning off mmx; it will end up disabling 2537 // SSE, which we don't want. 2538 // Additionally, if SSE is enabled and mmx is not explicitly disabled, 2539 // then enable MMX. 2540 std::vector<std::string>::iterator it; 2541 it = std::find(Features.begin(), Features.end(), "-mmx"); 2542 if (it != Features.end()) 2543 Features.erase(it); 2544 else if (SSELevel > NoSSE) 2545 MMX3DNowLevel = std::max(MMX3DNowLevel, MMX); 2546 return true; 2547 } 2548 2549 /// X86TargetInfo::getTargetDefines - Return the set of the X86-specific macro 2550 /// definitions for this particular subtarget. 2551 void X86TargetInfo::getTargetDefines(const LangOptions &Opts, 2552 MacroBuilder &Builder) const { 2553 // Target identification. 2554 if (getTriple().getArch() == llvm::Triple::x86_64) { 2555 Builder.defineMacro("__amd64__"); 2556 Builder.defineMacro("__amd64"); 2557 Builder.defineMacro("__x86_64"); 2558 Builder.defineMacro("__x86_64__"); 2559 } else { 2560 DefineStd(Builder, "i386", Opts); 2561 } 2562 2563 // Subtarget options. 2564 // FIXME: We are hard-coding the tune parameters based on the CPU, but they 2565 // truly should be based on -mtune options. 2566 switch (CPU) { 2567 case CK_Generic: 2568 break; 2569 case CK_i386: 2570 // The rest are coming from the i386 define above. 2571 Builder.defineMacro("__tune_i386__"); 2572 break; 2573 case CK_i486: 2574 case CK_WinChipC6: 2575 case CK_WinChip2: 2576 case CK_C3: 2577 defineCPUMacros(Builder, "i486"); 2578 break; 2579 case CK_PentiumMMX: 2580 Builder.defineMacro("__pentium_mmx__"); 2581 Builder.defineMacro("__tune_pentium_mmx__"); 2582 // Fallthrough 2583 case CK_i586: 2584 case CK_Pentium: 2585 defineCPUMacros(Builder, "i586"); 2586 defineCPUMacros(Builder, "pentium"); 2587 break; 2588 case CK_Pentium3: 2589 case CK_Pentium3M: 2590 case CK_PentiumM: 2591 Builder.defineMacro("__tune_pentium3__"); 2592 // Fallthrough 2593 case CK_Pentium2: 2594 case CK_C3_2: 2595 Builder.defineMacro("__tune_pentium2__"); 2596 // Fallthrough 2597 case CK_PentiumPro: 2598 Builder.defineMacro("__tune_i686__"); 2599 Builder.defineMacro("__tune_pentiumpro__"); 2600 // Fallthrough 2601 case CK_i686: 2602 Builder.defineMacro("__i686"); 2603 Builder.defineMacro("__i686__"); 2604 // Strangely, __tune_i686__ isn't defined by GCC when CPU == i686. 2605 Builder.defineMacro("__pentiumpro"); 2606 Builder.defineMacro("__pentiumpro__"); 2607 break; 2608 case CK_Pentium4: 2609 case CK_Pentium4M: 2610 defineCPUMacros(Builder, "pentium4"); 2611 break; 2612 case CK_Yonah: 2613 case CK_Prescott: 2614 case CK_Nocona: 2615 defineCPUMacros(Builder, "nocona"); 2616 break; 2617 case CK_Core2: 2618 case CK_Penryn: 2619 defineCPUMacros(Builder, "core2"); 2620 break; 2621 case CK_Atom: 2622 defineCPUMacros(Builder, "atom"); 2623 break; 2624 case CK_Silvermont: 2625 defineCPUMacros(Builder, "slm"); 2626 break; 2627 case CK_Corei7: 2628 case CK_Corei7AVX: 2629 case CK_CoreAVXi: 2630 case CK_CoreAVX2: 2631 defineCPUMacros(Builder, "corei7"); 2632 break; 2633 case CK_KNL: 2634 defineCPUMacros(Builder, "knl"); 2635 break; 2636 case CK_K6_2: 2637 Builder.defineMacro("__k6_2__"); 2638 Builder.defineMacro("__tune_k6_2__"); 2639 // Fallthrough 2640 case CK_K6_3: 2641 if (CPU != CK_K6_2) { // In case of fallthrough 2642 // FIXME: GCC may be enabling these in cases where some other k6 2643 // architecture is specified but -m3dnow is explicitly provided. The 2644 // exact semantics need to be determined and emulated here. 2645 Builder.defineMacro("__k6_3__"); 2646 Builder.defineMacro("__tune_k6_3__"); 2647 } 2648 // Fallthrough 2649 case CK_K6: 2650 defineCPUMacros(Builder, "k6"); 2651 break; 2652 case CK_Athlon: 2653 case CK_AthlonThunderbird: 2654 case CK_Athlon4: 2655 case CK_AthlonXP: 2656 case CK_AthlonMP: 2657 defineCPUMacros(Builder, "athlon"); 2658 if (SSELevel != NoSSE) { 2659 Builder.defineMacro("__athlon_sse__"); 2660 Builder.defineMacro("__tune_athlon_sse__"); 2661 } 2662 break; 2663 case CK_K8: 2664 case CK_K8SSE3: 2665 case CK_x86_64: 2666 case CK_Opteron: 2667 case CK_OpteronSSE3: 2668 case CK_Athlon64: 2669 case CK_Athlon64SSE3: 2670 case CK_AthlonFX: 2671 defineCPUMacros(Builder, "k8"); 2672 break; 2673 case CK_AMDFAM10: 2674 defineCPUMacros(Builder, "amdfam10"); 2675 break; 2676 case CK_BTVER1: 2677 defineCPUMacros(Builder, "btver1"); 2678 break; 2679 case CK_BTVER2: 2680 defineCPUMacros(Builder, "btver2"); 2681 break; 2682 case CK_BDVER1: 2683 defineCPUMacros(Builder, "bdver1"); 2684 break; 2685 case CK_BDVER2: 2686 defineCPUMacros(Builder, "bdver2"); 2687 break; 2688 case CK_BDVER3: 2689 defineCPUMacros(Builder, "bdver3"); 2690 break; 2691 case CK_Geode: 2692 defineCPUMacros(Builder, "geode"); 2693 break; 2694 } 2695 2696 // Target properties. 2697 Builder.defineMacro("__LITTLE_ENDIAN__"); 2698 Builder.defineMacro("__REGISTER_PREFIX__", ""); 2699 2700 // Define __NO_MATH_INLINES on linux/x86 so that we don't get inline 2701 // functions in glibc header files that use FP Stack inline asm which the 2702 // backend can't deal with (PR879). 2703 Builder.defineMacro("__NO_MATH_INLINES"); 2704 2705 if (HasAES) 2706 Builder.defineMacro("__AES__"); 2707 2708 if (HasPCLMUL) 2709 Builder.defineMacro("__PCLMUL__"); 2710 2711 if (HasLZCNT) 2712 Builder.defineMacro("__LZCNT__"); 2713 2714 if (HasRDRND) 2715 Builder.defineMacro("__RDRND__"); 2716 2717 if (HasBMI) 2718 Builder.defineMacro("__BMI__"); 2719 2720 if (HasBMI2) 2721 Builder.defineMacro("__BMI2__"); 2722 2723 if (HasPOPCNT) 2724 Builder.defineMacro("__POPCNT__"); 2725 2726 if (HasRTM) 2727 Builder.defineMacro("__RTM__"); 2728 2729 if (HasPRFCHW) 2730 Builder.defineMacro("__PRFCHW__"); 2731 2732 if (HasRDSEED) 2733 Builder.defineMacro("__RDSEED__"); 2734 2735 if (HasTBM) 2736 Builder.defineMacro("__TBM__"); 2737 2738 switch (XOPLevel) { 2739 case XOP: 2740 Builder.defineMacro("__XOP__"); 2741 case FMA4: 2742 Builder.defineMacro("__FMA4__"); 2743 case SSE4A: 2744 Builder.defineMacro("__SSE4A__"); 2745 case NoXOP: 2746 break; 2747 } 2748 2749 if (HasFMA) 2750 Builder.defineMacro("__FMA__"); 2751 2752 if (HasF16C) 2753 Builder.defineMacro("__F16C__"); 2754 2755 if (HasAVX512CD) 2756 Builder.defineMacro("__AVX512CD__"); 2757 if (HasAVX512ER) 2758 Builder.defineMacro("__AVX512ER__"); 2759 if (HasAVX512PF) 2760 Builder.defineMacro("__AVX512PF__"); 2761 2762 if (HasSHA) 2763 Builder.defineMacro("__SHA__"); 2764 2765 if (HasCX16) 2766 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_16"); 2767 2768 // Each case falls through to the previous one here. 2769 switch (SSELevel) { 2770 case AVX512F: 2771 Builder.defineMacro("__AVX512F__"); 2772 case AVX2: 2773 Builder.defineMacro("__AVX2__"); 2774 case AVX: 2775 Builder.defineMacro("__AVX__"); 2776 case SSE42: 2777 Builder.defineMacro("__SSE4_2__"); 2778 case SSE41: 2779 Builder.defineMacro("__SSE4_1__"); 2780 case SSSE3: 2781 Builder.defineMacro("__SSSE3__"); 2782 case SSE3: 2783 Builder.defineMacro("__SSE3__"); 2784 case SSE2: 2785 Builder.defineMacro("__SSE2__"); 2786 Builder.defineMacro("__SSE2_MATH__"); // -mfp-math=sse always implied. 2787 case SSE1: 2788 Builder.defineMacro("__SSE__"); 2789 Builder.defineMacro("__SSE_MATH__"); // -mfp-math=sse always implied. 2790 case NoSSE: 2791 break; 2792 } 2793 2794 if (Opts.MicrosoftExt && getTriple().getArch() == llvm::Triple::x86) { 2795 switch (SSELevel) { 2796 case AVX512F: 2797 case AVX2: 2798 case AVX: 2799 case SSE42: 2800 case SSE41: 2801 case SSSE3: 2802 case SSE3: 2803 case SSE2: 2804 Builder.defineMacro("_M_IX86_FP", Twine(2)); 2805 break; 2806 case SSE1: 2807 Builder.defineMacro("_M_IX86_FP", Twine(1)); 2808 break; 2809 default: 2810 Builder.defineMacro("_M_IX86_FP", Twine(0)); 2811 } 2812 } 2813 2814 // Each case falls through to the previous one here. 2815 switch (MMX3DNowLevel) { 2816 case AMD3DNowAthlon: 2817 Builder.defineMacro("__3dNOW_A__"); 2818 case AMD3DNow: 2819 Builder.defineMacro("__3dNOW__"); 2820 case MMX: 2821 Builder.defineMacro("__MMX__"); 2822 case NoMMX3DNow: 2823 break; 2824 } 2825 2826 if (CPU >= CK_i486) { 2827 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 2828 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 2829 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 2830 } 2831 if (CPU >= CK_i586) 2832 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 2833 } 2834 2835 bool X86TargetInfo::hasFeature(StringRef Feature) const { 2836 return llvm::StringSwitch<bool>(Feature) 2837 .Case("aes", HasAES) 2838 .Case("avx", SSELevel >= AVX) 2839 .Case("avx2", SSELevel >= AVX2) 2840 .Case("avx512f", SSELevel >= AVX512F) 2841 .Case("avx512cd", HasAVX512CD) 2842 .Case("avx512er", HasAVX512ER) 2843 .Case("avx512pf", HasAVX512PF) 2844 .Case("bmi", HasBMI) 2845 .Case("bmi2", HasBMI2) 2846 .Case("cx16", HasCX16) 2847 .Case("f16c", HasF16C) 2848 .Case("fma", HasFMA) 2849 .Case("fma4", XOPLevel >= FMA4) 2850 .Case("tbm", HasTBM) 2851 .Case("lzcnt", HasLZCNT) 2852 .Case("rdrnd", HasRDRND) 2853 .Case("mm3dnow", MMX3DNowLevel >= AMD3DNow) 2854 .Case("mm3dnowa", MMX3DNowLevel >= AMD3DNowAthlon) 2855 .Case("mmx", MMX3DNowLevel >= MMX) 2856 .Case("pclmul", HasPCLMUL) 2857 .Case("popcnt", HasPOPCNT) 2858 .Case("rtm", HasRTM) 2859 .Case("prfchw", HasPRFCHW) 2860 .Case("rdseed", HasRDSEED) 2861 .Case("sha", HasSHA) 2862 .Case("sse", SSELevel >= SSE1) 2863 .Case("sse2", SSELevel >= SSE2) 2864 .Case("sse3", SSELevel >= SSE3) 2865 .Case("ssse3", SSELevel >= SSSE3) 2866 .Case("sse4.1", SSELevel >= SSE41) 2867 .Case("sse4.2", SSELevel >= SSE42) 2868 .Case("sse4a", XOPLevel >= SSE4A) 2869 .Case("x86", true) 2870 .Case("x86_32", getTriple().getArch() == llvm::Triple::x86) 2871 .Case("x86_64", getTriple().getArch() == llvm::Triple::x86_64) 2872 .Case("xop", XOPLevel >= XOP) 2873 .Default(false); 2874 } 2875 2876 bool 2877 X86TargetInfo::validateAsmConstraint(const char *&Name, 2878 TargetInfo::ConstraintInfo &Info) const { 2879 switch (*Name) { 2880 default: return false; 2881 case 'Y': // first letter of a pair: 2882 switch (*(Name+1)) { 2883 default: return false; 2884 case '0': // First SSE register. 2885 case 't': // Any SSE register, when SSE2 is enabled. 2886 case 'i': // Any SSE register, when SSE2 and inter-unit moves enabled. 2887 case 'm': // any MMX register, when inter-unit moves enabled. 2888 break; // falls through to setAllowsRegister. 2889 } 2890 case 'a': // eax. 2891 case 'b': // ebx. 2892 case 'c': // ecx. 2893 case 'd': // edx. 2894 case 'S': // esi. 2895 case 'D': // edi. 2896 case 'A': // edx:eax. 2897 case 'f': // any x87 floating point stack register. 2898 case 't': // top of floating point stack. 2899 case 'u': // second from top of floating point stack. 2900 case 'q': // Any register accessible as [r]l: a, b, c, and d. 2901 case 'y': // Any MMX register. 2902 case 'x': // Any SSE register. 2903 case 'Q': // Any register accessible as [r]h: a, b, c, and d. 2904 case 'R': // "Legacy" registers: ax, bx, cx, dx, di, si, sp, bp. 2905 case 'l': // "Index" registers: any general register that can be used as an 2906 // index in a base+index memory access. 2907 Info.setAllowsRegister(); 2908 return true; 2909 case 'C': // SSE floating point constant. 2910 case 'G': // x87 floating point constant. 2911 case 'e': // 32-bit signed integer constant for use with zero-extending 2912 // x86_64 instructions. 2913 case 'Z': // 32-bit unsigned integer constant for use with zero-extending 2914 // x86_64 instructions. 2915 return true; 2916 } 2917 } 2918 2919 2920 std::string 2921 X86TargetInfo::convertConstraint(const char *&Constraint) const { 2922 switch (*Constraint) { 2923 case 'a': return std::string("{ax}"); 2924 case 'b': return std::string("{bx}"); 2925 case 'c': return std::string("{cx}"); 2926 case 'd': return std::string("{dx}"); 2927 case 'S': return std::string("{si}"); 2928 case 'D': return std::string("{di}"); 2929 case 'p': // address 2930 return std::string("im"); 2931 case 't': // top of floating point stack. 2932 return std::string("{st}"); 2933 case 'u': // second from top of floating point stack. 2934 return std::string("{st(1)}"); // second from top of floating point stack. 2935 default: 2936 return std::string(1, *Constraint); 2937 } 2938 } 2939 } // end anonymous namespace 2940 2941 namespace { 2942 // X86-32 generic target 2943 class X86_32TargetInfo : public X86TargetInfo { 2944 public: 2945 X86_32TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 2946 DoubleAlign = LongLongAlign = 32; 2947 LongDoubleWidth = 96; 2948 LongDoubleAlign = 32; 2949 SuitableAlign = 128; 2950 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 2951 "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-" 2952 "a0:0:64-f80:32:32-n8:16:32-S128"; 2953 SizeType = UnsignedInt; 2954 PtrDiffType = SignedInt; 2955 IntPtrType = SignedInt; 2956 RegParmMax = 3; 2957 2958 // Use fpret for all types. 2959 RealTypeUsesObjCFPRet = ((1 << TargetInfo::Float) | 2960 (1 << TargetInfo::Double) | 2961 (1 << TargetInfo::LongDouble)); 2962 2963 // x86-32 has atomics up to 8 bytes 2964 // FIXME: Check that we actually have cmpxchg8b before setting 2965 // MaxAtomicInlineWidth. (cmpxchg8b is an i586 instruction.) 2966 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 2967 } 2968 virtual BuiltinVaListKind getBuiltinVaListKind() const { 2969 return TargetInfo::CharPtrBuiltinVaList; 2970 } 2971 2972 int getEHDataRegisterNumber(unsigned RegNo) const { 2973 if (RegNo == 0) return 0; 2974 if (RegNo == 1) return 2; 2975 return -1; 2976 } 2977 virtual bool validateInputSize(StringRef Constraint, 2978 unsigned Size) const { 2979 switch (Constraint[0]) { 2980 default: break; 2981 case 'a': 2982 case 'b': 2983 case 'c': 2984 case 'd': 2985 return Size <= 32; 2986 } 2987 2988 return true; 2989 } 2990 }; 2991 } // end anonymous namespace 2992 2993 namespace { 2994 class NetBSDI386TargetInfo : public NetBSDTargetInfo<X86_32TargetInfo> { 2995 public: 2996 NetBSDI386TargetInfo(const llvm::Triple &Triple) 2997 : NetBSDTargetInfo<X86_32TargetInfo>(Triple) {} 2998 2999 virtual unsigned getFloatEvalMethod() const { 3000 unsigned Major, Minor, Micro; 3001 getTriple().getOSVersion(Major, Minor, Micro); 3002 // New NetBSD uses the default rounding mode. 3003 if (Major >= 7 || (Major == 6 && Minor == 99 && Micro >= 26) || Major == 0) 3004 return X86_32TargetInfo::getFloatEvalMethod(); 3005 // NetBSD before 6.99.26 defaults to "double" rounding. 3006 return 1; 3007 } 3008 }; 3009 } // end anonymous namespace 3010 3011 namespace { 3012 class OpenBSDI386TargetInfo : public OpenBSDTargetInfo<X86_32TargetInfo> { 3013 public: 3014 OpenBSDI386TargetInfo(const llvm::Triple &Triple) 3015 : OpenBSDTargetInfo<X86_32TargetInfo>(Triple) { 3016 SizeType = UnsignedLong; 3017 IntPtrType = SignedLong; 3018 PtrDiffType = SignedLong; 3019 } 3020 }; 3021 } // end anonymous namespace 3022 3023 namespace { 3024 class BitrigI386TargetInfo : public BitrigTargetInfo<X86_32TargetInfo> { 3025 public: 3026 BitrigI386TargetInfo(const llvm::Triple &Triple) 3027 : BitrigTargetInfo<X86_32TargetInfo>(Triple) { 3028 SizeType = UnsignedLong; 3029 IntPtrType = SignedLong; 3030 PtrDiffType = SignedLong; 3031 } 3032 }; 3033 } // end anonymous namespace 3034 3035 namespace { 3036 class DarwinI386TargetInfo : public DarwinTargetInfo<X86_32TargetInfo> { 3037 public: 3038 DarwinI386TargetInfo(const llvm::Triple &Triple) 3039 : DarwinTargetInfo<X86_32TargetInfo>(Triple) { 3040 LongDoubleWidth = 128; 3041 LongDoubleAlign = 128; 3042 SuitableAlign = 128; 3043 MaxVectorAlign = 256; 3044 SizeType = UnsignedLong; 3045 IntPtrType = SignedLong; 3046 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3047 "i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-" 3048 "a0:0:64-f80:128:128-n8:16:32-S128"; 3049 HasAlignMac68kSupport = true; 3050 } 3051 3052 }; 3053 } // end anonymous namespace 3054 3055 namespace { 3056 // x86-32 Windows target 3057 class WindowsX86_32TargetInfo : public WindowsTargetInfo<X86_32TargetInfo> { 3058 public: 3059 WindowsX86_32TargetInfo(const llvm::Triple &Triple) 3060 : WindowsTargetInfo<X86_32TargetInfo>(Triple) { 3061 TLSSupported = false; 3062 WCharType = UnsignedShort; 3063 DoubleAlign = LongLongAlign = 64; 3064 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3065 "i64:64:64-f32:32:32-f64:64:64-f80:128:128-v64:64:64-" 3066 "v128:128:128-a0:0:64-f80:32:32-n8:16:32-S32"; 3067 } 3068 virtual void getTargetDefines(const LangOptions &Opts, 3069 MacroBuilder &Builder) const { 3070 WindowsTargetInfo<X86_32TargetInfo>::getTargetDefines(Opts, Builder); 3071 } 3072 }; 3073 } // end anonymous namespace 3074 3075 namespace { 3076 3077 // x86-32 Windows Visual Studio target 3078 class VisualStudioWindowsX86_32TargetInfo : public WindowsX86_32TargetInfo { 3079 public: 3080 VisualStudioWindowsX86_32TargetInfo(const llvm::Triple &Triple) 3081 : WindowsX86_32TargetInfo(Triple) { 3082 LongDoubleWidth = LongDoubleAlign = 64; 3083 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3084 } 3085 virtual void getTargetDefines(const LangOptions &Opts, 3086 MacroBuilder &Builder) const { 3087 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3088 WindowsX86_32TargetInfo::getVisualStudioDefines(Opts, Builder); 3089 // The value of the following reflects processor type. 3090 // 300=386, 400=486, 500=Pentium, 600=Blend (default) 3091 // We lost the original triple, so we use the default. 3092 Builder.defineMacro("_M_IX86", "600"); 3093 } 3094 }; 3095 } // end anonymous namespace 3096 3097 namespace { 3098 // x86-32 MinGW target 3099 class MinGWX86_32TargetInfo : public WindowsX86_32TargetInfo { 3100 public: 3101 MinGWX86_32TargetInfo(const llvm::Triple &Triple) 3102 : WindowsX86_32TargetInfo(Triple) {} 3103 virtual void getTargetDefines(const LangOptions &Opts, 3104 MacroBuilder &Builder) const { 3105 WindowsX86_32TargetInfo::getTargetDefines(Opts, Builder); 3106 DefineStd(Builder, "WIN32", Opts); 3107 DefineStd(Builder, "WINNT", Opts); 3108 Builder.defineMacro("_X86_"); 3109 Builder.defineMacro("__MSVCRT__"); 3110 Builder.defineMacro("__MINGW32__"); 3111 3112 // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)). 3113 // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions. 3114 if (Opts.MicrosoftExt) 3115 // Provide "as-is" __declspec. 3116 Builder.defineMacro("__declspec", "__declspec"); 3117 else 3118 // Provide alias of __attribute__ like mingw32-gcc. 3119 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3120 } 3121 }; 3122 } // end anonymous namespace 3123 3124 namespace { 3125 // x86-32 Cygwin target 3126 class CygwinX86_32TargetInfo : public X86_32TargetInfo { 3127 public: 3128 CygwinX86_32TargetInfo(const llvm::Triple &Triple) 3129 : X86_32TargetInfo(Triple) { 3130 TLSSupported = false; 3131 WCharType = UnsignedShort; 3132 DoubleAlign = LongLongAlign = 64; 3133 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3134 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-" 3135 "a0:0:64-f80:32:32-n8:16:32-S32"; 3136 } 3137 virtual void getTargetDefines(const LangOptions &Opts, 3138 MacroBuilder &Builder) const { 3139 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3140 Builder.defineMacro("_X86_"); 3141 Builder.defineMacro("__CYGWIN__"); 3142 Builder.defineMacro("__CYGWIN32__"); 3143 DefineStd(Builder, "unix", Opts); 3144 if (Opts.CPlusPlus) 3145 Builder.defineMacro("_GNU_SOURCE"); 3146 } 3147 }; 3148 } // end anonymous namespace 3149 3150 namespace { 3151 // x86-32 Haiku target 3152 class HaikuX86_32TargetInfo : public X86_32TargetInfo { 3153 public: 3154 HaikuX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3155 SizeType = UnsignedLong; 3156 IntPtrType = SignedLong; 3157 PtrDiffType = SignedLong; 3158 ProcessIDType = SignedLong; 3159 this->UserLabelPrefix = ""; 3160 this->TLSSupported = false; 3161 } 3162 virtual void getTargetDefines(const LangOptions &Opts, 3163 MacroBuilder &Builder) const { 3164 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3165 Builder.defineMacro("__INTEL__"); 3166 Builder.defineMacro("__HAIKU__"); 3167 } 3168 }; 3169 } // end anonymous namespace 3170 3171 // RTEMS Target 3172 template<typename Target> 3173 class RTEMSTargetInfo : public OSTargetInfo<Target> { 3174 protected: 3175 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 3176 MacroBuilder &Builder) const { 3177 // RTEMS defines; list based off of gcc output 3178 3179 Builder.defineMacro("__rtems__"); 3180 Builder.defineMacro("__ELF__"); 3181 } 3182 3183 public: 3184 RTEMSTargetInfo(const llvm::Triple &Triple) : OSTargetInfo<Target>(Triple) { 3185 this->UserLabelPrefix = ""; 3186 3187 switch (Triple.getArch()) { 3188 default: 3189 case llvm::Triple::x86: 3190 // this->MCountName = ".mcount"; 3191 break; 3192 case llvm::Triple::mips: 3193 case llvm::Triple::mipsel: 3194 case llvm::Triple::ppc: 3195 case llvm::Triple::ppc64: 3196 case llvm::Triple::ppc64le: 3197 // this->MCountName = "_mcount"; 3198 break; 3199 case llvm::Triple::arm: 3200 // this->MCountName = "__mcount"; 3201 break; 3202 } 3203 } 3204 }; 3205 3206 namespace { 3207 // x86-32 RTEMS target 3208 class RTEMSX86_32TargetInfo : public X86_32TargetInfo { 3209 public: 3210 RTEMSX86_32TargetInfo(const llvm::Triple &Triple) : X86_32TargetInfo(Triple) { 3211 SizeType = UnsignedLong; 3212 IntPtrType = SignedLong; 3213 PtrDiffType = SignedLong; 3214 this->UserLabelPrefix = ""; 3215 } 3216 virtual void getTargetDefines(const LangOptions &Opts, 3217 MacroBuilder &Builder) const { 3218 X86_32TargetInfo::getTargetDefines(Opts, Builder); 3219 Builder.defineMacro("__INTEL__"); 3220 Builder.defineMacro("__rtems__"); 3221 } 3222 }; 3223 } // end anonymous namespace 3224 3225 namespace { 3226 // x86-64 generic target 3227 class X86_64TargetInfo : public X86TargetInfo { 3228 public: 3229 X86_64TargetInfo(const llvm::Triple &Triple) : X86TargetInfo(Triple) { 3230 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 3231 LongDoubleWidth = 128; 3232 LongDoubleAlign = 128; 3233 LargeArrayMinWidth = 128; 3234 LargeArrayAlign = 128; 3235 SuitableAlign = 128; 3236 IntMaxType = SignedLong; 3237 UIntMaxType = UnsignedLong; 3238 Int64Type = SignedLong; 3239 RegParmMax = 6; 3240 3241 DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3242 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-" 3243 "a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"; 3244 3245 // Use fpret only for long double. 3246 RealTypeUsesObjCFPRet = (1 << TargetInfo::LongDouble); 3247 3248 // Use fp2ret for _Complex long double. 3249 ComplexLongDoubleUsesFP2Ret = true; 3250 3251 // x86-64 has atomics up to 16 bytes. 3252 // FIXME: Once the backend is fixed, increase MaxAtomicInlineWidth to 128 3253 // on CPUs with cmpxchg16b 3254 MaxAtomicPromoteWidth = 128; 3255 MaxAtomicInlineWidth = 64; 3256 } 3257 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3258 return TargetInfo::X86_64ABIBuiltinVaList; 3259 } 3260 3261 int getEHDataRegisterNumber(unsigned RegNo) const { 3262 if (RegNo == 0) return 0; 3263 if (RegNo == 1) return 1; 3264 return -1; 3265 } 3266 3267 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 3268 return (CC == CC_C || 3269 CC == CC_IntelOclBicc || 3270 CC == CC_X86_64Win64) ? CCCR_OK : CCCR_Warning; 3271 } 3272 3273 virtual CallingConv getDefaultCallingConv(CallingConvMethodType MT) const { 3274 return CC_C; 3275 } 3276 3277 }; 3278 } // end anonymous namespace 3279 3280 namespace { 3281 // x86-64 Windows target 3282 class WindowsX86_64TargetInfo : public WindowsTargetInfo<X86_64TargetInfo> { 3283 public: 3284 WindowsX86_64TargetInfo(const llvm::Triple &Triple) 3285 : WindowsTargetInfo<X86_64TargetInfo>(Triple) { 3286 TLSSupported = false; 3287 WCharType = UnsignedShort; 3288 LongWidth = LongAlign = 32; 3289 DoubleAlign = LongLongAlign = 64; 3290 IntMaxType = SignedLongLong; 3291 UIntMaxType = UnsignedLongLong; 3292 Int64Type = SignedLongLong; 3293 SizeType = UnsignedLongLong; 3294 PtrDiffType = SignedLongLong; 3295 IntPtrType = SignedLongLong; 3296 this->UserLabelPrefix = ""; 3297 } 3298 virtual void getTargetDefines(const LangOptions &Opts, 3299 MacroBuilder &Builder) const { 3300 WindowsTargetInfo<X86_64TargetInfo>::getTargetDefines(Opts, Builder); 3301 Builder.defineMacro("_WIN64"); 3302 } 3303 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3304 return TargetInfo::CharPtrBuiltinVaList; 3305 } 3306 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 3307 return (CC == CC_C || 3308 CC == CC_IntelOclBicc || 3309 CC == CC_X86_64SysV) ? CCCR_OK : CCCR_Warning; 3310 } 3311 }; 3312 } // end anonymous namespace 3313 3314 namespace { 3315 // x86-64 Windows Visual Studio target 3316 class VisualStudioWindowsX86_64TargetInfo : public WindowsX86_64TargetInfo { 3317 public: 3318 VisualStudioWindowsX86_64TargetInfo(const llvm::Triple &Triple) 3319 : WindowsX86_64TargetInfo(Triple) { 3320 LongDoubleWidth = LongDoubleAlign = 64; 3321 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 3322 } 3323 virtual void getTargetDefines(const LangOptions &Opts, 3324 MacroBuilder &Builder) const { 3325 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3326 WindowsX86_64TargetInfo::getVisualStudioDefines(Opts, Builder); 3327 Builder.defineMacro("_M_X64"); 3328 Builder.defineMacro("_M_AMD64"); 3329 } 3330 }; 3331 } // end anonymous namespace 3332 3333 namespace { 3334 // x86-64 MinGW target 3335 class MinGWX86_64TargetInfo : public WindowsX86_64TargetInfo { 3336 public: 3337 MinGWX86_64TargetInfo(const llvm::Triple &Triple) 3338 : WindowsX86_64TargetInfo(Triple) {} 3339 virtual void getTargetDefines(const LangOptions &Opts, 3340 MacroBuilder &Builder) const { 3341 WindowsX86_64TargetInfo::getTargetDefines(Opts, Builder); 3342 DefineStd(Builder, "WIN64", Opts); 3343 Builder.defineMacro("__MSVCRT__"); 3344 Builder.defineMacro("__MINGW32__"); 3345 Builder.defineMacro("__MINGW64__"); 3346 3347 // mingw32-gcc provides __declspec(a) as alias of __attribute__((a)). 3348 // In contrast, clang-cc1 provides __declspec(a) with -fms-extensions. 3349 if (Opts.MicrosoftExt) 3350 // Provide "as-is" __declspec. 3351 Builder.defineMacro("__declspec", "__declspec"); 3352 else 3353 // Provide alias of __attribute__ like mingw32-gcc. 3354 Builder.defineMacro("__declspec(a)", "__attribute__((a))"); 3355 } 3356 }; 3357 } // end anonymous namespace 3358 3359 namespace { 3360 class DarwinX86_64TargetInfo : public DarwinTargetInfo<X86_64TargetInfo> { 3361 public: 3362 DarwinX86_64TargetInfo(const llvm::Triple &Triple) 3363 : DarwinTargetInfo<X86_64TargetInfo>(Triple) { 3364 Int64Type = SignedLongLong; 3365 MaxVectorAlign = 256; 3366 } 3367 }; 3368 } // end anonymous namespace 3369 3370 namespace { 3371 class OpenBSDX86_64TargetInfo : public OpenBSDTargetInfo<X86_64TargetInfo> { 3372 public: 3373 OpenBSDX86_64TargetInfo(const llvm::Triple &Triple) 3374 : OpenBSDTargetInfo<X86_64TargetInfo>(Triple) { 3375 IntMaxType = SignedLongLong; 3376 UIntMaxType = UnsignedLongLong; 3377 Int64Type = SignedLongLong; 3378 } 3379 }; 3380 } // end anonymous namespace 3381 3382 namespace { 3383 class BitrigX86_64TargetInfo : public BitrigTargetInfo<X86_64TargetInfo> { 3384 public: 3385 BitrigX86_64TargetInfo(const llvm::Triple &Triple) 3386 : BitrigTargetInfo<X86_64TargetInfo>(Triple) { 3387 IntMaxType = SignedLongLong; 3388 UIntMaxType = UnsignedLongLong; 3389 Int64Type = SignedLongLong; 3390 } 3391 }; 3392 } 3393 3394 namespace { 3395 class AArch64TargetInfo : public TargetInfo { 3396 static const char * const GCCRegNames[]; 3397 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3398 3399 enum FPUModeEnum { 3400 FPUMode, 3401 NeonMode 3402 }; 3403 3404 unsigned FPU; 3405 unsigned Crypto; 3406 static const Builtin::Info BuiltinInfo[]; 3407 3408 public: 3409 AArch64TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 3410 BigEndian = false; 3411 LongWidth = LongAlign = 64; 3412 LongDoubleWidth = LongDoubleAlign = 128; 3413 PointerWidth = PointerAlign = 64; 3414 SuitableAlign = 128; 3415 DescriptionString = "e-p:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3416 "i64:64:64-i128:128:128-f32:32:32-f64:64:64-" 3417 "f128:128:128-n32:64-S128"; 3418 3419 WCharType = UnsignedInt; 3420 LongDoubleFormat = &llvm::APFloat::IEEEquad; 3421 3422 // AArch64 backend supports 64-bit operations at the moment. In principle 3423 // 128-bit is possible if register-pairs are used. 3424 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 3425 3426 TheCXXABI.set(TargetCXXABI::GenericAArch64); 3427 } 3428 virtual void getTargetDefines(const LangOptions &Opts, 3429 MacroBuilder &Builder) const { 3430 // GCC defines theses currently 3431 Builder.defineMacro("__aarch64__"); 3432 Builder.defineMacro("__AARCH64EL__"); 3433 3434 // ACLE predefines. Many can only have one possible value on v8 AArch64. 3435 Builder.defineMacro("__ARM_ACLE", "200"); 3436 Builder.defineMacro("__ARM_ARCH", "8"); 3437 Builder.defineMacro("__ARM_ARCH_PROFILE", "'A'"); 3438 3439 Builder.defineMacro("__ARM_64BIT_STATE"); 3440 Builder.defineMacro("__ARM_PCS_AAPCS64"); 3441 Builder.defineMacro("__ARM_ARCH_ISA_A64"); 3442 3443 Builder.defineMacro("__ARM_FEATURE_UNALIGNED"); 3444 Builder.defineMacro("__ARM_FEATURE_CLZ"); 3445 Builder.defineMacro("__ARM_FEATURE_FMA"); 3446 Builder.defineMacro("__ARM_FEATURE_DIV"); 3447 3448 Builder.defineMacro("__ARM_ALIGN_MAX_STACK_PWR", "4"); 3449 3450 // 0xe implies support for half, single and double precision operations. 3451 Builder.defineMacro("__ARM_FP", "0xe"); 3452 3453 // PCS specifies this for SysV variants, which is all we support. Other ABIs 3454 // may choose __ARM_FP16_FORMAT_ALTERNATIVE. 3455 Builder.defineMacro("__ARM_FP16_FORMAT_IEEE"); 3456 3457 if (Opts.FastMath || Opts.FiniteMathOnly) 3458 Builder.defineMacro("__ARM_FP_FAST"); 3459 3460 if ((Opts.C99 || Opts.C11) && !Opts.Freestanding) 3461 Builder.defineMacro("__ARM_FP_FENV_ROUNDING"); 3462 3463 Builder.defineMacro("__ARM_SIZEOF_WCHAR_T", 3464 Opts.ShortWChar ? "2" : "4"); 3465 3466 Builder.defineMacro("__ARM_SIZEOF_MINIMAL_ENUM", 3467 Opts.ShortEnums ? "1" : "4"); 3468 3469 if (BigEndian) 3470 Builder.defineMacro("__AARCH_BIG_ENDIAN"); 3471 3472 if (FPU == NeonMode) { 3473 Builder.defineMacro("__ARM_NEON"); 3474 // 64-bit NEON supports half, single and double precision operations. 3475 Builder.defineMacro("__ARM_NEON_FP", "7"); 3476 } 3477 3478 if (Crypto) { 3479 Builder.defineMacro("__ARM_FEATURE_CRYPTO"); 3480 } 3481 } 3482 virtual void getTargetBuiltins(const Builtin::Info *&Records, 3483 unsigned &NumRecords) const { 3484 Records = BuiltinInfo; 3485 NumRecords = clang::AArch64::LastTSBuiltin-Builtin::FirstTSBuiltin; 3486 } 3487 virtual bool hasFeature(StringRef Feature) const { 3488 return Feature == "aarch64" || (Feature == "neon" && FPU == NeonMode); 3489 } 3490 3491 virtual bool setCPU(const std::string &Name) { 3492 return llvm::StringSwitch<bool>(Name) 3493 .Case("generic", true) 3494 .Cases("cortex-a53", "cortex-a57", true) 3495 .Default(false); 3496 } 3497 3498 virtual bool handleTargetFeatures(std::vector<std::string> &Features, 3499 DiagnosticsEngine &Diags) { 3500 FPU = FPUMode; 3501 Crypto = 0; 3502 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 3503 if (Features[i] == "+neon") 3504 FPU = NeonMode; 3505 if (Features[i] == "+crypto") 3506 Crypto = 1; 3507 } 3508 return true; 3509 } 3510 3511 virtual void getGCCRegNames(const char *const *&Names, 3512 unsigned &NumNames) const; 3513 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 3514 unsigned &NumAliases) const; 3515 3516 virtual bool isCLZForZeroUndef() const { return false; } 3517 3518 virtual bool validateAsmConstraint(const char *&Name, 3519 TargetInfo::ConstraintInfo &Info) const { 3520 switch (*Name) { 3521 default: return false; 3522 case 'w': // An FP/SIMD vector register 3523 Info.setAllowsRegister(); 3524 return true; 3525 case 'I': // Constant that can be used with an ADD instruction 3526 case 'J': // Constant that can be used with a SUB instruction 3527 case 'K': // Constant that can be used with a 32-bit logical instruction 3528 case 'L': // Constant that can be used with a 64-bit logical instruction 3529 case 'M': // Constant that can be used as a 32-bit MOV immediate 3530 case 'N': // Constant that can be used as a 64-bit MOV immediate 3531 case 'Y': // Floating point constant zero 3532 case 'Z': // Integer constant zero 3533 return true; 3534 case 'Q': // A memory reference with base register and no offset 3535 Info.setAllowsMemory(); 3536 return true; 3537 case 'S': // A symbolic address 3538 Info.setAllowsRegister(); 3539 return true; 3540 case 'U': 3541 // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be 3542 // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be 3543 // Usa: An absolute symbolic address 3544 // Ush: The high part (bits 32:12) of a pc-relative symbolic address 3545 llvm_unreachable("FIXME: Unimplemented support for bizarre constraints"); 3546 } 3547 } 3548 3549 virtual const char *getClobbers() const { 3550 // There are no AArch64 clobbers shared by all asm statements. 3551 return ""; 3552 } 3553 3554 virtual BuiltinVaListKind getBuiltinVaListKind() const { 3555 return TargetInfo::AArch64ABIBuiltinVaList; 3556 } 3557 }; 3558 3559 const char * const AArch64TargetInfo::GCCRegNames[] = { 3560 "w0", "w1", "w2", "w3", "w4", "w5", "w6", "w7", 3561 "w8", "w9", "w10", "w11", "w12", "w13", "w14", "w15", 3562 "w16", "w17", "w18", "w19", "w20", "w21", "w22", "w23", 3563 "w24", "w25", "w26", "w27", "w28", "w29", "w30", "wsp", "wzr", 3564 3565 "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", 3566 "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", 3567 "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", 3568 "x24", "x25", "x26", "x27", "x28", "x29", "x30", "sp", "xzr", 3569 3570 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7", 3571 "b8", "b9", "b10", "b11", "b12", "b13", "b14", "b15", 3572 "b16", "b17", "b18", "b19", "b20", "b21", "b22", "b23", 3573 "b24", "b25", "b26", "b27", "b28", "b29", "b30", "b31", 3574 3575 "h0", "h1", "h2", "h3", "h4", "h5", "h6", "h7", 3576 "h8", "h9", "h10", "h11", "h12", "h13", "h14", "h15", 3577 "h16", "h17", "h18", "h19", "h20", "h21", "h22", "h23", 3578 "h24", "h25", "h26", "h27", "h28", "h29", "h30", "h31", 3579 3580 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 3581 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 3582 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 3583 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 3584 3585 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 3586 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 3587 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 3588 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 3589 3590 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 3591 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15", 3592 "q16", "q17", "q18", "q19", "q20", "q21", "q22", "q23", 3593 "q24", "q25", "q26", "q27", "q28", "q29", "q30", "q31" 3594 }; 3595 3596 void AArch64TargetInfo::getGCCRegNames(const char * const *&Names, 3597 unsigned &NumNames) const { 3598 Names = GCCRegNames; 3599 NumNames = llvm::array_lengthof(GCCRegNames); 3600 } 3601 3602 const TargetInfo::GCCRegAlias AArch64TargetInfo::GCCRegAliases[] = { 3603 { { "x16" }, "ip0"}, 3604 { { "x17" }, "ip1"}, 3605 { { "x29" }, "fp" }, 3606 { { "x30" }, "lr" } 3607 }; 3608 3609 void AArch64TargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 3610 unsigned &NumAliases) const { 3611 Aliases = GCCRegAliases; 3612 NumAliases = llvm::array_lengthof(GCCRegAliases); 3613 3614 } 3615 3616 const Builtin::Info AArch64TargetInfo::BuiltinInfo[] = { 3617 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 3618 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 3619 ALL_LANGUAGES }, 3620 #include "clang/Basic/BuiltinsAArch64.def" 3621 }; 3622 3623 } // end anonymous namespace 3624 3625 namespace { 3626 class ARMTargetInfo : public TargetInfo { 3627 // Possible FPU choices. 3628 enum FPUMode { 3629 VFP2FPU = (1 << 0), 3630 VFP3FPU = (1 << 1), 3631 VFP4FPU = (1 << 2), 3632 NeonFPU = (1 << 3), 3633 FPARMV8 = (1 << 4) 3634 }; 3635 3636 // Possible HWDiv features. 3637 enum HWDivMode { 3638 HWDivThumb = (1 << 0), 3639 HWDivARM = (1 << 1) 3640 }; 3641 3642 static bool FPUModeIsVFP(FPUMode Mode) { 3643 return Mode & (VFP2FPU | VFP3FPU | VFP4FPU | NeonFPU | FPARMV8); 3644 } 3645 3646 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 3647 static const char * const GCCRegNames[]; 3648 3649 std::string ABI, CPU; 3650 3651 enum { 3652 FP_Default, 3653 FP_VFP, 3654 FP_Neon 3655 } FPMath; 3656 3657 unsigned FPU : 5; 3658 3659 unsigned IsAAPCS : 1; 3660 unsigned IsThumb : 1; 3661 unsigned HWDiv : 2; 3662 3663 // Initialized via features. 3664 unsigned SoftFloat : 1; 3665 unsigned SoftFloatABI : 1; 3666 3667 unsigned CRC : 1; 3668 3669 static const Builtin::Info BuiltinInfo[]; 3670 3671 static bool shouldUseInlineAtomic(const llvm::Triple &T) { 3672 // On linux, binaries targeting old cpus call functions in libgcc to 3673 // perform atomic operations. The implementation in libgcc then calls into 3674 // the kernel which on armv6 and newer uses ldrex and strex. The net result 3675 // is that if we assume the kernel is at least as recent as the hardware, 3676 // it is safe to use atomic instructions on armv6 and newer. 3677 if (!T.isOSLinux() && 3678 T.getOS() != llvm::Triple::FreeBSD && 3679 T.getOS() != llvm::Triple::Bitrig) 3680 return false; 3681 StringRef ArchName = T.getArchName(); 3682 if (T.getArch() == llvm::Triple::arm) { 3683 if (!ArchName.startswith("armv")) 3684 return false; 3685 StringRef VersionStr = ArchName.substr(4); 3686 unsigned Version; 3687 if (VersionStr.getAsInteger(10, Version)) 3688 return false; 3689 return Version >= 6; 3690 } 3691 assert(T.getArch() == llvm::Triple::thumb); 3692 if (!ArchName.startswith("thumbv")) 3693 return false; 3694 StringRef VersionStr = ArchName.substr(6); 3695 unsigned Version; 3696 if (VersionStr.getAsInteger(10, Version)) 3697 return false; 3698 return Version >= 7; 3699 } 3700 3701 public: 3702 ARMTargetInfo(const llvm::Triple &Triple) 3703 : TargetInfo(Triple), ABI("aapcs-linux"), CPU("arm1136j-s"), 3704 FPMath(FP_Default), IsAAPCS(true) { 3705 BigEndian = false; 3706 SizeType = UnsignedInt; 3707 PtrDiffType = SignedInt; 3708 // AAPCS 7.1.1, ARM-Linux ABI 2.4: type of wchar_t is unsigned int. 3709 WCharType = UnsignedInt; 3710 3711 // {} in inline assembly are neon specifiers, not assembly variant 3712 // specifiers. 3713 NoAsmVariants = true; 3714 3715 // FIXME: Should we just treat this as a feature? 3716 IsThumb = getTriple().getArchName().startswith("thumb"); 3717 if (IsThumb) { 3718 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 3719 // so set preferred for small types to 32. 3720 DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-" 3721 "i64:64:64-f32:32:32-f64:64:64-" 3722 "v64:64:64-v128:64:128-a0:0:32-n32-S64"); 3723 } else { 3724 DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3725 "i64:64:64-f32:32:32-f64:64:64-" 3726 "v64:64:64-v128:64:128-a0:0:64-n32-S64"); 3727 } 3728 3729 // ARM targets default to using the ARM C++ ABI. 3730 TheCXXABI.set(TargetCXXABI::GenericARM); 3731 3732 // ARM has atomics up to 8 bytes 3733 MaxAtomicPromoteWidth = 64; 3734 if (shouldUseInlineAtomic(getTriple())) 3735 MaxAtomicInlineWidth = 64; 3736 3737 // Do force alignment of members that follow zero length bitfields. If 3738 // the alignment of the zero-length bitfield is greater than the member 3739 // that follows it, `bar', `bar' will be aligned as the type of the 3740 // zero length bitfield. 3741 UseZeroLengthBitfieldAlignment = true; 3742 } 3743 virtual const char *getABI() const { return ABI.c_str(); } 3744 virtual bool setABI(const std::string &Name) { 3745 ABI = Name; 3746 3747 // The defaults (above) are for AAPCS, check if we need to change them. 3748 // 3749 // FIXME: We need support for -meabi... we could just mangle it into the 3750 // name. 3751 if (Name == "apcs-gnu") { 3752 DoubleAlign = LongLongAlign = LongDoubleAlign = SuitableAlign = 32; 3753 // size_t is unsigned int on FreeBSD. 3754 if (getTriple().getOS() != llvm::Triple::FreeBSD) 3755 SizeType = UnsignedLong; 3756 3757 // Revert to using SignedInt on apcs-gnu to comply with existing behaviour. 3758 WCharType = SignedInt; 3759 3760 // Do not respect the alignment of bit-field types when laying out 3761 // structures. This corresponds to PCC_BITFIELD_TYPE_MATTERS in gcc. 3762 UseBitFieldTypeAlignment = false; 3763 3764 /// gcc forces the alignment to 4 bytes, regardless of the type of the 3765 /// zero length bitfield. This corresponds to EMPTY_FIELD_BOUNDARY in 3766 /// gcc. 3767 ZeroLengthBitfieldBoundary = 32; 3768 3769 IsAAPCS = false; 3770 3771 if (IsThumb) { 3772 // Thumb1 add sp, #imm requires the immediate value be multiple of 4, 3773 // so set preferred for small types to 32. 3774 DescriptionString = ("e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-" 3775 "i64:32:64-f32:32:32-f64:32:64-" 3776 "v64:32:64-v128:32:128-a0:0:32-n32-S32"); 3777 } else { 3778 DescriptionString = ("e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 3779 "i64:32:64-f32:32:32-f64:32:64-" 3780 "v64:32:64-v128:32:128-a0:0:32-n32-S32"); 3781 } 3782 3783 // FIXME: Override "preferred align" for double and long long. 3784 } else if (Name == "aapcs" || Name == "aapcs-vfp") { 3785 // size_t is unsigned long on Darwin. 3786 if (getTriple().isOSDarwin()) 3787 SizeType = UnsignedLong; 3788 IsAAPCS = true; 3789 // FIXME: Enumerated types are variable width in straight AAPCS. 3790 } else if (Name == "aapcs-linux") { 3791 IsAAPCS = true; 3792 } else 3793 return false; 3794 3795 return true; 3796 } 3797 3798 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 3799 StringRef ArchName = getTriple().getArchName(); 3800 if (CPU == "arm1136jf-s" || CPU == "arm1176jzf-s" || CPU == "mpcore") 3801 Features["vfp2"] = true; 3802 else if (CPU == "cortex-a8" || CPU == "cortex-a9" || 3803 CPU == "cortex-a9-mp") { 3804 Features["vfp3"] = true; 3805 Features["neon"] = true; 3806 } 3807 else if (CPU == "cortex-a5") { 3808 Features["vfp4"] = true; 3809 Features["neon"] = true; 3810 } else if (CPU == "swift" || CPU == "cortex-a7" || CPU == "cortex-a15") { 3811 Features["vfp4"] = true; 3812 Features["neon"] = true; 3813 Features["hwdiv"] = true; 3814 Features["hwdiv-arm"] = true; 3815 } else if (CPU == "cortex-a53" || CPU == "cortex-a57") { 3816 Features["fp-armv8"] = true; 3817 Features["neon"] = true; 3818 Features["hwdiv"] = true; 3819 Features["hwdiv-arm"] = true; 3820 Features["crc"] = true; 3821 } else if (CPU == "cortex-r5" || CPU == "cortex-m3" || 3822 CPU == "cortex-m4" || 3823 // Enable the hwdiv extension for all v8a AArch32 cores by 3824 // default. 3825 ArchName == "armv8a" || ArchName == "armv8" || 3826 ArchName == "thumbv8a" || ArchName == "thumbv8") { 3827 Features["hwdiv"] = true; 3828 Features["hwdiv-arm"] = true; 3829 } 3830 } 3831 3832 virtual bool handleTargetFeatures(std::vector<std::string> &Features, 3833 DiagnosticsEngine &Diags) { 3834 FPU = 0; 3835 CRC = 0; 3836 SoftFloat = SoftFloatABI = false; 3837 HWDiv = 0; 3838 for (unsigned i = 0, e = Features.size(); i != e; ++i) { 3839 if (Features[i] == "+soft-float") 3840 SoftFloat = true; 3841 else if (Features[i] == "+soft-float-abi") 3842 SoftFloatABI = true; 3843 else if (Features[i] == "+vfp2") 3844 FPU |= VFP2FPU; 3845 else if (Features[i] == "+vfp3") 3846 FPU |= VFP3FPU; 3847 else if (Features[i] == "+vfp4") 3848 FPU |= VFP4FPU; 3849 else if (Features[i] == "+fp-armv8") 3850 FPU |= FPARMV8; 3851 else if (Features[i] == "+neon") 3852 FPU |= NeonFPU; 3853 else if (Features[i] == "+hwdiv") 3854 HWDiv |= HWDivThumb; 3855 else if (Features[i] == "+hwdiv-arm") 3856 HWDiv |= HWDivARM; 3857 else if (Features[i] == "+crc") 3858 CRC = 1; 3859 } 3860 3861 if (!(FPU & NeonFPU) && FPMath == FP_Neon) { 3862 Diags.Report(diag::err_target_unsupported_fpmath) << "neon"; 3863 return false; 3864 } 3865 3866 if (FPMath == FP_Neon) 3867 Features.push_back("+neonfp"); 3868 else if (FPMath == FP_VFP) 3869 Features.push_back("-neonfp"); 3870 3871 // Remove front-end specific options which the backend handles differently. 3872 std::vector<std::string>::iterator it; 3873 it = std::find(Features.begin(), Features.end(), "+soft-float"); 3874 if (it != Features.end()) 3875 Features.erase(it); 3876 it = std::find(Features.begin(), Features.end(), "+soft-float-abi"); 3877 if (it != Features.end()) 3878 Features.erase(it); 3879 return true; 3880 } 3881 3882 virtual bool hasFeature(StringRef Feature) const { 3883 return llvm::StringSwitch<bool>(Feature) 3884 .Case("arm", true) 3885 .Case("softfloat", SoftFloat) 3886 .Case("thumb", IsThumb) 3887 .Case("neon", (FPU & NeonFPU) && !SoftFloat) 3888 .Case("hwdiv", HWDiv & HWDivThumb) 3889 .Case("hwdiv-arm", HWDiv & HWDivARM) 3890 .Default(false); 3891 } 3892 // FIXME: Should we actually have some table instead of these switches? 3893 static const char *getCPUDefineSuffix(StringRef Name) { 3894 return llvm::StringSwitch<const char*>(Name) 3895 .Cases("arm8", "arm810", "4") 3896 .Cases("strongarm", "strongarm110", "strongarm1100", "strongarm1110", "4") 3897 .Cases("arm7tdmi", "arm7tdmi-s", "arm710t", "arm720t", "arm9", "4T") 3898 .Cases("arm9tdmi", "arm920", "arm920t", "arm922t", "arm940t", "4T") 3899 .Case("ep9312", "4T") 3900 .Cases("arm10tdmi", "arm1020t", "5T") 3901 .Cases("arm9e", "arm946e-s", "arm966e-s", "arm968e-s", "5TE") 3902 .Case("arm926ej-s", "5TEJ") 3903 .Cases("arm10e", "arm1020e", "arm1022e", "5TE") 3904 .Cases("xscale", "iwmmxt", "5TE") 3905 .Case("arm1136j-s", "6J") 3906 .Cases("arm1176jz-s", "arm1176jzf-s", "6ZK") 3907 .Cases("arm1136jf-s", "mpcorenovfp", "mpcore", "6K") 3908 .Cases("arm1156t2-s", "arm1156t2f-s", "6T2") 3909 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "7A") 3910 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "7A") 3911 .Cases("cortex-r4", "cortex-r5", "7R") 3912 .Case("cortex-a9-mp", "7F") 3913 .Case("swift", "7S") 3914 .Cases("cortex-m3", "cortex-m4", "7M") 3915 .Case("cortex-m0", "6M") 3916 .Cases("cortex-a53", "cortex-a57", "8A") 3917 .Default(0); 3918 } 3919 static const char *getCPUProfile(StringRef Name) { 3920 return llvm::StringSwitch<const char*>(Name) 3921 .Cases("cortex-a5", "cortex-a7", "cortex-a8", "A") 3922 .Cases("cortex-a9", "cortex-a12", "cortex-a15", "A") 3923 .Cases("cortex-a53", "cortex-a57", "A") 3924 .Cases("cortex-m3", "cortex-m4", "cortex-m0", "M") 3925 .Cases("cortex-r4", "cortex-r5", "R") 3926 .Default(""); 3927 } 3928 virtual bool setCPU(const std::string &Name) { 3929 if (!getCPUDefineSuffix(Name)) 3930 return false; 3931 3932 CPU = Name; 3933 return true; 3934 } 3935 virtual bool setFPMath(StringRef Name); 3936 virtual void getTargetDefines(const LangOptions &Opts, 3937 MacroBuilder &Builder) const { 3938 // Target identification. 3939 Builder.defineMacro("__arm"); 3940 Builder.defineMacro("__arm__"); 3941 3942 // Target properties. 3943 Builder.defineMacro("__ARMEL__"); 3944 Builder.defineMacro("__LITTLE_ENDIAN__"); 3945 Builder.defineMacro("__REGISTER_PREFIX__", ""); 3946 3947 StringRef CPUArch = getCPUDefineSuffix(CPU); 3948 unsigned int CPUArchVer; 3949 if(CPUArch.substr(0, 1).getAsInteger<unsigned int>(10, CPUArchVer)) { 3950 llvm_unreachable("Invalid char for architecture version number"); 3951 } 3952 Builder.defineMacro("__ARM_ARCH_" + CPUArch + "__"); 3953 Builder.defineMacro("__ARM_ARCH", CPUArch.substr(0, 1)); 3954 StringRef CPUProfile = getCPUProfile(CPU); 3955 if (!CPUProfile.empty()) 3956 Builder.defineMacro("__ARM_ARCH_PROFILE", CPUProfile); 3957 3958 // Subtarget options. 3959 3960 // FIXME: It's more complicated than this and we don't really support 3961 // interworking. 3962 if (5 <= CPUArchVer && CPUArchVer <= 7) 3963 Builder.defineMacro("__THUMB_INTERWORK__"); 3964 3965 if (ABI == "aapcs" || ABI == "aapcs-linux" || ABI == "aapcs-vfp") { 3966 // Embedded targets on Darwin follow AAPCS, but not EABI. 3967 if (!getTriple().isOSDarwin()) 3968 Builder.defineMacro("__ARM_EABI__"); 3969 Builder.defineMacro("__ARM_PCS", "1"); 3970 3971 if ((!SoftFloat && !SoftFloatABI) || ABI == "aapcs-vfp") 3972 Builder.defineMacro("__ARM_PCS_VFP", "1"); 3973 } 3974 3975 if (SoftFloat) 3976 Builder.defineMacro("__SOFTFP__"); 3977 3978 if (CPU == "xscale") 3979 Builder.defineMacro("__XSCALE__"); 3980 3981 if (IsThumb) { 3982 Builder.defineMacro("__THUMBEL__"); 3983 Builder.defineMacro("__thumb__"); 3984 if (CPUArch == "6T2" || CPUArchVer == 7) 3985 Builder.defineMacro("__thumb2__"); 3986 } 3987 if (((HWDiv & HWDivThumb) && IsThumb) || ((HWDiv & HWDivARM) && !IsThumb)) 3988 Builder.defineMacro("__ARM_ARCH_EXT_IDIV__", "1"); 3989 3990 // Note, this is always on in gcc, even though it doesn't make sense. 3991 Builder.defineMacro("__APCS_32__"); 3992 3993 if (FPUModeIsVFP((FPUMode) FPU)) { 3994 Builder.defineMacro("__VFP_FP__"); 3995 if (FPU & VFP2FPU) 3996 Builder.defineMacro("__ARM_VFPV2__"); 3997 if (FPU & VFP3FPU) 3998 Builder.defineMacro("__ARM_VFPV3__"); 3999 if (FPU & VFP4FPU) 4000 Builder.defineMacro("__ARM_VFPV4__"); 4001 } 4002 4003 // This only gets set when Neon instructions are actually available, unlike 4004 // the VFP define, hence the soft float and arch check. This is subtly 4005 // different from gcc, we follow the intent which was that it should be set 4006 // when Neon instructions are actually available. 4007 if ((FPU & NeonFPU) && !SoftFloat && CPUArchVer >= 7) 4008 Builder.defineMacro("__ARM_NEON__"); 4009 4010 if (CRC) 4011 Builder.defineMacro("__ARM_FEATURE_CRC32"); 4012 4013 if (CPUArchVer >= 6 && CPUArch != "6M") { 4014 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); 4015 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); 4016 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); 4017 Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); 4018 } 4019 } 4020 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4021 unsigned &NumRecords) const { 4022 Records = BuiltinInfo; 4023 NumRecords = clang::ARM::LastTSBuiltin-Builtin::FirstTSBuiltin; 4024 } 4025 virtual bool isCLZForZeroUndef() const { return false; } 4026 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4027 return IsAAPCS ? AAPCSABIBuiltinVaList : TargetInfo::VoidPtrBuiltinVaList; 4028 } 4029 virtual void getGCCRegNames(const char * const *&Names, 4030 unsigned &NumNames) const; 4031 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4032 unsigned &NumAliases) const; 4033 virtual bool validateAsmConstraint(const char *&Name, 4034 TargetInfo::ConstraintInfo &Info) const { 4035 switch (*Name) { 4036 default: break; 4037 case 'l': // r0-r7 4038 case 'h': // r8-r15 4039 case 'w': // VFP Floating point register single precision 4040 case 'P': // VFP Floating point register double precision 4041 Info.setAllowsRegister(); 4042 return true; 4043 case 'Q': // A memory address that is a single base register. 4044 Info.setAllowsMemory(); 4045 return true; 4046 case 'U': // a memory reference... 4047 switch (Name[1]) { 4048 case 'q': // ...ARMV4 ldrsb 4049 case 'v': // ...VFP load/store (reg+constant offset) 4050 case 'y': // ...iWMMXt load/store 4051 case 't': // address valid for load/store opaque types wider 4052 // than 128-bits 4053 case 'n': // valid address for Neon doubleword vector load/store 4054 case 'm': // valid address for Neon element and structure load/store 4055 case 's': // valid address for non-offset loads/stores of quad-word 4056 // values in four ARM registers 4057 Info.setAllowsMemory(); 4058 Name++; 4059 return true; 4060 } 4061 } 4062 return false; 4063 } 4064 virtual std::string convertConstraint(const char *&Constraint) const { 4065 std::string R; 4066 switch (*Constraint) { 4067 case 'U': // Two-character constraint; add "^" hint for later parsing. 4068 R = std::string("^") + std::string(Constraint, 2); 4069 Constraint++; 4070 break; 4071 case 'p': // 'p' should be translated to 'r' by default. 4072 R = std::string("r"); 4073 break; 4074 default: 4075 return std::string(1, *Constraint); 4076 } 4077 return R; 4078 } 4079 virtual bool validateConstraintModifier(StringRef Constraint, 4080 const char Modifier, 4081 unsigned Size) const { 4082 bool isOutput = (Constraint[0] == '='); 4083 bool isInOut = (Constraint[0] == '+'); 4084 4085 // Strip off constraint modifiers. 4086 while (Constraint[0] == '=' || 4087 Constraint[0] == '+' || 4088 Constraint[0] == '&') 4089 Constraint = Constraint.substr(1); 4090 4091 switch (Constraint[0]) { 4092 default: break; 4093 case 'r': { 4094 switch (Modifier) { 4095 default: 4096 return (isInOut || isOutput || Size <= 32); 4097 case 'q': 4098 // A register of size 32 cannot fit a vector type. 4099 return false; 4100 } 4101 } 4102 } 4103 4104 return true; 4105 } 4106 virtual const char *getClobbers() const { 4107 // FIXME: Is this really right? 4108 return ""; 4109 } 4110 4111 virtual CallingConvCheckResult checkCallingConvention(CallingConv CC) const { 4112 return (CC == CC_AAPCS || CC == CC_AAPCS_VFP) ? CCCR_OK : CCCR_Warning; 4113 } 4114 4115 virtual int getEHDataRegisterNumber(unsigned RegNo) const { 4116 if (RegNo == 0) return 0; 4117 if (RegNo == 1) return 1; 4118 return -1; 4119 } 4120 }; 4121 4122 bool ARMTargetInfo::setFPMath(StringRef Name) { 4123 if (Name == "neon") { 4124 FPMath = FP_Neon; 4125 return true; 4126 } else if (Name == "vfp" || Name == "vfp2" || Name == "vfp3" || 4127 Name == "vfp4") { 4128 FPMath = FP_VFP; 4129 return true; 4130 } 4131 return false; 4132 } 4133 4134 const char * const ARMTargetInfo::GCCRegNames[] = { 4135 // Integer registers 4136 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4137 "r8", "r9", "r10", "r11", "r12", "sp", "lr", "pc", 4138 4139 // Float registers 4140 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", 4141 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15", 4142 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23", 4143 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31", 4144 4145 // Double registers 4146 "d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", 4147 "d8", "d9", "d10", "d11", "d12", "d13", "d14", "d15", 4148 "d16", "d17", "d18", "d19", "d20", "d21", "d22", "d23", 4149 "d24", "d25", "d26", "d27", "d28", "d29", "d30", "d31", 4150 4151 // Quad registers 4152 "q0", "q1", "q2", "q3", "q4", "q5", "q6", "q7", 4153 "q8", "q9", "q10", "q11", "q12", "q13", "q14", "q15" 4154 }; 4155 4156 void ARMTargetInfo::getGCCRegNames(const char * const *&Names, 4157 unsigned &NumNames) const { 4158 Names = GCCRegNames; 4159 NumNames = llvm::array_lengthof(GCCRegNames); 4160 } 4161 4162 const TargetInfo::GCCRegAlias ARMTargetInfo::GCCRegAliases[] = { 4163 { { "a1" }, "r0" }, 4164 { { "a2" }, "r1" }, 4165 { { "a3" }, "r2" }, 4166 { { "a4" }, "r3" }, 4167 { { "v1" }, "r4" }, 4168 { { "v2" }, "r5" }, 4169 { { "v3" }, "r6" }, 4170 { { "v4" }, "r7" }, 4171 { { "v5" }, "r8" }, 4172 { { "v6", "rfp" }, "r9" }, 4173 { { "sl" }, "r10" }, 4174 { { "fp" }, "r11" }, 4175 { { "ip" }, "r12" }, 4176 { { "r13" }, "sp" }, 4177 { { "r14" }, "lr" }, 4178 { { "r15" }, "pc" }, 4179 // The S, D and Q registers overlap, but aren't really aliases; we 4180 // don't want to substitute one of these for a different-sized one. 4181 }; 4182 4183 void ARMTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4184 unsigned &NumAliases) const { 4185 Aliases = GCCRegAliases; 4186 NumAliases = llvm::array_lengthof(GCCRegAliases); 4187 } 4188 4189 const Builtin::Info ARMTargetInfo::BuiltinInfo[] = { 4190 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4191 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4192 ALL_LANGUAGES }, 4193 #include "clang/Basic/BuiltinsARM.def" 4194 }; 4195 } // end anonymous namespace. 4196 4197 namespace { 4198 class DarwinARMTargetInfo : 4199 public DarwinTargetInfo<ARMTargetInfo> { 4200 protected: 4201 virtual void getOSDefines(const LangOptions &Opts, const llvm::Triple &Triple, 4202 MacroBuilder &Builder) const { 4203 getDarwinDefines(Builder, Opts, Triple, PlatformName, PlatformMinVersion); 4204 } 4205 4206 public: 4207 DarwinARMTargetInfo(const llvm::Triple &Triple) 4208 : DarwinTargetInfo<ARMTargetInfo>(Triple) { 4209 HasAlignMac68kSupport = true; 4210 // iOS always has 64-bit atomic instructions. 4211 // FIXME: This should be based off of the target features in ARMTargetInfo. 4212 MaxAtomicInlineWidth = 64; 4213 4214 // Darwin on iOS uses a variant of the ARM C++ ABI. 4215 TheCXXABI.set(TargetCXXABI::iOS); 4216 } 4217 }; 4218 } // end anonymous namespace. 4219 4220 4221 namespace { 4222 // Hexagon abstract base class 4223 class HexagonTargetInfo : public TargetInfo { 4224 static const Builtin::Info BuiltinInfo[]; 4225 static const char * const GCCRegNames[]; 4226 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4227 std::string CPU; 4228 public: 4229 HexagonTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4230 BigEndian = false; 4231 DescriptionString = ("e-p:32:32:32-" 4232 "i64:64:64-i32:32:32-i16:16:16-i1:32:32-" 4233 "f64:64:64-f32:32:32-a0:0-n32"); 4234 4235 // {} in inline assembly are packet specifiers, not assembly variant 4236 // specifiers. 4237 NoAsmVariants = true; 4238 } 4239 4240 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4241 unsigned &NumRecords) const { 4242 Records = BuiltinInfo; 4243 NumRecords = clang::Hexagon::LastTSBuiltin-Builtin::FirstTSBuiltin; 4244 } 4245 4246 virtual bool validateAsmConstraint(const char *&Name, 4247 TargetInfo::ConstraintInfo &Info) const { 4248 return true; 4249 } 4250 4251 virtual void getTargetDefines(const LangOptions &Opts, 4252 MacroBuilder &Builder) const; 4253 4254 virtual bool hasFeature(StringRef Feature) const { 4255 return Feature == "hexagon"; 4256 } 4257 4258 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4259 return TargetInfo::CharPtrBuiltinVaList; 4260 } 4261 virtual void getGCCRegNames(const char * const *&Names, 4262 unsigned &NumNames) const; 4263 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4264 unsigned &NumAliases) const; 4265 virtual const char *getClobbers() const { 4266 return ""; 4267 } 4268 4269 static const char *getHexagonCPUSuffix(StringRef Name) { 4270 return llvm::StringSwitch<const char*>(Name) 4271 .Case("hexagonv4", "4") 4272 .Case("hexagonv5", "5") 4273 .Default(0); 4274 } 4275 4276 virtual bool setCPU(const std::string &Name) { 4277 if (!getHexagonCPUSuffix(Name)) 4278 return false; 4279 4280 CPU = Name; 4281 return true; 4282 } 4283 }; 4284 4285 void HexagonTargetInfo::getTargetDefines(const LangOptions &Opts, 4286 MacroBuilder &Builder) const { 4287 Builder.defineMacro("qdsp6"); 4288 Builder.defineMacro("__qdsp6", "1"); 4289 Builder.defineMacro("__qdsp6__", "1"); 4290 4291 Builder.defineMacro("hexagon"); 4292 Builder.defineMacro("__hexagon", "1"); 4293 Builder.defineMacro("__hexagon__", "1"); 4294 4295 if(CPU == "hexagonv1") { 4296 Builder.defineMacro("__HEXAGON_V1__"); 4297 Builder.defineMacro("__HEXAGON_ARCH__", "1"); 4298 if(Opts.HexagonQdsp6Compat) { 4299 Builder.defineMacro("__QDSP6_V1__"); 4300 Builder.defineMacro("__QDSP6_ARCH__", "1"); 4301 } 4302 } 4303 else if(CPU == "hexagonv2") { 4304 Builder.defineMacro("__HEXAGON_V2__"); 4305 Builder.defineMacro("__HEXAGON_ARCH__", "2"); 4306 if(Opts.HexagonQdsp6Compat) { 4307 Builder.defineMacro("__QDSP6_V2__"); 4308 Builder.defineMacro("__QDSP6_ARCH__", "2"); 4309 } 4310 } 4311 else if(CPU == "hexagonv3") { 4312 Builder.defineMacro("__HEXAGON_V3__"); 4313 Builder.defineMacro("__HEXAGON_ARCH__", "3"); 4314 if(Opts.HexagonQdsp6Compat) { 4315 Builder.defineMacro("__QDSP6_V3__"); 4316 Builder.defineMacro("__QDSP6_ARCH__", "3"); 4317 } 4318 } 4319 else if(CPU == "hexagonv4") { 4320 Builder.defineMacro("__HEXAGON_V4__"); 4321 Builder.defineMacro("__HEXAGON_ARCH__", "4"); 4322 if(Opts.HexagonQdsp6Compat) { 4323 Builder.defineMacro("__QDSP6_V4__"); 4324 Builder.defineMacro("__QDSP6_ARCH__", "4"); 4325 } 4326 } 4327 else if(CPU == "hexagonv5") { 4328 Builder.defineMacro("__HEXAGON_V5__"); 4329 Builder.defineMacro("__HEXAGON_ARCH__", "5"); 4330 if(Opts.HexagonQdsp6Compat) { 4331 Builder.defineMacro("__QDSP6_V5__"); 4332 Builder.defineMacro("__QDSP6_ARCH__", "5"); 4333 } 4334 } 4335 } 4336 4337 const char * const HexagonTargetInfo::GCCRegNames[] = { 4338 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4339 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4340 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 4341 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", 4342 "p0", "p1", "p2", "p3", 4343 "sa0", "lc0", "sa1", "lc1", "m0", "m1", "usr", "ugp" 4344 }; 4345 4346 void HexagonTargetInfo::getGCCRegNames(const char * const *&Names, 4347 unsigned &NumNames) const { 4348 Names = GCCRegNames; 4349 NumNames = llvm::array_lengthof(GCCRegNames); 4350 } 4351 4352 4353 const TargetInfo::GCCRegAlias HexagonTargetInfo::GCCRegAliases[] = { 4354 { { "sp" }, "r29" }, 4355 { { "fp" }, "r30" }, 4356 { { "lr" }, "r31" }, 4357 }; 4358 4359 void HexagonTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4360 unsigned &NumAliases) const { 4361 Aliases = GCCRegAliases; 4362 NumAliases = llvm::array_lengthof(GCCRegAliases); 4363 } 4364 4365 4366 const Builtin::Info HexagonTargetInfo::BuiltinInfo[] = { 4367 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 4368 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 4369 ALL_LANGUAGES }, 4370 #include "clang/Basic/BuiltinsHexagon.def" 4371 }; 4372 } 4373 4374 4375 namespace { 4376 // Shared base class for SPARC v8 (32-bit) and SPARC v9 (64-bit). 4377 class SparcTargetInfo : public TargetInfo { 4378 static const TargetInfo::GCCRegAlias GCCRegAliases[]; 4379 static const char * const GCCRegNames[]; 4380 bool SoftFloat; 4381 public: 4382 SparcTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) {} 4383 4384 virtual bool handleTargetFeatures(std::vector<std::string> &Features, 4385 DiagnosticsEngine &Diags) { 4386 SoftFloat = false; 4387 for (unsigned i = 0, e = Features.size(); i != e; ++i) 4388 if (Features[i] == "+soft-float") 4389 SoftFloat = true; 4390 return true; 4391 } 4392 virtual void getTargetDefines(const LangOptions &Opts, 4393 MacroBuilder &Builder) const { 4394 DefineStd(Builder, "sparc", Opts); 4395 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4396 4397 if (SoftFloat) 4398 Builder.defineMacro("SOFT_FLOAT", "1"); 4399 } 4400 4401 virtual bool hasFeature(StringRef Feature) const { 4402 return llvm::StringSwitch<bool>(Feature) 4403 .Case("softfloat", SoftFloat) 4404 .Case("sparc", true) 4405 .Default(false); 4406 } 4407 4408 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4409 unsigned &NumRecords) const { 4410 // FIXME: Implement! 4411 } 4412 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4413 return TargetInfo::VoidPtrBuiltinVaList; 4414 } 4415 virtual void getGCCRegNames(const char * const *&Names, 4416 unsigned &NumNames) const; 4417 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4418 unsigned &NumAliases) const; 4419 virtual bool validateAsmConstraint(const char *&Name, 4420 TargetInfo::ConstraintInfo &info) const { 4421 // FIXME: Implement! 4422 return false; 4423 } 4424 virtual const char *getClobbers() const { 4425 // FIXME: Implement! 4426 return ""; 4427 } 4428 }; 4429 4430 const char * const SparcTargetInfo::GCCRegNames[] = { 4431 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4432 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4433 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", 4434 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31" 4435 }; 4436 4437 void SparcTargetInfo::getGCCRegNames(const char * const *&Names, 4438 unsigned &NumNames) const { 4439 Names = GCCRegNames; 4440 NumNames = llvm::array_lengthof(GCCRegNames); 4441 } 4442 4443 const TargetInfo::GCCRegAlias SparcTargetInfo::GCCRegAliases[] = { 4444 { { "g0" }, "r0" }, 4445 { { "g1" }, "r1" }, 4446 { { "g2" }, "r2" }, 4447 { { "g3" }, "r3" }, 4448 { { "g4" }, "r4" }, 4449 { { "g5" }, "r5" }, 4450 { { "g6" }, "r6" }, 4451 { { "g7" }, "r7" }, 4452 { { "o0" }, "r8" }, 4453 { { "o1" }, "r9" }, 4454 { { "o2" }, "r10" }, 4455 { { "o3" }, "r11" }, 4456 { { "o4" }, "r12" }, 4457 { { "o5" }, "r13" }, 4458 { { "o6", "sp" }, "r14" }, 4459 { { "o7" }, "r15" }, 4460 { { "l0" }, "r16" }, 4461 { { "l1" }, "r17" }, 4462 { { "l2" }, "r18" }, 4463 { { "l3" }, "r19" }, 4464 { { "l4" }, "r20" }, 4465 { { "l5" }, "r21" }, 4466 { { "l6" }, "r22" }, 4467 { { "l7" }, "r23" }, 4468 { { "i0" }, "r24" }, 4469 { { "i1" }, "r25" }, 4470 { { "i2" }, "r26" }, 4471 { { "i3" }, "r27" }, 4472 { { "i4" }, "r28" }, 4473 { { "i5" }, "r29" }, 4474 { { "i6", "fp" }, "r30" }, 4475 { { "i7" }, "r31" }, 4476 }; 4477 4478 void SparcTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 4479 unsigned &NumAliases) const { 4480 Aliases = GCCRegAliases; 4481 NumAliases = llvm::array_lengthof(GCCRegAliases); 4482 } 4483 4484 // SPARC v8 is the 32-bit mode selected by Triple::sparc. 4485 class SparcV8TargetInfo : public SparcTargetInfo { 4486 public: 4487 SparcV8TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 4488 // FIXME: Support Sparc quad-precision long double? 4489 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 4490 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64"; 4491 } 4492 4493 virtual void getTargetDefines(const LangOptions &Opts, 4494 MacroBuilder &Builder) const { 4495 SparcTargetInfo::getTargetDefines(Opts, Builder); 4496 Builder.defineMacro("__sparcv8"); 4497 } 4498 }; 4499 4500 // SPARC v9 is the 64-bit mode selected by Triple::sparcv9. 4501 class SparcV9TargetInfo : public SparcTargetInfo { 4502 public: 4503 SparcV9TargetInfo(const llvm::Triple &Triple) : SparcTargetInfo(Triple) { 4504 // FIXME: Support Sparc quad-precision long double? 4505 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-" 4506 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32:64-S128"; 4507 // This is an LP64 platform. 4508 LongWidth = LongAlign = PointerWidth = PointerAlign = 64; 4509 4510 // OpenBSD uses long long for int64_t and intmax_t. 4511 if (getTriple().getOS() == llvm::Triple::OpenBSD) { 4512 IntMaxType = SignedLongLong; 4513 UIntMaxType = UnsignedLongLong; 4514 } else { 4515 IntMaxType = SignedLong; 4516 UIntMaxType = UnsignedLong; 4517 } 4518 Int64Type = IntMaxType; 4519 } 4520 4521 virtual void getTargetDefines(const LangOptions &Opts, 4522 MacroBuilder &Builder) const { 4523 SparcTargetInfo::getTargetDefines(Opts, Builder); 4524 Builder.defineMacro("__sparcv9"); 4525 Builder.defineMacro("__arch64__"); 4526 // Solaris and its derivative AuroraUX don't need these variants, but the 4527 // BSDs do. 4528 if (getTriple().getOS() != llvm::Triple::Solaris && 4529 getTriple().getOS() != llvm::Triple::AuroraUX) { 4530 Builder.defineMacro("__sparc64__"); 4531 Builder.defineMacro("__sparc_v9__"); 4532 Builder.defineMacro("__sparcv9__"); 4533 } 4534 } 4535 }; 4536 4537 } // end anonymous namespace. 4538 4539 namespace { 4540 class AuroraUXSparcV8TargetInfo : public AuroraUXTargetInfo<SparcV8TargetInfo> { 4541 public: 4542 AuroraUXSparcV8TargetInfo(const llvm::Triple &Triple) 4543 : AuroraUXTargetInfo<SparcV8TargetInfo>(Triple) { 4544 SizeType = UnsignedInt; 4545 PtrDiffType = SignedInt; 4546 } 4547 }; 4548 class SolarisSparcV8TargetInfo : public SolarisTargetInfo<SparcV8TargetInfo> { 4549 public: 4550 SolarisSparcV8TargetInfo(const llvm::Triple &Triple) 4551 : SolarisTargetInfo<SparcV8TargetInfo>(Triple) { 4552 SizeType = UnsignedInt; 4553 PtrDiffType = SignedInt; 4554 } 4555 }; 4556 } // end anonymous namespace. 4557 4558 namespace { 4559 class SystemZTargetInfo : public TargetInfo { 4560 static const char *const GCCRegNames[]; 4561 4562 public: 4563 SystemZTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4564 TLSSupported = true; 4565 IntWidth = IntAlign = 32; 4566 LongWidth = LongLongWidth = LongAlign = LongLongAlign = 64; 4567 PointerWidth = PointerAlign = 64; 4568 LongDoubleWidth = 128; 4569 LongDoubleAlign = 64; 4570 LongDoubleFormat = &llvm::APFloat::IEEEquad; 4571 MinGlobalAlign = 16; 4572 DescriptionString = "E-p:64:64:64-i1:8:16-i8:8:16-i16:16-i32:32-i64:64" 4573 "-f32:32-f64:64-f128:64-a0:8:16-n32:64"; 4574 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 4575 } 4576 virtual void getTargetDefines(const LangOptions &Opts, 4577 MacroBuilder &Builder) const { 4578 Builder.defineMacro("__s390__"); 4579 Builder.defineMacro("__s390x__"); 4580 Builder.defineMacro("__zarch__"); 4581 Builder.defineMacro("__LONG_DOUBLE_128__"); 4582 } 4583 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4584 unsigned &NumRecords) const { 4585 // FIXME: Implement. 4586 Records = 0; 4587 NumRecords = 0; 4588 } 4589 4590 virtual void getGCCRegNames(const char *const *&Names, 4591 unsigned &NumNames) const; 4592 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4593 unsigned &NumAliases) const { 4594 // No aliases. 4595 Aliases = 0; 4596 NumAliases = 0; 4597 } 4598 virtual bool validateAsmConstraint(const char *&Name, 4599 TargetInfo::ConstraintInfo &info) const; 4600 virtual const char *getClobbers() const { 4601 // FIXME: Is this really right? 4602 return ""; 4603 } 4604 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4605 return TargetInfo::SystemZBuiltinVaList; 4606 } 4607 virtual bool setCPU(const std::string &Name) { 4608 bool CPUKnown = llvm::StringSwitch<bool>(Name) 4609 .Case("z10", true) 4610 .Case("z196", true) 4611 .Case("zEC12", true) 4612 .Default(false); 4613 4614 // No need to store the CPU yet. There aren't any CPU-specific 4615 // macros to define. 4616 return CPUKnown; 4617 } 4618 }; 4619 4620 const char *const SystemZTargetInfo::GCCRegNames[] = { 4621 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4622 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 4623 "f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7", 4624 "f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15" 4625 }; 4626 4627 void SystemZTargetInfo::getGCCRegNames(const char *const *&Names, 4628 unsigned &NumNames) const { 4629 Names = GCCRegNames; 4630 NumNames = llvm::array_lengthof(GCCRegNames); 4631 } 4632 4633 bool SystemZTargetInfo:: 4634 validateAsmConstraint(const char *&Name, 4635 TargetInfo::ConstraintInfo &Info) const { 4636 switch (*Name) { 4637 default: 4638 return false; 4639 4640 case 'a': // Address register 4641 case 'd': // Data register (equivalent to 'r') 4642 case 'f': // Floating-point register 4643 Info.setAllowsRegister(); 4644 return true; 4645 4646 case 'I': // Unsigned 8-bit constant 4647 case 'J': // Unsigned 12-bit constant 4648 case 'K': // Signed 16-bit constant 4649 case 'L': // Signed 20-bit displacement (on all targets we support) 4650 case 'M': // 0x7fffffff 4651 return true; 4652 4653 case 'Q': // Memory with base and unsigned 12-bit displacement 4654 case 'R': // Likewise, plus an index 4655 case 'S': // Memory with base and signed 20-bit displacement 4656 case 'T': // Likewise, plus an index 4657 Info.setAllowsMemory(); 4658 return true; 4659 } 4660 } 4661 } 4662 4663 namespace { 4664 class MSP430TargetInfo : public TargetInfo { 4665 static const char * const GCCRegNames[]; 4666 public: 4667 MSP430TargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4668 BigEndian = false; 4669 TLSSupported = false; 4670 IntWidth = 16; IntAlign = 16; 4671 LongWidth = 32; LongLongWidth = 64; 4672 LongAlign = LongLongAlign = 16; 4673 PointerWidth = 16; PointerAlign = 16; 4674 SuitableAlign = 16; 4675 SizeType = UnsignedInt; 4676 IntMaxType = SignedLongLong; 4677 UIntMaxType = UnsignedLongLong; 4678 IntPtrType = SignedInt; 4679 PtrDiffType = SignedInt; 4680 SigAtomicType = SignedLong; 4681 DescriptionString = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"; 4682 } 4683 virtual void getTargetDefines(const LangOptions &Opts, 4684 MacroBuilder &Builder) const { 4685 Builder.defineMacro("MSP430"); 4686 Builder.defineMacro("__MSP430__"); 4687 // FIXME: defines for different 'flavours' of MCU 4688 } 4689 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4690 unsigned &NumRecords) const { 4691 // FIXME: Implement. 4692 Records = 0; 4693 NumRecords = 0; 4694 } 4695 virtual bool hasFeature(StringRef Feature) const { 4696 return Feature == "msp430"; 4697 } 4698 virtual void getGCCRegNames(const char * const *&Names, 4699 unsigned &NumNames) const; 4700 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4701 unsigned &NumAliases) const { 4702 // No aliases. 4703 Aliases = 0; 4704 NumAliases = 0; 4705 } 4706 virtual bool validateAsmConstraint(const char *&Name, 4707 TargetInfo::ConstraintInfo &info) const { 4708 // No target constraints for now. 4709 return false; 4710 } 4711 virtual const char *getClobbers() const { 4712 // FIXME: Is this really right? 4713 return ""; 4714 } 4715 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4716 // FIXME: implement 4717 return TargetInfo::CharPtrBuiltinVaList; 4718 } 4719 }; 4720 4721 const char * const MSP430TargetInfo::GCCRegNames[] = { 4722 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 4723 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" 4724 }; 4725 4726 void MSP430TargetInfo::getGCCRegNames(const char * const *&Names, 4727 unsigned &NumNames) const { 4728 Names = GCCRegNames; 4729 NumNames = llvm::array_lengthof(GCCRegNames); 4730 } 4731 } 4732 4733 namespace { 4734 4735 // LLVM and Clang cannot be used directly to output native binaries for 4736 // target, but is used to compile C code to llvm bitcode with correct 4737 // type and alignment information. 4738 // 4739 // TCE uses the llvm bitcode as input and uses it for generating customized 4740 // target processor and program binary. TCE co-design environment is 4741 // publicly available in http://tce.cs.tut.fi 4742 4743 static const unsigned TCEOpenCLAddrSpaceMap[] = { 4744 3, // opencl_global 4745 4, // opencl_local 4746 5, // opencl_constant 4747 0, // cuda_device 4748 0, // cuda_constant 4749 0 // cuda_shared 4750 }; 4751 4752 class TCETargetInfo : public TargetInfo{ 4753 public: 4754 TCETargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 4755 TLSSupported = false; 4756 IntWidth = 32; 4757 LongWidth = LongLongWidth = 32; 4758 PointerWidth = 32; 4759 IntAlign = 32; 4760 LongAlign = LongLongAlign = 32; 4761 PointerAlign = 32; 4762 SuitableAlign = 32; 4763 SizeType = UnsignedInt; 4764 IntMaxType = SignedLong; 4765 UIntMaxType = UnsignedLong; 4766 IntPtrType = SignedInt; 4767 PtrDiffType = SignedInt; 4768 FloatWidth = 32; 4769 FloatAlign = 32; 4770 DoubleWidth = 32; 4771 DoubleAlign = 32; 4772 LongDoubleWidth = 32; 4773 LongDoubleAlign = 32; 4774 FloatFormat = &llvm::APFloat::IEEEsingle; 4775 DoubleFormat = &llvm::APFloat::IEEEsingle; 4776 LongDoubleFormat = &llvm::APFloat::IEEEsingle; 4777 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-" 4778 "i16:16:32-i32:32:32-i64:32:32-" 4779 "f32:32:32-f64:32:32-v64:32:32-" 4780 "v128:32:32-a0:0:32-n32"; 4781 AddrSpaceMap = &TCEOpenCLAddrSpaceMap; 4782 UseAddrSpaceMapMangling = true; 4783 } 4784 4785 virtual void getTargetDefines(const LangOptions &Opts, 4786 MacroBuilder &Builder) const { 4787 DefineStd(Builder, "tce", Opts); 4788 Builder.defineMacro("__TCE__"); 4789 Builder.defineMacro("__TCE_V1__"); 4790 } 4791 virtual bool hasFeature(StringRef Feature) const { 4792 return Feature == "tce"; 4793 } 4794 4795 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4796 unsigned &NumRecords) const {} 4797 virtual const char *getClobbers() const { 4798 return ""; 4799 } 4800 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4801 return TargetInfo::VoidPtrBuiltinVaList; 4802 } 4803 virtual void getGCCRegNames(const char * const *&Names, 4804 unsigned &NumNames) const {} 4805 virtual bool validateAsmConstraint(const char *&Name, 4806 TargetInfo::ConstraintInfo &info) const { 4807 return true; 4808 } 4809 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4810 unsigned &NumAliases) const {} 4811 }; 4812 } 4813 4814 namespace { 4815 class MipsTargetInfoBase : public TargetInfo { 4816 virtual void setDescriptionString() = 0; 4817 4818 static const Builtin::Info BuiltinInfo[]; 4819 std::string CPU; 4820 bool IsMips16; 4821 bool IsMicromips; 4822 bool IsNan2008; 4823 bool IsSingleFloat; 4824 enum MipsFloatABI { 4825 HardFloat, SoftFloat 4826 } FloatABI; 4827 enum DspRevEnum { 4828 NoDSP, DSP1, DSP2 4829 } DspRev; 4830 bool HasMSA; 4831 4832 protected: 4833 bool HasFP64; 4834 std::string ABI; 4835 4836 public: 4837 MipsTargetInfoBase(const llvm::Triple &Triple, const std::string &ABIStr, 4838 const std::string &CPUStr) 4839 : TargetInfo(Triple), CPU(CPUStr), IsMips16(false), IsMicromips(false), 4840 IsNan2008(false), IsSingleFloat(false), FloatABI(HardFloat), 4841 DspRev(NoDSP), HasMSA(false), HasFP64(false), ABI(ABIStr) {} 4842 4843 virtual const char *getABI() const { return ABI.c_str(); } 4844 virtual bool setABI(const std::string &Name) = 0; 4845 virtual bool setCPU(const std::string &Name) { 4846 CPU = Name; 4847 return true; 4848 } 4849 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 4850 Features[ABI] = true; 4851 Features[CPU] = true; 4852 } 4853 4854 virtual void getTargetDefines(const LangOptions &Opts, 4855 MacroBuilder &Builder) const { 4856 DefineStd(Builder, "mips", Opts); 4857 Builder.defineMacro("_mips"); 4858 Builder.defineMacro("__REGISTER_PREFIX__", ""); 4859 4860 switch (FloatABI) { 4861 case HardFloat: 4862 Builder.defineMacro("__mips_hard_float", Twine(1)); 4863 break; 4864 case SoftFloat: 4865 Builder.defineMacro("__mips_soft_float", Twine(1)); 4866 break; 4867 } 4868 4869 if (IsSingleFloat) 4870 Builder.defineMacro("__mips_single_float", Twine(1)); 4871 4872 Builder.defineMacro("__mips_fpr", HasFP64 ? Twine(64) : Twine(32)); 4873 Builder.defineMacro("_MIPS_FPSET", 4874 Twine(32 / (HasFP64 || IsSingleFloat ? 1 : 2))); 4875 4876 if (IsMips16) 4877 Builder.defineMacro("__mips16", Twine(1)); 4878 4879 if (IsMicromips) 4880 Builder.defineMacro("__mips_micromips", Twine(1)); 4881 4882 if (IsNan2008) 4883 Builder.defineMacro("__mips_nan2008", Twine(1)); 4884 4885 switch (DspRev) { 4886 default: 4887 break; 4888 case DSP1: 4889 Builder.defineMacro("__mips_dsp_rev", Twine(1)); 4890 Builder.defineMacro("__mips_dsp", Twine(1)); 4891 break; 4892 case DSP2: 4893 Builder.defineMacro("__mips_dsp_rev", Twine(2)); 4894 Builder.defineMacro("__mips_dspr2", Twine(1)); 4895 Builder.defineMacro("__mips_dsp", Twine(1)); 4896 break; 4897 } 4898 4899 if (HasMSA) 4900 Builder.defineMacro("__mips_msa", Twine(1)); 4901 4902 Builder.defineMacro("_MIPS_SZPTR", Twine(getPointerWidth(0))); 4903 Builder.defineMacro("_MIPS_SZINT", Twine(getIntWidth())); 4904 Builder.defineMacro("_MIPS_SZLONG", Twine(getLongWidth())); 4905 4906 Builder.defineMacro("_MIPS_ARCH", "\"" + CPU + "\""); 4907 Builder.defineMacro("_MIPS_ARCH_" + StringRef(CPU).upper()); 4908 } 4909 4910 virtual void getTargetBuiltins(const Builtin::Info *&Records, 4911 unsigned &NumRecords) const { 4912 Records = BuiltinInfo; 4913 NumRecords = clang::Mips::LastTSBuiltin - Builtin::FirstTSBuiltin; 4914 } 4915 virtual bool hasFeature(StringRef Feature) const { 4916 return llvm::StringSwitch<bool>(Feature) 4917 .Case("mips", true) 4918 .Case("fp64", HasFP64) 4919 .Default(false); 4920 } 4921 virtual BuiltinVaListKind getBuiltinVaListKind() const { 4922 return TargetInfo::VoidPtrBuiltinVaList; 4923 } 4924 virtual void getGCCRegNames(const char * const *&Names, 4925 unsigned &NumNames) const { 4926 static const char *const GCCRegNames[] = { 4927 // CPU register names 4928 // Must match second column of GCCRegAliases 4929 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", 4930 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", 4931 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", 4932 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31", 4933 // Floating point register names 4934 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", 4935 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", 4936 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", 4937 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31", 4938 // Hi/lo and condition register names 4939 "hi", "lo", "", "$fcc0","$fcc1","$fcc2","$fcc3","$fcc4", 4940 "$fcc5","$fcc6","$fcc7", 4941 // MSA register names 4942 "$w0", "$w1", "$w2", "$w3", "$w4", "$w5", "$w6", "$w7", 4943 "$w8", "$w9", "$w10", "$w11", "$w12", "$w13", "$w14", "$w15", 4944 "$w16", "$w17", "$w18", "$w19", "$w20", "$w21", "$w22", "$w23", 4945 "$w24", "$w25", "$w26", "$w27", "$w28", "$w29", "$w30", "$w31", 4946 // MSA control register names 4947 "$msair", "$msacsr", "$msaaccess", "$msasave", "$msamodify", 4948 "$msarequest", "$msamap", "$msaunmap" 4949 }; 4950 Names = GCCRegNames; 4951 NumNames = llvm::array_lengthof(GCCRegNames); 4952 } 4953 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 4954 unsigned &NumAliases) const = 0; 4955 virtual bool validateAsmConstraint(const char *&Name, 4956 TargetInfo::ConstraintInfo &Info) const { 4957 switch (*Name) { 4958 default: 4959 return false; 4960 4961 case 'r': // CPU registers. 4962 case 'd': // Equivalent to "r" unless generating MIPS16 code. 4963 case 'y': // Equivalent to "r", backwards compatibility only. 4964 case 'f': // floating-point registers. 4965 case 'c': // $25 for indirect jumps 4966 case 'l': // lo register 4967 case 'x': // hilo register pair 4968 Info.setAllowsRegister(); 4969 return true; 4970 case 'R': // An address that can be used in a non-macro load or store 4971 Info.setAllowsMemory(); 4972 return true; 4973 } 4974 } 4975 4976 virtual const char *getClobbers() const { 4977 // FIXME: Implement! 4978 return ""; 4979 } 4980 4981 virtual bool handleTargetFeatures(std::vector<std::string> &Features, 4982 DiagnosticsEngine &Diags) { 4983 IsMips16 = false; 4984 IsMicromips = false; 4985 IsNan2008 = false; 4986 IsSingleFloat = false; 4987 FloatABI = HardFloat; 4988 DspRev = NoDSP; 4989 HasFP64 = ABI == "n32" || ABI == "n64" || ABI == "64"; 4990 4991 for (std::vector<std::string>::iterator it = Features.begin(), 4992 ie = Features.end(); it != ie; ++it) { 4993 if (*it == "+single-float") 4994 IsSingleFloat = true; 4995 else if (*it == "+soft-float") 4996 FloatABI = SoftFloat; 4997 else if (*it == "+mips16") 4998 IsMips16 = true; 4999 else if (*it == "+micromips") 5000 IsMicromips = true; 5001 else if (*it == "+dsp") 5002 DspRev = std::max(DspRev, DSP1); 5003 else if (*it == "+dspr2") 5004 DspRev = std::max(DspRev, DSP2); 5005 else if (*it == "+msa") 5006 HasMSA = true; 5007 else if (*it == "+fp64") 5008 HasFP64 = true; 5009 else if (*it == "-fp64") 5010 HasFP64 = false; 5011 else if (*it == "+nan2008") 5012 IsNan2008 = true; 5013 } 5014 5015 // Remove front-end specific options. 5016 std::vector<std::string>::iterator it = 5017 std::find(Features.begin(), Features.end(), "+soft-float"); 5018 if (it != Features.end()) 5019 Features.erase(it); 5020 it = std::find(Features.begin(), Features.end(), "+nan2008"); 5021 if (it != Features.end()) 5022 Features.erase(it); 5023 5024 setDescriptionString(); 5025 5026 return true; 5027 } 5028 5029 virtual int getEHDataRegisterNumber(unsigned RegNo) const { 5030 if (RegNo == 0) return 4; 5031 if (RegNo == 1) return 5; 5032 return -1; 5033 } 5034 }; 5035 5036 const Builtin::Info MipsTargetInfoBase::BuiltinInfo[] = { 5037 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5038 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5039 ALL_LANGUAGES }, 5040 #include "clang/Basic/BuiltinsMips.def" 5041 }; 5042 5043 class Mips32TargetInfoBase : public MipsTargetInfoBase { 5044 public: 5045 Mips32TargetInfoBase(const llvm::Triple &Triple) 5046 : MipsTargetInfoBase(Triple, "o32", "mips32") { 5047 SizeType = UnsignedInt; 5048 PtrDiffType = SignedInt; 5049 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 32; 5050 } 5051 virtual bool setABI(const std::string &Name) { 5052 if ((Name == "o32") || (Name == "eabi")) { 5053 ABI = Name; 5054 return true; 5055 } else if (Name == "32") { 5056 ABI = "o32"; 5057 return true; 5058 } else 5059 return false; 5060 } 5061 virtual void getTargetDefines(const LangOptions &Opts, 5062 MacroBuilder &Builder) const { 5063 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 5064 5065 if (ABI == "o32") { 5066 Builder.defineMacro("__mips_o32"); 5067 Builder.defineMacro("_ABIO32", "1"); 5068 Builder.defineMacro("_MIPS_SIM", "_ABIO32"); 5069 } 5070 else if (ABI == "eabi") 5071 Builder.defineMacro("__mips_eabi"); 5072 else 5073 llvm_unreachable("Invalid ABI for Mips32."); 5074 } 5075 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5076 unsigned &NumAliases) const { 5077 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 5078 { { "at" }, "$1" }, 5079 { { "v0" }, "$2" }, 5080 { { "v1" }, "$3" }, 5081 { { "a0" }, "$4" }, 5082 { { "a1" }, "$5" }, 5083 { { "a2" }, "$6" }, 5084 { { "a3" }, "$7" }, 5085 { { "t0" }, "$8" }, 5086 { { "t1" }, "$9" }, 5087 { { "t2" }, "$10" }, 5088 { { "t3" }, "$11" }, 5089 { { "t4" }, "$12" }, 5090 { { "t5" }, "$13" }, 5091 { { "t6" }, "$14" }, 5092 { { "t7" }, "$15" }, 5093 { { "s0" }, "$16" }, 5094 { { "s1" }, "$17" }, 5095 { { "s2" }, "$18" }, 5096 { { "s3" }, "$19" }, 5097 { { "s4" }, "$20" }, 5098 { { "s5" }, "$21" }, 5099 { { "s6" }, "$22" }, 5100 { { "s7" }, "$23" }, 5101 { { "t8" }, "$24" }, 5102 { { "t9" }, "$25" }, 5103 { { "k0" }, "$26" }, 5104 { { "k1" }, "$27" }, 5105 { { "gp" }, "$28" }, 5106 { { "sp","$sp" }, "$29" }, 5107 { { "fp","$fp" }, "$30" }, 5108 { { "ra" }, "$31" } 5109 }; 5110 Aliases = GCCRegAliases; 5111 NumAliases = llvm::array_lengthof(GCCRegAliases); 5112 } 5113 }; 5114 5115 class Mips32EBTargetInfo : public Mips32TargetInfoBase { 5116 virtual void setDescriptionString() { 5117 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 5118 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64"; 5119 } 5120 5121 public: 5122 Mips32EBTargetInfo(const llvm::Triple &Triple) 5123 : Mips32TargetInfoBase(Triple) { 5124 } 5125 virtual void getTargetDefines(const LangOptions &Opts, 5126 MacroBuilder &Builder) const { 5127 DefineStd(Builder, "MIPSEB", Opts); 5128 Builder.defineMacro("_MIPSEB"); 5129 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 5130 } 5131 }; 5132 5133 class Mips32ELTargetInfo : public Mips32TargetInfoBase { 5134 virtual void setDescriptionString() { 5135 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 5136 "i64:64:64-f32:32:32-f64:64:64-v64:64:64-n32-S64"; 5137 } 5138 5139 public: 5140 Mips32ELTargetInfo(const llvm::Triple &Triple) 5141 : Mips32TargetInfoBase(Triple) { 5142 BigEndian = false; 5143 } 5144 virtual void getTargetDefines(const LangOptions &Opts, 5145 MacroBuilder &Builder) const { 5146 DefineStd(Builder, "MIPSEL", Opts); 5147 Builder.defineMacro("_MIPSEL"); 5148 Mips32TargetInfoBase::getTargetDefines(Opts, Builder); 5149 } 5150 }; 5151 5152 class Mips64TargetInfoBase : public MipsTargetInfoBase { 5153 public: 5154 Mips64TargetInfoBase(const llvm::Triple &Triple) 5155 : MipsTargetInfoBase(Triple, "n64", "mips64") { 5156 LongWidth = LongAlign = 64; 5157 PointerWidth = PointerAlign = 64; 5158 LongDoubleWidth = LongDoubleAlign = 128; 5159 LongDoubleFormat = &llvm::APFloat::IEEEquad; 5160 if (getTriple().getOS() == llvm::Triple::FreeBSD) { 5161 LongDoubleWidth = LongDoubleAlign = 64; 5162 LongDoubleFormat = &llvm::APFloat::IEEEdouble; 5163 } 5164 SuitableAlign = 128; 5165 MaxAtomicPromoteWidth = MaxAtomicInlineWidth = 64; 5166 } 5167 virtual bool setABI(const std::string &Name) { 5168 if (Name == "n32") { 5169 LongWidth = LongAlign = 32; 5170 PointerWidth = PointerAlign = 32; 5171 ABI = Name; 5172 return true; 5173 } else if (Name == "n64") { 5174 ABI = Name; 5175 return true; 5176 } else if (Name == "64") { 5177 ABI = "n64"; 5178 return true; 5179 } else 5180 return false; 5181 } 5182 virtual void getTargetDefines(const LangOptions &Opts, 5183 MacroBuilder &Builder) const { 5184 MipsTargetInfoBase::getTargetDefines(Opts, Builder); 5185 5186 Builder.defineMacro("__mips64"); 5187 Builder.defineMacro("__mips64__"); 5188 5189 if (ABI == "n32") { 5190 Builder.defineMacro("__mips_n32"); 5191 Builder.defineMacro("_ABIN32", "2"); 5192 Builder.defineMacro("_MIPS_SIM", "_ABIN32"); 5193 } 5194 else if (ABI == "n64") { 5195 Builder.defineMacro("__mips_n64"); 5196 Builder.defineMacro("_ABI64", "3"); 5197 Builder.defineMacro("_MIPS_SIM", "_ABI64"); 5198 } 5199 else 5200 llvm_unreachable("Invalid ABI for Mips64."); 5201 } 5202 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5203 unsigned &NumAliases) const { 5204 static const TargetInfo::GCCRegAlias GCCRegAliases[] = { 5205 { { "at" }, "$1" }, 5206 { { "v0" }, "$2" }, 5207 { { "v1" }, "$3" }, 5208 { { "a0" }, "$4" }, 5209 { { "a1" }, "$5" }, 5210 { { "a2" }, "$6" }, 5211 { { "a3" }, "$7" }, 5212 { { "a4" }, "$8" }, 5213 { { "a5" }, "$9" }, 5214 { { "a6" }, "$10" }, 5215 { { "a7" }, "$11" }, 5216 { { "t0" }, "$12" }, 5217 { { "t1" }, "$13" }, 5218 { { "t2" }, "$14" }, 5219 { { "t3" }, "$15" }, 5220 { { "s0" }, "$16" }, 5221 { { "s1" }, "$17" }, 5222 { { "s2" }, "$18" }, 5223 { { "s3" }, "$19" }, 5224 { { "s4" }, "$20" }, 5225 { { "s5" }, "$21" }, 5226 { { "s6" }, "$22" }, 5227 { { "s7" }, "$23" }, 5228 { { "t8" }, "$24" }, 5229 { { "t9" }, "$25" }, 5230 { { "k0" }, "$26" }, 5231 { { "k1" }, "$27" }, 5232 { { "gp" }, "$28" }, 5233 { { "sp","$sp" }, "$29" }, 5234 { { "fp","$fp" }, "$30" }, 5235 { { "ra" }, "$31" } 5236 }; 5237 Aliases = GCCRegAliases; 5238 NumAliases = llvm::array_lengthof(GCCRegAliases); 5239 } 5240 }; 5241 5242 class Mips64EBTargetInfo : public Mips64TargetInfoBase { 5243 virtual void setDescriptionString() { 5244 if (ABI == "n32") 5245 DescriptionString = "E-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 5246 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" 5247 "v64:64:64-n32:64-S128"; 5248 else 5249 DescriptionString = "E-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 5250 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" 5251 "v64:64:64-n32:64-S128"; 5252 5253 } 5254 5255 public: 5256 Mips64EBTargetInfo(const llvm::Triple &Triple) 5257 : Mips64TargetInfoBase(Triple) {} 5258 virtual void getTargetDefines(const LangOptions &Opts, 5259 MacroBuilder &Builder) const { 5260 DefineStd(Builder, "MIPSEB", Opts); 5261 Builder.defineMacro("_MIPSEB"); 5262 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 5263 } 5264 }; 5265 5266 class Mips64ELTargetInfo : public Mips64TargetInfoBase { 5267 virtual void setDescriptionString() { 5268 if (ABI == "n32") 5269 DescriptionString = "e-p:32:32:32-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 5270 "i64:64:64-f32:32:32-f64:64:64-f128:128:128" 5271 "-v64:64:64-n32:64-S128"; 5272 else 5273 DescriptionString = "e-p:64:64:64-i1:8:8-i8:8:32-i16:16:32-i32:32:32-" 5274 "i64:64:64-f32:32:32-f64:64:64-f128:128:128-" 5275 "v64:64:64-n32:64-S128"; 5276 } 5277 public: 5278 Mips64ELTargetInfo(const llvm::Triple &Triple) 5279 : Mips64TargetInfoBase(Triple) { 5280 // Default ABI is n64. 5281 BigEndian = false; 5282 } 5283 virtual void getTargetDefines(const LangOptions &Opts, 5284 MacroBuilder &Builder) const { 5285 DefineStd(Builder, "MIPSEL", Opts); 5286 Builder.defineMacro("_MIPSEL"); 5287 Mips64TargetInfoBase::getTargetDefines(Opts, Builder); 5288 } 5289 }; 5290 } // end anonymous namespace. 5291 5292 namespace { 5293 class PNaClTargetInfo : public TargetInfo { 5294 public: 5295 PNaClTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5296 BigEndian = false; 5297 this->UserLabelPrefix = ""; 5298 this->LongAlign = 32; 5299 this->LongWidth = 32; 5300 this->PointerAlign = 32; 5301 this->PointerWidth = 32; 5302 this->IntMaxType = TargetInfo::SignedLongLong; 5303 this->UIntMaxType = TargetInfo::UnsignedLongLong; 5304 this->Int64Type = TargetInfo::SignedLongLong; 5305 this->DoubleAlign = 64; 5306 this->LongDoubleWidth = 64; 5307 this->LongDoubleAlign = 64; 5308 this->SizeType = TargetInfo::UnsignedInt; 5309 this->PtrDiffType = TargetInfo::SignedInt; 5310 this->IntPtrType = TargetInfo::SignedInt; 5311 this->RegParmMax = 0; // Disallow regparm 5312 DescriptionString = "e-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 5313 "f32:32:32-f64:64:64-p:32:32:32-v128:32:32"; 5314 } 5315 5316 void getDefaultFeatures(llvm::StringMap<bool> &Features) const { 5317 } 5318 virtual void getArchDefines(const LangOptions &Opts, 5319 MacroBuilder &Builder) const { 5320 Builder.defineMacro("__le32__"); 5321 Builder.defineMacro("__pnacl__"); 5322 } 5323 virtual void getTargetDefines(const LangOptions &Opts, 5324 MacroBuilder &Builder) const { 5325 Builder.defineMacro("__LITTLE_ENDIAN__"); 5326 getArchDefines(Opts, Builder); 5327 } 5328 virtual bool hasFeature(StringRef Feature) const { 5329 return Feature == "pnacl"; 5330 } 5331 virtual void getTargetBuiltins(const Builtin::Info *&Records, 5332 unsigned &NumRecords) const { 5333 } 5334 virtual BuiltinVaListKind getBuiltinVaListKind() const { 5335 return TargetInfo::PNaClABIBuiltinVaList; 5336 } 5337 virtual void getGCCRegNames(const char * const *&Names, 5338 unsigned &NumNames) const; 5339 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5340 unsigned &NumAliases) const; 5341 virtual bool validateAsmConstraint(const char *&Name, 5342 TargetInfo::ConstraintInfo &Info) const { 5343 return false; 5344 } 5345 5346 virtual const char *getClobbers() const { 5347 return ""; 5348 } 5349 }; 5350 5351 void PNaClTargetInfo::getGCCRegNames(const char * const *&Names, 5352 unsigned &NumNames) const { 5353 Names = NULL; 5354 NumNames = 0; 5355 } 5356 5357 void PNaClTargetInfo::getGCCRegAliases(const GCCRegAlias *&Aliases, 5358 unsigned &NumAliases) const { 5359 Aliases = NULL; 5360 NumAliases = 0; 5361 } 5362 } // end anonymous namespace. 5363 5364 namespace { 5365 static const unsigned SPIRAddrSpaceMap[] = { 5366 1, // opencl_global 5367 3, // opencl_local 5368 2, // opencl_constant 5369 0, // cuda_device 5370 0, // cuda_constant 5371 0 // cuda_shared 5372 }; 5373 class SPIRTargetInfo : public TargetInfo { 5374 public: 5375 SPIRTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5376 assert(getTriple().getOS() == llvm::Triple::UnknownOS && 5377 "SPIR target must use unknown OS"); 5378 assert(getTriple().getEnvironment() == llvm::Triple::UnknownEnvironment && 5379 "SPIR target must use unknown environment type"); 5380 BigEndian = false; 5381 TLSSupported = false; 5382 LongWidth = LongAlign = 64; 5383 AddrSpaceMap = &SPIRAddrSpaceMap; 5384 UseAddrSpaceMapMangling = true; 5385 // Define available target features 5386 // These must be defined in sorted order! 5387 NoAsmVariants = true; 5388 } 5389 virtual void getTargetDefines(const LangOptions &Opts, 5390 MacroBuilder &Builder) const { 5391 DefineStd(Builder, "SPIR", Opts); 5392 } 5393 virtual bool hasFeature(StringRef Feature) const { 5394 return Feature == "spir"; 5395 } 5396 5397 virtual void getTargetBuiltins(const Builtin::Info *&Records, 5398 unsigned &NumRecords) const {} 5399 virtual const char *getClobbers() const { 5400 return ""; 5401 } 5402 virtual void getGCCRegNames(const char * const *&Names, 5403 unsigned &NumNames) const {} 5404 virtual bool validateAsmConstraint(const char *&Name, 5405 TargetInfo::ConstraintInfo &info) const { 5406 return true; 5407 } 5408 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5409 unsigned &NumAliases) const {} 5410 virtual BuiltinVaListKind getBuiltinVaListKind() const { 5411 return TargetInfo::VoidPtrBuiltinVaList; 5412 } 5413 }; 5414 5415 5416 class SPIR32TargetInfo : public SPIRTargetInfo { 5417 public: 5418 SPIR32TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 5419 PointerWidth = PointerAlign = 32; 5420 SizeType = TargetInfo::UnsignedInt; 5421 PtrDiffType = IntPtrType = TargetInfo::SignedInt; 5422 DescriptionString 5423 = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 5424 "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-" 5425 "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-" 5426 "v512:512:512-v1024:1024:1024"; 5427 } 5428 virtual void getTargetDefines(const LangOptions &Opts, 5429 MacroBuilder &Builder) const { 5430 DefineStd(Builder, "SPIR32", Opts); 5431 } 5432 }; 5433 5434 class SPIR64TargetInfo : public SPIRTargetInfo { 5435 public: 5436 SPIR64TargetInfo(const llvm::Triple &Triple) : SPIRTargetInfo(Triple) { 5437 PointerWidth = PointerAlign = 64; 5438 SizeType = TargetInfo::UnsignedLong; 5439 PtrDiffType = IntPtrType = TargetInfo::SignedLong; 5440 DescriptionString 5441 = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-" 5442 "f32:32:32-f64:64:64-v16:16:16-v24:32:32-v32:32:32-v48:64:64-" 5443 "v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-" 5444 "v512:512:512-v1024:1024:1024"; 5445 } 5446 virtual void getTargetDefines(const LangOptions &Opts, 5447 MacroBuilder &Builder) const { 5448 DefineStd(Builder, "SPIR64", Opts); 5449 } 5450 }; 5451 } 5452 5453 namespace { 5454 class XCoreTargetInfo : public TargetInfo { 5455 static const Builtin::Info BuiltinInfo[]; 5456 public: 5457 XCoreTargetInfo(const llvm::Triple &Triple) : TargetInfo(Triple) { 5458 BigEndian = false; 5459 NoAsmVariants = true; 5460 LongLongAlign = 32; 5461 SuitableAlign = 32; 5462 DoubleAlign = LongDoubleAlign = 32; 5463 SizeType = UnsignedInt; 5464 PtrDiffType = SignedInt; 5465 IntPtrType = SignedInt; 5466 WCharType = UnsignedChar; 5467 WIntType = UnsignedInt; 5468 UseZeroLengthBitfieldAlignment = true; 5469 DescriptionString = "e-p:32:32:32-a0:0:32-n32" 5470 "-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32" 5471 "-f16:16:32-f32:32:32-f64:32:32"; 5472 } 5473 virtual void getTargetDefines(const LangOptions &Opts, 5474 MacroBuilder &Builder) const { 5475 Builder.defineMacro("__XS1B__"); 5476 } 5477 virtual void getTargetBuiltins(const Builtin::Info *&Records, 5478 unsigned &NumRecords) const { 5479 Records = BuiltinInfo; 5480 NumRecords = clang::XCore::LastTSBuiltin-Builtin::FirstTSBuiltin; 5481 } 5482 virtual BuiltinVaListKind getBuiltinVaListKind() const { 5483 return TargetInfo::VoidPtrBuiltinVaList; 5484 } 5485 virtual const char *getClobbers() const { 5486 return ""; 5487 } 5488 virtual void getGCCRegNames(const char * const *&Names, 5489 unsigned &NumNames) const { 5490 static const char * const GCCRegNames[] = { 5491 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 5492 "r8", "r9", "r10", "r11", "cp", "dp", "sp", "lr" 5493 }; 5494 Names = GCCRegNames; 5495 NumNames = llvm::array_lengthof(GCCRegNames); 5496 } 5497 virtual void getGCCRegAliases(const GCCRegAlias *&Aliases, 5498 unsigned &NumAliases) const { 5499 Aliases = NULL; 5500 NumAliases = 0; 5501 } 5502 virtual bool validateAsmConstraint(const char *&Name, 5503 TargetInfo::ConstraintInfo &Info) const { 5504 return false; 5505 } 5506 }; 5507 5508 const Builtin::Info XCoreTargetInfo::BuiltinInfo[] = { 5509 #define BUILTIN(ID, TYPE, ATTRS) { #ID, TYPE, ATTRS, 0, ALL_LANGUAGES }, 5510 #define LIBBUILTIN(ID, TYPE, ATTRS, HEADER) { #ID, TYPE, ATTRS, HEADER,\ 5511 ALL_LANGUAGES }, 5512 #include "clang/Basic/BuiltinsXCore.def" 5513 }; 5514 } // end anonymous namespace. 5515 5516 5517 //===----------------------------------------------------------------------===// 5518 // Driver code 5519 //===----------------------------------------------------------------------===// 5520 5521 static TargetInfo *AllocateTarget(const llvm::Triple &Triple) { 5522 llvm::Triple::OSType os = Triple.getOS(); 5523 5524 switch (Triple.getArch()) { 5525 default: 5526 return NULL; 5527 5528 case llvm::Triple::xcore: 5529 return new XCoreTargetInfo(Triple); 5530 5531 case llvm::Triple::hexagon: 5532 return new HexagonTargetInfo(Triple); 5533 5534 case llvm::Triple::aarch64: 5535 switch (os) { 5536 case llvm::Triple::Linux: 5537 return new LinuxTargetInfo<AArch64TargetInfo>(Triple); 5538 default: 5539 return new AArch64TargetInfo(Triple); 5540 } 5541 5542 case llvm::Triple::arm: 5543 case llvm::Triple::thumb: 5544 if (Triple.isOSDarwin()) 5545 return new DarwinARMTargetInfo(Triple); 5546 5547 switch (os) { 5548 case llvm::Triple::Linux: 5549 return new LinuxTargetInfo<ARMTargetInfo>(Triple); 5550 case llvm::Triple::FreeBSD: 5551 return new FreeBSDTargetInfo<ARMTargetInfo>(Triple); 5552 case llvm::Triple::NetBSD: 5553 return new NetBSDTargetInfo<ARMTargetInfo>(Triple); 5554 case llvm::Triple::Minix: 5555 return new MinixTargetInfo<ARMTargetInfo>(Triple); 5556 case llvm::Triple::OpenBSD: 5557 return new OpenBSDTargetInfo<ARMTargetInfo>(Triple); 5558 case llvm::Triple::Bitrig: 5559 return new BitrigTargetInfo<ARMTargetInfo>(Triple); 5560 case llvm::Triple::RTEMS: 5561 return new RTEMSTargetInfo<ARMTargetInfo>(Triple); 5562 case llvm::Triple::NaCl: 5563 return new NaClTargetInfo<ARMTargetInfo>(Triple); 5564 default: 5565 return new ARMTargetInfo(Triple); 5566 } 5567 5568 case llvm::Triple::msp430: 5569 return new MSP430TargetInfo(Triple); 5570 5571 case llvm::Triple::mips: 5572 switch (os) { 5573 case llvm::Triple::Linux: 5574 return new LinuxTargetInfo<Mips32EBTargetInfo>(Triple); 5575 case llvm::Triple::RTEMS: 5576 return new RTEMSTargetInfo<Mips32EBTargetInfo>(Triple); 5577 case llvm::Triple::FreeBSD: 5578 return new FreeBSDTargetInfo<Mips32EBTargetInfo>(Triple); 5579 case llvm::Triple::NetBSD: 5580 return new NetBSDTargetInfo<Mips32EBTargetInfo>(Triple); 5581 default: 5582 return new Mips32EBTargetInfo(Triple); 5583 } 5584 5585 case llvm::Triple::mipsel: 5586 switch (os) { 5587 case llvm::Triple::Linux: 5588 return new LinuxTargetInfo<Mips32ELTargetInfo>(Triple); 5589 case llvm::Triple::RTEMS: 5590 return new RTEMSTargetInfo<Mips32ELTargetInfo>(Triple); 5591 case llvm::Triple::FreeBSD: 5592 return new FreeBSDTargetInfo<Mips32ELTargetInfo>(Triple); 5593 case llvm::Triple::NetBSD: 5594 return new NetBSDTargetInfo<Mips32ELTargetInfo>(Triple); 5595 case llvm::Triple::NaCl: 5596 return new NaClTargetInfo<Mips32ELTargetInfo>(Triple); 5597 default: 5598 return new Mips32ELTargetInfo(Triple); 5599 } 5600 5601 case llvm::Triple::mips64: 5602 switch (os) { 5603 case llvm::Triple::Linux: 5604 return new LinuxTargetInfo<Mips64EBTargetInfo>(Triple); 5605 case llvm::Triple::RTEMS: 5606 return new RTEMSTargetInfo<Mips64EBTargetInfo>(Triple); 5607 case llvm::Triple::FreeBSD: 5608 return new FreeBSDTargetInfo<Mips64EBTargetInfo>(Triple); 5609 case llvm::Triple::NetBSD: 5610 return new NetBSDTargetInfo<Mips64EBTargetInfo>(Triple); 5611 case llvm::Triple::OpenBSD: 5612 return new OpenBSDTargetInfo<Mips64EBTargetInfo>(Triple); 5613 default: 5614 return new Mips64EBTargetInfo(Triple); 5615 } 5616 5617 case llvm::Triple::mips64el: 5618 switch (os) { 5619 case llvm::Triple::Linux: 5620 return new LinuxTargetInfo<Mips64ELTargetInfo>(Triple); 5621 case llvm::Triple::RTEMS: 5622 return new RTEMSTargetInfo<Mips64ELTargetInfo>(Triple); 5623 case llvm::Triple::FreeBSD: 5624 return new FreeBSDTargetInfo<Mips64ELTargetInfo>(Triple); 5625 case llvm::Triple::NetBSD: 5626 return new NetBSDTargetInfo<Mips64ELTargetInfo>(Triple); 5627 case llvm::Triple::OpenBSD: 5628 return new OpenBSDTargetInfo<Mips64ELTargetInfo>(Triple); 5629 default: 5630 return new Mips64ELTargetInfo(Triple); 5631 } 5632 5633 case llvm::Triple::le32: 5634 switch (os) { 5635 case llvm::Triple::NaCl: 5636 return new NaClTargetInfo<PNaClTargetInfo>(Triple); 5637 default: 5638 return NULL; 5639 } 5640 5641 case llvm::Triple::ppc: 5642 if (Triple.isOSDarwin()) 5643 return new DarwinPPC32TargetInfo(Triple); 5644 switch (os) { 5645 case llvm::Triple::Linux: 5646 return new LinuxTargetInfo<PPC32TargetInfo>(Triple); 5647 case llvm::Triple::FreeBSD: 5648 return new FreeBSDTargetInfo<PPC32TargetInfo>(Triple); 5649 case llvm::Triple::NetBSD: 5650 return new NetBSDTargetInfo<PPC32TargetInfo>(Triple); 5651 case llvm::Triple::OpenBSD: 5652 return new OpenBSDTargetInfo<PPC32TargetInfo>(Triple); 5653 case llvm::Triple::RTEMS: 5654 return new RTEMSTargetInfo<PPC32TargetInfo>(Triple); 5655 default: 5656 return new PPC32TargetInfo(Triple); 5657 } 5658 5659 case llvm::Triple::ppc64: 5660 if (Triple.isOSDarwin()) 5661 return new DarwinPPC64TargetInfo(Triple); 5662 switch (os) { 5663 case llvm::Triple::Linux: 5664 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 5665 case llvm::Triple::Lv2: 5666 return new PS3PPUTargetInfo<PPC64TargetInfo>(Triple); 5667 case llvm::Triple::FreeBSD: 5668 return new FreeBSDTargetInfo<PPC64TargetInfo>(Triple); 5669 case llvm::Triple::NetBSD: 5670 return new NetBSDTargetInfo<PPC64TargetInfo>(Triple); 5671 default: 5672 return new PPC64TargetInfo(Triple); 5673 } 5674 5675 case llvm::Triple::ppc64le: 5676 switch (os) { 5677 case llvm::Triple::Linux: 5678 return new LinuxTargetInfo<PPC64TargetInfo>(Triple); 5679 default: 5680 return new PPC64TargetInfo(Triple); 5681 } 5682 5683 case llvm::Triple::nvptx: 5684 return new NVPTX32TargetInfo(Triple); 5685 case llvm::Triple::nvptx64: 5686 return new NVPTX64TargetInfo(Triple); 5687 5688 case llvm::Triple::r600: 5689 return new R600TargetInfo(Triple); 5690 5691 case llvm::Triple::sparc: 5692 switch (os) { 5693 case llvm::Triple::Linux: 5694 return new LinuxTargetInfo<SparcV8TargetInfo>(Triple); 5695 case llvm::Triple::AuroraUX: 5696 return new AuroraUXSparcV8TargetInfo(Triple); 5697 case llvm::Triple::Solaris: 5698 return new SolarisSparcV8TargetInfo(Triple); 5699 case llvm::Triple::NetBSD: 5700 return new NetBSDTargetInfo<SparcV8TargetInfo>(Triple); 5701 case llvm::Triple::OpenBSD: 5702 return new OpenBSDTargetInfo<SparcV8TargetInfo>(Triple); 5703 case llvm::Triple::RTEMS: 5704 return new RTEMSTargetInfo<SparcV8TargetInfo>(Triple); 5705 default: 5706 return new SparcV8TargetInfo(Triple); 5707 } 5708 5709 case llvm::Triple::sparcv9: 5710 switch (os) { 5711 case llvm::Triple::Linux: 5712 return new LinuxTargetInfo<SparcV9TargetInfo>(Triple); 5713 case llvm::Triple::AuroraUX: 5714 return new AuroraUXTargetInfo<SparcV9TargetInfo>(Triple); 5715 case llvm::Triple::Solaris: 5716 return new SolarisTargetInfo<SparcV9TargetInfo>(Triple); 5717 case llvm::Triple::NetBSD: 5718 return new NetBSDTargetInfo<SparcV9TargetInfo>(Triple); 5719 case llvm::Triple::OpenBSD: 5720 return new OpenBSDTargetInfo<SparcV9TargetInfo>(Triple); 5721 case llvm::Triple::FreeBSD: 5722 return new FreeBSDTargetInfo<SparcV9TargetInfo>(Triple); 5723 default: 5724 return new SparcV9TargetInfo(Triple); 5725 } 5726 5727 case llvm::Triple::systemz: 5728 switch (os) { 5729 case llvm::Triple::Linux: 5730 return new LinuxTargetInfo<SystemZTargetInfo>(Triple); 5731 default: 5732 return new SystemZTargetInfo(Triple); 5733 } 5734 5735 case llvm::Triple::tce: 5736 return new TCETargetInfo(Triple); 5737 5738 case llvm::Triple::x86: 5739 if (Triple.isOSDarwin()) 5740 return new DarwinI386TargetInfo(Triple); 5741 5742 switch (os) { 5743 case llvm::Triple::AuroraUX: 5744 return new AuroraUXTargetInfo<X86_32TargetInfo>(Triple); 5745 case llvm::Triple::Linux: 5746 return new LinuxTargetInfo<X86_32TargetInfo>(Triple); 5747 case llvm::Triple::DragonFly: 5748 return new DragonFlyBSDTargetInfo<X86_32TargetInfo>(Triple); 5749 case llvm::Triple::NetBSD: 5750 return new NetBSDI386TargetInfo(Triple); 5751 case llvm::Triple::OpenBSD: 5752 return new OpenBSDI386TargetInfo(Triple); 5753 case llvm::Triple::Bitrig: 5754 return new BitrigI386TargetInfo(Triple); 5755 case llvm::Triple::FreeBSD: 5756 return new FreeBSDTargetInfo<X86_32TargetInfo>(Triple); 5757 case llvm::Triple::KFreeBSD: 5758 return new KFreeBSDTargetInfo<X86_32TargetInfo>(Triple); 5759 case llvm::Triple::Minix: 5760 return new MinixTargetInfo<X86_32TargetInfo>(Triple); 5761 case llvm::Triple::Solaris: 5762 return new SolarisTargetInfo<X86_32TargetInfo>(Triple); 5763 case llvm::Triple::Cygwin: 5764 return new CygwinX86_32TargetInfo(Triple); 5765 case llvm::Triple::MinGW32: 5766 return new MinGWX86_32TargetInfo(Triple); 5767 case llvm::Triple::Win32: 5768 return new VisualStudioWindowsX86_32TargetInfo(Triple); 5769 case llvm::Triple::Haiku: 5770 return new HaikuX86_32TargetInfo(Triple); 5771 case llvm::Triple::RTEMS: 5772 return new RTEMSX86_32TargetInfo(Triple); 5773 case llvm::Triple::NaCl: 5774 return new NaClTargetInfo<X86_32TargetInfo>(Triple); 5775 default: 5776 return new X86_32TargetInfo(Triple); 5777 } 5778 5779 case llvm::Triple::x86_64: 5780 if (Triple.isOSDarwin() || Triple.getEnvironment() == llvm::Triple::MachO) 5781 return new DarwinX86_64TargetInfo(Triple); 5782 5783 switch (os) { 5784 case llvm::Triple::AuroraUX: 5785 return new AuroraUXTargetInfo<X86_64TargetInfo>(Triple); 5786 case llvm::Triple::Linux: 5787 return new LinuxTargetInfo<X86_64TargetInfo>(Triple); 5788 case llvm::Triple::DragonFly: 5789 return new DragonFlyBSDTargetInfo<X86_64TargetInfo>(Triple); 5790 case llvm::Triple::NetBSD: 5791 return new NetBSDTargetInfo<X86_64TargetInfo>(Triple); 5792 case llvm::Triple::OpenBSD: 5793 return new OpenBSDX86_64TargetInfo(Triple); 5794 case llvm::Triple::Bitrig: 5795 return new BitrigX86_64TargetInfo(Triple); 5796 case llvm::Triple::FreeBSD: 5797 return new FreeBSDTargetInfo<X86_64TargetInfo>(Triple); 5798 case llvm::Triple::KFreeBSD: 5799 return new KFreeBSDTargetInfo<X86_64TargetInfo>(Triple); 5800 case llvm::Triple::Solaris: 5801 return new SolarisTargetInfo<X86_64TargetInfo>(Triple); 5802 case llvm::Triple::MinGW32: 5803 return new MinGWX86_64TargetInfo(Triple); 5804 case llvm::Triple::Win32: // This is what Triple.h supports now. 5805 return new VisualStudioWindowsX86_64TargetInfo(Triple); 5806 case llvm::Triple::NaCl: 5807 return new NaClTargetInfo<X86_64TargetInfo>(Triple); 5808 default: 5809 return new X86_64TargetInfo(Triple); 5810 } 5811 5812 case llvm::Triple::spir: { 5813 if (Triple.getOS() != llvm::Triple::UnknownOS || 5814 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 5815 return NULL; 5816 return new SPIR32TargetInfo(Triple); 5817 } 5818 case llvm::Triple::spir64: { 5819 if (Triple.getOS() != llvm::Triple::UnknownOS || 5820 Triple.getEnvironment() != llvm::Triple::UnknownEnvironment) 5821 return NULL; 5822 return new SPIR64TargetInfo(Triple); 5823 } 5824 } 5825 } 5826 5827 /// CreateTargetInfo - Return the target info object for the specified target 5828 /// triple. 5829 TargetInfo *TargetInfo::CreateTargetInfo(DiagnosticsEngine &Diags, 5830 TargetOptions *Opts) { 5831 llvm::Triple Triple(Opts->Triple); 5832 5833 // Construct the target 5834 OwningPtr<TargetInfo> Target(AllocateTarget(Triple)); 5835 if (!Target) { 5836 Diags.Report(diag::err_target_unknown_triple) << Triple.str(); 5837 return 0; 5838 } 5839 Target->setTargetOpts(Opts); 5840 5841 // Set the target CPU if specified. 5842 if (!Opts->CPU.empty() && !Target->setCPU(Opts->CPU)) { 5843 Diags.Report(diag::err_target_unknown_cpu) << Opts->CPU; 5844 return 0; 5845 } 5846 5847 // Set the target ABI if specified. 5848 if (!Opts->ABI.empty() && !Target->setABI(Opts->ABI)) { 5849 Diags.Report(diag::err_target_unknown_abi) << Opts->ABI; 5850 return 0; 5851 } 5852 5853 // Set the target C++ ABI. 5854 if (!Opts->CXXABI.empty() && !Target->setCXXABI(Opts->CXXABI)) { 5855 Diags.Report(diag::err_target_unknown_cxxabi) << Opts->CXXABI; 5856 return 0; 5857 } 5858 5859 // Set the fp math unit. 5860 if (!Opts->FPMath.empty() && !Target->setFPMath(Opts->FPMath)) { 5861 Diags.Report(diag::err_target_unknown_fpmath) << Opts->FPMath; 5862 return 0; 5863 } 5864 5865 // Compute the default target features, we need the target to handle this 5866 // because features may have dependencies on one another. 5867 llvm::StringMap<bool> Features; 5868 Target->getDefaultFeatures(Features); 5869 5870 // Apply the user specified deltas. 5871 for (unsigned I = 0, N = Opts->FeaturesAsWritten.size(); 5872 I < N; ++I) { 5873 const char *Name = Opts->FeaturesAsWritten[I].c_str(); 5874 // Apply the feature via the target. 5875 bool Enabled = Name[0] == '+'; 5876 Target->setFeatureEnabled(Features, Name + 1, Enabled); 5877 } 5878 5879 // Add the features to the compile options. 5880 // 5881 // FIXME: If we are completely confident that we have the right set, we only 5882 // need to pass the minuses. 5883 Opts->Features.clear(); 5884 for (llvm::StringMap<bool>::const_iterator it = Features.begin(), 5885 ie = Features.end(); it != ie; ++it) 5886 Opts->Features.push_back((it->second ? "+" : "-") + it->first().str()); 5887 if (!Target->handleTargetFeatures(Opts->Features, Diags)) 5888 return 0; 5889 5890 return Target.take(); 5891 } 5892