1 //===- SparseTensorPipelines.cpp - Pipelines for sparse tensor code -------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "mlir/Dialect/SparseTensor/Pipelines/Passes.h" 10 11 #include "mlir/Conversion/GPUToNVVM/GPUToNVVMPass.h" 12 #include "mlir/Conversion/Passes.h" 13 #include "mlir/Dialect/Arith/Transforms/Passes.h" 14 #include "mlir/Dialect/Bufferization/Transforms/Bufferize.h" 15 #include "mlir/Dialect/Bufferization/Transforms/OneShotAnalysis.h" 16 #include "mlir/Dialect/Bufferization/Transforms/Passes.h" 17 #include "mlir/Dialect/Func/IR/FuncOps.h" 18 #include "mlir/Dialect/GPU/IR/GPUDialect.h" 19 #include "mlir/Dialect/GPU/Transforms/Passes.h" 20 #include "mlir/Dialect/LLVMIR/NVVMDialect.h" 21 #include "mlir/Dialect/Linalg/Passes.h" 22 #include "mlir/Dialect/MemRef/Transforms/Passes.h" 23 #include "mlir/Dialect/SparseTensor/IR/SparseTensor.h" 24 #include "mlir/Dialect/SparseTensor/Transforms/Passes.h" 25 #include "mlir/Pass/PassManager.h" 26 #include "mlir/Transforms/Passes.h" 27 28 //===----------------------------------------------------------------------===// 29 // Pipeline implementation. 30 //===----------------------------------------------------------------------===// 31 32 void mlir::sparse_tensor::buildSparseCompiler( 33 OpPassManager &pm, const SparseCompilerOptions &options) { 34 pm.addNestedPass<func::FuncOp>(createLinalgGeneralizationPass()); 35 pm.addPass(createSparsificationAndBufferizationPass( 36 getBufferizationOptionsForSparsification( 37 options.testBufferizationAnalysisOnly), 38 options.sparsificationOptions(), options.sparseTensorConversionOptions(), 39 options.createSparseDeallocs, options.enableRuntimeLibrary, 40 options.enableBufferInitialization, options.vectorLength, 41 /*enableVLAVectorization=*/options.armSVE, 42 /*enableSIMDIndex32=*/options.force32BitVectorIndices)); 43 if (options.testBufferizationAnalysisOnly) 44 return; 45 46 pm.addPass(createStorageSpecifierToLLVMPass()); 47 pm.addNestedPass<func::FuncOp>(createCanonicalizerPass()); 48 pm.addNestedPass<func::FuncOp>( 49 mlir::bufferization::createFinalizingBufferizePass()); 50 51 // GPU code generation. 52 const bool gpuCodegen = options.gpuTriple.hasValue(); 53 if (gpuCodegen) { 54 pm.addPass(createSparseGPUCodegenPass()); 55 pm.addNestedPass<gpu::GPUModuleOp>(createStripDebugInfoPass()); 56 pm.addNestedPass<gpu::GPUModuleOp>(createConvertSCFToCFPass()); 57 pm.addNestedPass<gpu::GPUModuleOp>(createConvertGpuOpsToNVVMOps()); 58 } 59 60 // TODO(springerm): Add sparse support to the BufferDeallocation pass and add 61 // it to this pipeline. 62 pm.addNestedPass<func::FuncOp>(createConvertLinalgToLoopsPass()); 63 pm.addNestedPass<func::FuncOp>(createConvertVectorToSCFPass()); 64 pm.addNestedPass<func::FuncOp>(memref::createExpandReallocPass()); 65 pm.addNestedPass<func::FuncOp>(createConvertSCFToCFPass()); 66 pm.addPass(memref::createExpandStridedMetadataPass()); 67 pm.addPass(createLowerAffinePass()); 68 pm.addPass(createConvertVectorToLLVMPass(options.lowerVectorToLLVMOptions())); 69 pm.addPass(createFinalizeMemRefToLLVMConversionPass()); 70 pm.addNestedPass<func::FuncOp>(createConvertComplexToStandardPass()); 71 pm.addNestedPass<func::FuncOp>(arith::createArithExpandOpsPass()); 72 pm.addNestedPass<func::FuncOp>(createConvertMathToLLVMPass()); 73 pm.addPass(createConvertMathToLibmPass()); 74 pm.addPass(createConvertComplexToLibmPass()); 75 // Repeat convert-vector-to-llvm. 76 pm.addPass(createConvertVectorToLLVMPass(options.lowerVectorToLLVMOptions())); 77 pm.addPass(createConvertComplexToLLVMPass()); 78 pm.addPass(createConvertVectorToLLVMPass(options.lowerVectorToLLVMOptions())); 79 pm.addPass(createConvertFuncToLLVMPass()); 80 81 // Finalize GPU code generation. 82 if (gpuCodegen) { 83 GpuNVVMAttachTargetOptions nvvmTargetOptions; 84 nvvmTargetOptions.triple = options.gpuTriple; 85 nvvmTargetOptions.chip = options.gpuChip; 86 nvvmTargetOptions.features = options.gpuFeatures; 87 pm.addPass(createGpuNVVMAttachTarget(nvvmTargetOptions)); 88 pm.addPass(createGpuToLLVMConversionPass()); 89 GpuModuleToBinaryPassOptions gpuModuleToBinaryPassOptions; 90 gpuModuleToBinaryPassOptions.compilationTarget = options.gpuFormat; 91 pm.addPass(createGpuModuleToBinaryPass(gpuModuleToBinaryPassOptions)); 92 } 93 94 pm.addPass(createReconcileUnrealizedCastsPass()); 95 } 96 97 //===----------------------------------------------------------------------===// 98 // Pipeline registration. 99 //===----------------------------------------------------------------------===// 100 101 void mlir::sparse_tensor::registerSparseTensorPipelines() { 102 PassPipelineRegistration<SparseCompilerOptions>( 103 "sparse-compiler", 104 "The standard pipeline for taking sparsity-agnostic IR using the" 105 " sparse-tensor type, and lowering it to LLVM IR with concrete" 106 " representations and algorithms for sparse tensors.", 107 buildSparseCompiler); 108 } 109