1 //===- LowerGpuOpsToROCDLOps.cpp - MLIR GPU to ROCDL lowering passes ------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements a pass to generate ROCDLIR operations for higher-level 10 // GPU operations. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "mlir/Conversion/ControlFlowToLLVM/ControlFlowToLLVM.h" 15 #include "mlir/Conversion/GPUToROCDL/GPUToROCDLPass.h" 16 17 #include "mlir/Conversion/ArithmeticToLLVM/ArithmeticToLLVM.h" 18 #include "mlir/Conversion/FuncToLLVM/ConvertFuncToLLVM.h" 19 #include "mlir/Conversion/LLVMCommon/ConversionTarget.h" 20 #include "mlir/Conversion/LLVMCommon/LoweringOptions.h" 21 #include "mlir/Conversion/LLVMCommon/Pattern.h" 22 #include "mlir/Conversion/LLVMCommon/TypeConverter.h" 23 #include "mlir/Conversion/MemRefToLLVM/MemRefToLLVM.h" 24 #include "mlir/Conversion/VectorToLLVM/ConvertVectorToLLVM.h" 25 #include "mlir/Conversion/VectorToROCDL/VectorToROCDL.h" 26 #include "mlir/Dialect/Func/IR/FuncOps.h" 27 #include "mlir/Dialect/GPU/GPUDialect.h" 28 #include "mlir/Dialect/GPU/Passes.h" 29 #include "mlir/Dialect/LLVMIR/ROCDLDialect.h" 30 #include "mlir/Dialect/Math/IR/Math.h" 31 #include "mlir/Dialect/Vector/IR/VectorOps.h" 32 #include "mlir/Pass/Pass.h" 33 #include "mlir/Transforms/DialectConversion.h" 34 #include "mlir/Transforms/GreedyPatternRewriteDriver.h" 35 #include "llvm/Support/FormatVariadic.h" 36 37 #include "../GPUCommon/GPUOpsLowering.h" 38 #include "../GPUCommon/IndexIntrinsicsOpLowering.h" 39 #include "../GPUCommon/OpToFuncCallLowering.h" 40 #include "../PassDetail.h" 41 42 using namespace mlir; 43 44 namespace { 45 46 /// Import the GPU Ops to ROCDL Patterns. 47 #include "GPUToROCDL.cpp.inc" 48 49 // A pass that replaces all occurrences of GPU device operations with their 50 // corresponding ROCDL equivalent. 51 // 52 // This pass only handles device code and is not meant to be run on GPU host 53 // code. 54 struct LowerGpuOpsToROCDLOpsPass 55 : public ConvertGpuOpsToROCDLOpsBase<LowerGpuOpsToROCDLOpsPass> { 56 LowerGpuOpsToROCDLOpsPass() = default; 57 LowerGpuOpsToROCDLOpsPass(unsigned indexBitwidth, gpu::amd::Runtime runtime) { 58 this->indexBitwidth = indexBitwidth; 59 this->runtime = runtime; 60 } 61 62 void runOnOperation() override { 63 gpu::GPUModuleOp m = getOperation(); 64 65 /// Customize the bitwidth used for the device side index computations. 66 LowerToLLVMOptions options( 67 m.getContext(), 68 DataLayout(cast<DataLayoutOpInterface>(m.getOperation()))); 69 options.emitCWrappers = true; 70 if (indexBitwidth != kDeriveIndexBitwidthFromDataLayout) 71 options.overrideIndexBitwidth(indexBitwidth); 72 LLVMTypeConverter converter(m.getContext(), options); 73 74 RewritePatternSet patterns(m.getContext()); 75 RewritePatternSet llvmPatterns(m.getContext()); 76 77 populateGpuRewritePatterns(patterns); 78 (void)applyPatternsAndFoldGreedily(m, std::move(patterns)); 79 80 mlir::arith::populateArithmeticToLLVMConversionPatterns(converter, 81 llvmPatterns); 82 populateVectorToLLVMConversionPatterns(converter, llvmPatterns); 83 populateVectorToROCDLConversionPatterns(converter, llvmPatterns); 84 cf::populateControlFlowToLLVMConversionPatterns(converter, llvmPatterns); 85 populateFuncToLLVMConversionPatterns(converter, llvmPatterns); 86 populateMemRefToLLVMConversionPatterns(converter, llvmPatterns); 87 populateGpuToROCDLConversionPatterns(converter, llvmPatterns, runtime); 88 LLVMConversionTarget target(getContext()); 89 configureGpuToROCDLConversionLegality(target); 90 if (failed(applyPartialConversion(m, target, std::move(llvmPatterns)))) 91 signalPassFailure(); 92 } 93 }; 94 95 } // namespace 96 97 void mlir::configureGpuToROCDLConversionLegality(ConversionTarget &target) { 98 target.addIllegalOp<func::FuncOp>(); 99 target.addLegalDialect<::mlir::LLVM::LLVMDialect>(); 100 target.addLegalDialect<ROCDL::ROCDLDialect>(); 101 target.addIllegalDialect<gpu::GPUDialect>(); 102 target.addIllegalOp<LLVM::CosOp, LLVM::ExpOp, LLVM::Exp2Op, LLVM::FAbsOp, 103 LLVM::FCeilOp, LLVM::FFloorOp, LLVM::LogOp, LLVM::Log10Op, 104 LLVM::Log2Op, LLVM::PowOp, LLVM::SinOp, LLVM::SqrtOp>(); 105 106 // TODO: Remove once we support replacing non-root ops. 107 target.addLegalOp<gpu::YieldOp, gpu::GPUModuleOp, gpu::ModuleEndOp>(); 108 } 109 110 void mlir::populateGpuToROCDLConversionPatterns( 111 LLVMTypeConverter &converter, RewritePatternSet &patterns, 112 mlir::gpu::amd::Runtime runtime) { 113 using mlir::gpu::amd::Runtime; 114 115 populateWithGenerated(patterns); 116 patterns 117 .add<GPUIndexIntrinsicOpLowering<gpu::ThreadIdOp, ROCDL::ThreadIdXOp, 118 ROCDL::ThreadIdYOp, ROCDL::ThreadIdZOp>, 119 GPUIndexIntrinsicOpLowering<gpu::BlockDimOp, ROCDL::BlockDimXOp, 120 ROCDL::BlockDimYOp, ROCDL::BlockDimZOp>, 121 GPUIndexIntrinsicOpLowering<gpu::BlockIdOp, ROCDL::BlockIdXOp, 122 ROCDL::BlockIdYOp, ROCDL::BlockIdZOp>, 123 GPUIndexIntrinsicOpLowering<gpu::GridDimOp, ROCDL::GridDimXOp, 124 ROCDL::GridDimYOp, ROCDL::GridDimZOp>, 125 GPUReturnOpLowering>(converter); 126 patterns.add<GPUFuncOpLowering>( 127 converter, /*allocaAddrSpace=*/5, 128 StringAttr::get(&converter.getContext(), 129 ROCDL::ROCDLDialect::getKernelFuncAttrName())); 130 if (Runtime::HIP == runtime) { 131 patterns.add<GPUPrintfOpToHIPLowering>(converter); 132 } else if (Runtime::OpenCL == runtime) { 133 // Use address space = 4 to match the OpenCL definition of printf() 134 patterns.add<GPUPrintfOpToLLVMCallLowering>(converter, /*addressSpace=*/4); 135 } 136 137 patterns.add<OpToFuncCallLowering<math::AbsOp>>(converter, "__ocml_fabs_f32", 138 "__ocml_fabs_f64"); 139 patterns.add<OpToFuncCallLowering<math::AtanOp>>(converter, "__ocml_atan_f32", 140 "__ocml_atan_f64"); 141 patterns.add<OpToFuncCallLowering<math::Atan2Op>>( 142 converter, "__ocml_atan2_f32", "__ocml_atan2_f64"); 143 patterns.add<OpToFuncCallLowering<math::CeilOp>>(converter, "__ocml_ceil_f32", 144 "__ocml_ceil_f64"); 145 patterns.add<OpToFuncCallLowering<math::CosOp>>(converter, "__ocml_cos_f32", 146 "__ocml_cos_f64"); 147 patterns.add<OpToFuncCallLowering<math::ExpOp>>(converter, "__ocml_exp_f32", 148 "__ocml_exp_f64"); 149 patterns.add<OpToFuncCallLowering<math::Exp2Op>>(converter, "__ocml_exp2_f32", 150 "__ocml_exp2_f64"); 151 patterns.add<OpToFuncCallLowering<math::ExpM1Op>>( 152 converter, "__ocml_expm1_f32", "__ocml_expm1_f64"); 153 patterns.add<OpToFuncCallLowering<math::FloorOp>>( 154 converter, "__ocml_floor_f32", "__ocml_floor_f64"); 155 patterns.add<OpToFuncCallLowering<math::LogOp>>(converter, "__ocml_log_f32", 156 "__ocml_log_f64"); 157 patterns.add<OpToFuncCallLowering<math::Log10Op>>( 158 converter, "__ocml_log10_f32", "__ocml_log10_f64"); 159 patterns.add<OpToFuncCallLowering<math::Log1pOp>>( 160 converter, "__ocml_log1p_f32", "__ocml_log1p_f64"); 161 patterns.add<OpToFuncCallLowering<math::Log2Op>>(converter, "__ocml_log2_f32", 162 "__ocml_log2_f64"); 163 patterns.add<OpToFuncCallLowering<math::PowFOp>>(converter, "__ocml_pow_f32", 164 "__ocml_pow_f64"); 165 patterns.add<OpToFuncCallLowering<math::RsqrtOp>>( 166 converter, "__ocml_rsqrt_f32", "__ocml_rsqrt_f64"); 167 patterns.add<OpToFuncCallLowering<math::SinOp>>(converter, "__ocml_sin_f32", 168 "__ocml_sin_f64"); 169 patterns.add<OpToFuncCallLowering<math::SqrtOp>>(converter, "__ocml_sqrt_f32", 170 "__ocml_sqrt_f64"); 171 patterns.add<OpToFuncCallLowering<math::TanhOp>>(converter, "__ocml_tanh_f32", 172 "__ocml_tanh_f64"); 173 } 174 175 std::unique_ptr<OperationPass<gpu::GPUModuleOp>> 176 mlir::createLowerGpuOpsToROCDLOpsPass(unsigned indexBitwidth, 177 gpu::amd::Runtime runtime) { 178 return std::make_unique<LowerGpuOpsToROCDLOpsPass>(indexBitwidth, runtime); 179 } 180