1 //===- LowerGpuOpsToROCDLOps.cpp - MLIR GPU to ROCDL lowering passes ------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements a pass to generate ROCDLIR operations for higher-level 10 // GPU operations. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "mlir/Conversion/GPUToROCDL/GPUToROCDLPass.h" 15 16 #include "mlir/Conversion/ArithmeticToLLVM/ArithmeticToLLVM.h" 17 #include "mlir/Conversion/LLVMCommon/ConversionTarget.h" 18 #include "mlir/Conversion/LLVMCommon/LoweringOptions.h" 19 #include "mlir/Conversion/LLVMCommon/TypeConverter.h" 20 #include "mlir/Conversion/MemRefToLLVM/MemRefToLLVM.h" 21 #include "mlir/Conversion/StandardToLLVM/ConvertStandardToLLVM.h" 22 #include "mlir/Conversion/VectorToLLVM/ConvertVectorToLLVM.h" 23 #include "mlir/Conversion/VectorToROCDL/VectorToROCDL.h" 24 #include "mlir/Dialect/GPU/GPUDialect.h" 25 #include "mlir/Dialect/GPU/Passes.h" 26 #include "mlir/Dialect/LLVMIR/ROCDLDialect.h" 27 #include "mlir/Dialect/Math/IR/Math.h" 28 #include "mlir/Dialect/Vector/VectorOps.h" 29 #include "mlir/Pass/Pass.h" 30 #include "mlir/Transforms/DialectConversion.h" 31 #include "mlir/Transforms/GreedyPatternRewriteDriver.h" 32 #include "llvm/Support/FormatVariadic.h" 33 34 #include "../GPUCommon/GPUOpsLowering.h" 35 #include "../GPUCommon/IndexIntrinsicsOpLowering.h" 36 #include "../GPUCommon/OpToFuncCallLowering.h" 37 #include "../PassDetail.h" 38 39 using namespace mlir; 40 41 namespace { 42 43 /// Import the GPU Ops to ROCDL Patterns. 44 #include "GPUToROCDL.cpp.inc" 45 46 // A pass that replaces all occurrences of GPU device operations with their 47 // corresponding ROCDL equivalent. 48 // 49 // This pass only handles device code and is not meant to be run on GPU host 50 // code. 51 struct LowerGpuOpsToROCDLOpsPass 52 : public ConvertGpuOpsToROCDLOpsBase<LowerGpuOpsToROCDLOpsPass> { 53 LowerGpuOpsToROCDLOpsPass() = default; 54 LowerGpuOpsToROCDLOpsPass(unsigned indexBitwidth) { 55 this->indexBitwidth = indexBitwidth; 56 } 57 58 void runOnOperation() override { 59 gpu::GPUModuleOp m = getOperation(); 60 61 /// Customize the bitwidth used for the device side index computations. 62 LowerToLLVMOptions options( 63 m.getContext(), 64 DataLayout(cast<DataLayoutOpInterface>(m.getOperation()))); 65 options.emitCWrappers = true; 66 if (indexBitwidth != kDeriveIndexBitwidthFromDataLayout) 67 options.overrideIndexBitwidth(indexBitwidth); 68 LLVMTypeConverter converter(m.getContext(), options); 69 70 RewritePatternSet patterns(m.getContext()); 71 RewritePatternSet llvmPatterns(m.getContext()); 72 73 populateGpuRewritePatterns(patterns); 74 (void)applyPatternsAndFoldGreedily(m, std::move(patterns)); 75 76 mlir::arith::populateArithmeticToLLVMConversionPatterns(converter, 77 llvmPatterns); 78 populateVectorToLLVMConversionPatterns(converter, llvmPatterns); 79 populateVectorToROCDLConversionPatterns(converter, llvmPatterns); 80 populateStdToLLVMConversionPatterns(converter, llvmPatterns); 81 populateMemRefToLLVMConversionPatterns(converter, llvmPatterns); 82 populateGpuToROCDLConversionPatterns(converter, llvmPatterns); 83 LLVMConversionTarget target(getContext()); 84 configureGpuToROCDLConversionLegality(target); 85 if (failed(applyPartialConversion(m, target, std::move(llvmPatterns)))) 86 signalPassFailure(); 87 } 88 }; 89 90 } // namespace 91 92 void mlir::configureGpuToROCDLConversionLegality(ConversionTarget &target) { 93 target.addIllegalOp<FuncOp>(); 94 target.addLegalDialect<::mlir::LLVM::LLVMDialect>(); 95 target.addLegalDialect<ROCDL::ROCDLDialect>(); 96 target.addIllegalDialect<gpu::GPUDialect>(); 97 target.addIllegalOp<LLVM::CosOp, LLVM::ExpOp, LLVM::Exp2Op, LLVM::FAbsOp, 98 LLVM::FCeilOp, LLVM::FFloorOp, LLVM::LogOp, LLVM::Log10Op, 99 LLVM::Log2Op, LLVM::PowOp, LLVM::SinOp, LLVM::SqrtOp>(); 100 101 // TODO: Remove once we support replacing non-root ops. 102 target.addLegalOp<gpu::YieldOp, gpu::GPUModuleOp, gpu::ModuleEndOp>(); 103 } 104 105 void mlir::populateGpuToROCDLConversionPatterns(LLVMTypeConverter &converter, 106 RewritePatternSet &patterns) { 107 populateWithGenerated(patterns); 108 patterns 109 .add<GPUIndexIntrinsicOpLowering<gpu::ThreadIdOp, ROCDL::ThreadIdXOp, 110 ROCDL::ThreadIdYOp, ROCDL::ThreadIdZOp>, 111 GPUIndexIntrinsicOpLowering<gpu::BlockDimOp, ROCDL::BlockDimXOp, 112 ROCDL::BlockDimYOp, ROCDL::BlockDimZOp>, 113 GPUIndexIntrinsicOpLowering<gpu::BlockIdOp, ROCDL::BlockIdXOp, 114 ROCDL::BlockIdYOp, ROCDL::BlockIdZOp>, 115 GPUIndexIntrinsicOpLowering<gpu::GridDimOp, ROCDL::GridDimXOp, 116 ROCDL::GridDimYOp, ROCDL::GridDimZOp>, 117 GPUReturnOpLowering>(converter); 118 patterns.add<GPUFuncOpLowering>( 119 converter, /*allocaAddrSpace=*/5, 120 StringAttr::get(&converter.getContext(), 121 ROCDL::ROCDLDialect::getKernelFuncAttrName())); 122 patterns.add<OpToFuncCallLowering<math::AbsOp>>(converter, "__ocml_fabs_f32", 123 "__ocml_fabs_f64"); 124 patterns.add<OpToFuncCallLowering<math::AtanOp>>(converter, "__ocml_atan_f32", 125 "__ocml_atan_f64"); 126 patterns.add<OpToFuncCallLowering<math::Atan2Op>>( 127 converter, "__ocml_atan2_f32", "__ocml_atan2_f64"); 128 patterns.add<OpToFuncCallLowering<math::CeilOp>>(converter, "__ocml_ceil_f32", 129 "__ocml_ceil_f64"); 130 patterns.add<OpToFuncCallLowering<math::CosOp>>(converter, "__ocml_cos_f32", 131 "__ocml_cos_f64"); 132 patterns.add<OpToFuncCallLowering<math::ExpOp>>(converter, "__ocml_exp_f32", 133 "__ocml_exp_f64"); 134 patterns.add<OpToFuncCallLowering<math::Exp2Op>>(converter, "__ocml_exp2_f32", 135 "__ocml_exp2_f64"); 136 patterns.add<OpToFuncCallLowering<math::ExpM1Op>>( 137 converter, "__ocml_expm1_f32", "__ocml_expm1_f64"); 138 patterns.add<OpToFuncCallLowering<math::FloorOp>>( 139 converter, "__ocml_floor_f32", "__ocml_floor_f64"); 140 patterns.add<OpToFuncCallLowering<math::LogOp>>(converter, "__ocml_log_f32", 141 "__ocml_log_f64"); 142 patterns.add<OpToFuncCallLowering<math::Log10Op>>( 143 converter, "__ocml_log10_f32", "__ocml_log10_f64"); 144 patterns.add<OpToFuncCallLowering<math::Log1pOp>>( 145 converter, "__ocml_log1p_f32", "__ocml_log1p_f64"); 146 patterns.add<OpToFuncCallLowering<math::Log2Op>>(converter, "__ocml_log2_f32", 147 "__ocml_log2_f64"); 148 patterns.add<OpToFuncCallLowering<math::PowFOp>>(converter, "__ocml_pow_f32", 149 "__ocml_pow_f64"); 150 patterns.add<OpToFuncCallLowering<math::RsqrtOp>>( 151 converter, "__ocml_rsqrt_f32", "__ocml_rsqrt_f64"); 152 patterns.add<OpToFuncCallLowering<math::SinOp>>(converter, "__ocml_sin_f32", 153 "__ocml_sin_f64"); 154 patterns.add<OpToFuncCallLowering<math::SqrtOp>>(converter, "__ocml_sqrt_f32", 155 "__ocml_sqrt_f64"); 156 patterns.add<OpToFuncCallLowering<math::TanhOp>>(converter, "__ocml_tanh_f32", 157 "__ocml_tanh_f64"); 158 } 159 160 std::unique_ptr<OperationPass<gpu::GPUModuleOp>> 161 mlir::createLowerGpuOpsToROCDLOpsPass(unsigned indexBitwidth) { 162 return std::make_unique<LowerGpuOpsToROCDLOpsPass>(indexBitwidth); 163 } 164