1 //===- LowerGpuOpsToROCDLOps.cpp - MLIR GPU to ROCDL lowering passes ------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements a pass to generate ROCDLIR operations for higher-level 10 // GPU operations. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "mlir/Conversion/ControlFlowToLLVM/ControlFlowToLLVM.h" 15 #include "mlir/Conversion/GPUToROCDL/GPUToROCDLPass.h" 16 17 #include "mlir/Conversion/AMDGPUToROCDL/AMDGPUToROCDL.h" 18 #include "mlir/Conversion/ArithToLLVM/ArithToLLVM.h" 19 #include "mlir/Conversion/FuncToLLVM/ConvertFuncToLLVM.h" 20 #include "mlir/Conversion/LLVMCommon/ConversionTarget.h" 21 #include "mlir/Conversion/LLVMCommon/LoweringOptions.h" 22 #include "mlir/Conversion/LLVMCommon/Pattern.h" 23 #include "mlir/Conversion/LLVMCommon/TypeConverter.h" 24 #include "mlir/Conversion/MemRefToLLVM/MemRefToLLVM.h" 25 #include "mlir/Conversion/VectorToLLVM/ConvertVectorToLLVM.h" 26 #include "mlir/Dialect/ControlFlow/IR/ControlFlow.h" 27 #include "mlir/Dialect/MemRef/IR/MemRef.h" 28 #include "mlir/Dialect/Func/IR/FuncOps.h" 29 #include "mlir/Dialect/GPU/IR/GPUDialect.h" 30 #include "mlir/Dialect/GPU/Transforms/Passes.h" 31 #include "mlir/Dialect/LLVMIR/LLVMDialect.h" 32 #include "mlir/Dialect/LLVMIR/ROCDLDialect.h" 33 #include "mlir/Dialect/Math/IR/Math.h" 34 #include "mlir/Dialect/Vector/IR/VectorOps.h" 35 #include "mlir/IR/BuiltinAttributes.h" 36 #include "mlir/Pass/Pass.h" 37 #include "mlir/Transforms/DialectConversion.h" 38 #include "mlir/Transforms/GreedyPatternRewriteDriver.h" 39 #include "llvm/Support/FormatVariadic.h" 40 41 #include "../GPUCommon/GPUOpsLowering.h" 42 #include "../GPUCommon/IndexIntrinsicsOpLowering.h" 43 #include "../GPUCommon/OpToFuncCallLowering.h" 44 45 namespace mlir { 46 #define GEN_PASS_DEF_CONVERTGPUOPSTOROCDLOPS 47 #include "mlir/Conversion/Passes.h.inc" 48 } // namespace mlir 49 50 using namespace mlir; 51 52 /// Returns true if the given `gpu.func` can be safely called using the bare 53 /// pointer calling convention. 54 static bool canBeCalledWithBarePointers(gpu::GPUFuncOp func) { 55 bool canBeBare = true; 56 for (Type type : func.getArgumentTypes()) 57 if (auto memrefTy = dyn_cast<BaseMemRefType>(type)) 58 canBeBare &= LLVMTypeConverter::canConvertToBarePtr(memrefTy); 59 return canBeBare; 60 } 61 62 namespace { 63 64 /// Import the GPU Ops to ROCDL Patterns. 65 #include "GPUToROCDL.cpp.inc" 66 67 // A pass that replaces all occurrences of GPU device operations with their 68 // corresponding ROCDL equivalent. 69 // 70 // This pass only handles device code and is not meant to be run on GPU host 71 // code. 72 struct LowerGpuOpsToROCDLOpsPass 73 : public impl::ConvertGpuOpsToROCDLOpsBase<LowerGpuOpsToROCDLOpsPass> { 74 LowerGpuOpsToROCDLOpsPass() = default; 75 LowerGpuOpsToROCDLOpsPass(const std::string &chipset, unsigned indexBitwidth, 76 bool useBarePtrCallConv, 77 gpu::amd::Runtime runtime) { 78 if (this->chipset.getNumOccurrences() == 0) 79 this->chipset = chipset; 80 if (this->indexBitwidth.getNumOccurrences() == 0) 81 this->indexBitwidth = indexBitwidth; 82 if (this->useBarePtrCallConv.getNumOccurrences() == 0) 83 this->useBarePtrCallConv = useBarePtrCallConv; 84 if (this->runtime.getNumOccurrences() == 0) 85 this->runtime = runtime; 86 } 87 88 void runOnOperation() override { 89 gpu::GPUModuleOp m = getOperation(); 90 MLIRContext *ctx = m.getContext(); 91 92 // Request C wrapper emission. 93 for (auto func : m.getOps<func::FuncOp>()) { 94 func->setAttr(LLVM::LLVMDialect::getEmitCWrapperAttrName(), 95 UnitAttr::get(ctx)); 96 } 97 98 FailureOr<amdgpu::Chipset> maybeChipset = amdgpu::Chipset::parse(chipset); 99 if (failed(maybeChipset)) { 100 emitError(UnknownLoc::get(ctx), "Invalid chipset name: " + chipset); 101 return signalPassFailure(); 102 } 103 104 /// Customize the bitwidth used for the device side index computations. 105 LowerToLLVMOptions options( 106 ctx, DataLayout(cast<DataLayoutOpInterface>(m.getOperation()))); 107 if (indexBitwidth != kDeriveIndexBitwidthFromDataLayout) 108 options.overrideIndexBitwidth(indexBitwidth); 109 options.useOpaquePointers = useOpaquePointers; 110 111 if (useBarePtrCallConv) { 112 options.useBarePtrCallConv = true; 113 WalkResult canUseBarePointers = 114 m.walk([](gpu::GPUFuncOp func) -> WalkResult { 115 if (canBeCalledWithBarePointers(func)) 116 return WalkResult::advance(); 117 return WalkResult::interrupt(); 118 }); 119 if (canUseBarePointers.wasInterrupted()) { 120 emitError(UnknownLoc::get(ctx), 121 "bare pointer calling convention requires all memrefs to " 122 "have static shape and use the identity map"); 123 return signalPassFailure(); 124 } 125 } 126 127 // Apply in-dialect lowering. In-dialect lowering will replace 128 // ops which need to be lowered further, which is not supported by a 129 // single conversion pass. 130 { 131 RewritePatternSet patterns(ctx); 132 populateGpuRewritePatterns(patterns); 133 (void)applyPatternsAndFoldGreedily(m, std::move(patterns)); 134 } 135 136 LLVMTypeConverter converter(ctx, options); 137 populateGpuMemorySpaceAttributeConversions( 138 converter, [](gpu::AddressSpace space) { 139 switch (space) { 140 case gpu::AddressSpace::Global: 141 return 1; 142 case gpu::AddressSpace::Workgroup: 143 return 3; 144 case gpu::AddressSpace::Private: 145 return 5; 146 } 147 llvm_unreachable("unknown address space enum value"); 148 return 0; 149 }); 150 151 RewritePatternSet llvmPatterns(ctx); 152 153 mlir::arith::populateArithToLLVMConversionPatterns(converter, llvmPatterns); 154 populateAMDGPUToROCDLConversionPatterns(converter, llvmPatterns, 155 *maybeChipset); 156 populateVectorToLLVMConversionPatterns(converter, llvmPatterns); 157 cf::populateControlFlowToLLVMConversionPatterns(converter, llvmPatterns); 158 populateFuncToLLVMConversionPatterns(converter, llvmPatterns); 159 populateFinalizeMemRefToLLVMConversionPatterns(converter, llvmPatterns); 160 populateGpuToROCDLConversionPatterns(converter, llvmPatterns, runtime); 161 LLVMConversionTarget target(getContext()); 162 configureGpuToROCDLConversionLegality(target); 163 if (failed(applyPartialConversion(m, target, std::move(llvmPatterns)))) 164 signalPassFailure(); 165 166 // Manually rewrite known block size attributes so the LLVMIR translation 167 // infrastructure can pick them up. 168 m.walk([ctx](LLVM::LLVMFuncOp op) { 169 if (auto blockSizes = dyn_cast_or_null<DenseI32ArrayAttr>( 170 op->removeAttr(gpu::GPUFuncOp::getKnownBlockSizeAttrName()))) { 171 op->setAttr(ROCDL::ROCDLDialect::getReqdWorkGroupSizeAttrName(), 172 blockSizes); 173 // Also set up the rocdl.flat_work_group_size attribute to prevent 174 // conflicting metadata. 175 uint32_t flatSize = 1; 176 for (uint32_t size : blockSizes.asArrayRef()) { 177 flatSize *= size; 178 } 179 StringAttr flatSizeAttr = 180 StringAttr::get(ctx, Twine(flatSize) + "," + Twine(flatSize)); 181 op->setAttr(ROCDL::ROCDLDialect::getFlatWorkGroupSizeAttrName(), 182 flatSizeAttr); 183 } 184 }); 185 } 186 }; 187 188 } // namespace 189 190 void mlir::configureGpuToROCDLConversionLegality(ConversionTarget &target) { 191 target.addIllegalOp<func::FuncOp>(); 192 target.addLegalDialect<::mlir::LLVM::LLVMDialect>(); 193 target.addLegalDialect<ROCDL::ROCDLDialect>(); 194 target.addIllegalDialect<gpu::GPUDialect>(); 195 target.addIllegalOp<LLVM::CosOp, LLVM::ExpOp, LLVM::Exp2Op, LLVM::FAbsOp, 196 LLVM::FCeilOp, LLVM::FFloorOp, LLVM::LogOp, LLVM::Log10Op, 197 LLVM::Log2Op, LLVM::PowOp, LLVM::SinOp, LLVM::SqrtOp>(); 198 199 // TODO: Remove once we support replacing non-root ops. 200 target.addLegalOp<gpu::YieldOp, gpu::GPUModuleOp, gpu::ModuleEndOp>(); 201 } 202 203 template <typename OpTy> 204 static void populateOpPatterns(LLVMTypeConverter &converter, 205 RewritePatternSet &patterns, StringRef f32Func, 206 StringRef f64Func) { 207 patterns.add<ScalarizeVectorOpLowering<OpTy>>(converter); 208 patterns.add<OpToFuncCallLowering<OpTy>>(converter, f32Func, f64Func); 209 } 210 211 void mlir::populateGpuToROCDLConversionPatterns( 212 LLVMTypeConverter &converter, RewritePatternSet &patterns, 213 mlir::gpu::amd::Runtime runtime) { 214 using mlir::gpu::amd::Runtime; 215 216 populateWithGenerated(patterns); 217 patterns 218 .add<GPUIndexIntrinsicOpLowering<gpu::ThreadIdOp, ROCDL::ThreadIdXOp, 219 ROCDL::ThreadIdYOp, ROCDL::ThreadIdZOp>>( 220 converter, gpu::GPUFuncOp::getKnownBlockSizeAttrName()); 221 patterns.add<GPUIndexIntrinsicOpLowering< 222 gpu::BlockIdOp, ROCDL::BlockIdXOp, ROCDL::BlockIdYOp, ROCDL::BlockIdZOp>>( 223 converter, gpu::GPUFuncOp::getKnownGridSizeAttrName()); 224 patterns 225 .add<GPUIndexIntrinsicOpLowering<gpu::BlockDimOp, ROCDL::BlockDimXOp, 226 ROCDL::BlockDimYOp, ROCDL::BlockDimZOp>, 227 GPUIndexIntrinsicOpLowering<gpu::GridDimOp, ROCDL::GridDimXOp, 228 ROCDL::GridDimYOp, ROCDL::GridDimZOp>, 229 GPUReturnOpLowering>(converter); 230 patterns.add<GPUFuncOpLowering>( 231 converter, 232 /*allocaAddrSpace=*/ROCDL::ROCDLDialect::kPrivateMemoryAddressSpace, 233 /*workgroupAddrSpace=*/ROCDL::ROCDLDialect::kSharedMemoryAddressSpace, 234 StringAttr::get(&converter.getContext(), 235 ROCDL::ROCDLDialect::getKernelFuncAttrName())); 236 if (Runtime::HIP == runtime) { 237 patterns.add<GPUPrintfOpToHIPLowering>(converter); 238 } else if (Runtime::OpenCL == runtime) { 239 // Use address space = 4 to match the OpenCL definition of printf() 240 patterns.add<GPUPrintfOpToLLVMCallLowering>(converter, /*addressSpace=*/4); 241 } 242 243 populateOpPatterns<math::AbsFOp>(converter, patterns, "__ocml_fabs_f32", 244 "__ocml_fabs_f64"); 245 populateOpPatterns<math::AtanOp>(converter, patterns, "__ocml_atan_f32", 246 "__ocml_atan_f64"); 247 populateOpPatterns<math::Atan2Op>(converter, patterns, "__ocml_atan2_f32", 248 "__ocml_atan2_f64"); 249 populateOpPatterns<math::CbrtOp>(converter, patterns, "__ocml_cbrt_f32", 250 "__ocml_cbrt_f64"); 251 populateOpPatterns<math::CeilOp>(converter, patterns, "__ocml_ceil_f32", 252 "__ocml_ceil_f64"); 253 populateOpPatterns<math::CosOp>(converter, patterns, "__ocml_cos_f32", 254 "__ocml_cos_f64"); 255 populateOpPatterns<math::ExpOp>(converter, patterns, "__ocml_exp_f32", 256 "__ocml_exp_f64"); 257 populateOpPatterns<math::Exp2Op>(converter, patterns, "__ocml_exp2_f32", 258 "__ocml_exp2_f64"); 259 populateOpPatterns<math::ExpM1Op>(converter, patterns, "__ocml_expm1_f32", 260 "__ocml_expm1_f64"); 261 populateOpPatterns<math::FloorOp>(converter, patterns, "__ocml_floor_f32", 262 "__ocml_floor_f64"); 263 populateOpPatterns<math::LogOp>(converter, patterns, "__ocml_log_f32", 264 "__ocml_log_f64"); 265 populateOpPatterns<math::Log10Op>(converter, patterns, "__ocml_log10_f32", 266 "__ocml_log10_f64"); 267 populateOpPatterns<math::Log1pOp>(converter, patterns, "__ocml_log1p_f32", 268 "__ocml_log1p_f64"); 269 populateOpPatterns<math::Log2Op>(converter, patterns, "__ocml_log2_f32", 270 "__ocml_log2_f64"); 271 populateOpPatterns<math::PowFOp>(converter, patterns, "__ocml_pow_f32", 272 "__ocml_pow_f64"); 273 populateOpPatterns<math::RsqrtOp>(converter, patterns, "__ocml_rsqrt_f32", 274 "__ocml_rsqrt_f64"); 275 populateOpPatterns<math::SinOp>(converter, patterns, "__ocml_sin_f32", 276 "__ocml_sin_f64"); 277 populateOpPatterns<math::SqrtOp>(converter, patterns, "__ocml_sqrt_f32", 278 "__ocml_sqrt_f64"); 279 populateOpPatterns<math::TanhOp>(converter, patterns, "__ocml_tanh_f32", 280 "__ocml_tanh_f64"); 281 populateOpPatterns<math::TanOp>(converter, patterns, "__ocml_tan_f32", 282 "__ocml_tan_f64"); 283 populateOpPatterns<math::ErfOp>(converter, patterns, "__ocml_erf_f32", 284 "__ocml_erf_f64"); 285 } 286 287 std::unique_ptr<OperationPass<gpu::GPUModuleOp>> 288 mlir::createLowerGpuOpsToROCDLOpsPass(const std::string &chipset, 289 unsigned indexBitwidth, 290 bool useBarePtrCallConv, 291 gpu::amd::Runtime runtime) { 292 return std::make_unique<LowerGpuOpsToROCDLOpsPass>( 293 chipset, indexBitwidth, useBarePtrCallConv, runtime); 294 } 295