1 //===- LowerGpuOpsToROCDLOps.cpp - MLIR GPU to ROCDL lowering passes ------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements a pass to generate ROCDLIR operations for higher-level 10 // GPU operations. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "mlir/Conversion/GPUToROCDL/GPUToROCDLPass.h" 15 16 #include "mlir/Conversion/LLVMCommon/ConversionTarget.h" 17 #include "mlir/Conversion/LLVMCommon/LoweringOptions.h" 18 #include "mlir/Conversion/LLVMCommon/TypeConverter.h" 19 #include "mlir/Conversion/MemRefToLLVM/MemRefToLLVM.h" 20 #include "mlir/Conversion/StandardToLLVM/ConvertStandardToLLVM.h" 21 #include "mlir/Conversion/VectorToLLVM/ConvertVectorToLLVM.h" 22 #include "mlir/Conversion/VectorToROCDL/VectorToROCDL.h" 23 #include "mlir/Dialect/GPU/GPUDialect.h" 24 #include "mlir/Dialect/GPU/Passes.h" 25 #include "mlir/Dialect/LLVMIR/ROCDLDialect.h" 26 #include "mlir/Dialect/Math/IR/Math.h" 27 #include "mlir/Dialect/Vector/VectorOps.h" 28 #include "mlir/Pass/Pass.h" 29 #include "mlir/Transforms/DialectConversion.h" 30 #include "mlir/Transforms/GreedyPatternRewriteDriver.h" 31 #include "llvm/Support/FormatVariadic.h" 32 33 #include "../GPUCommon/GPUOpsLowering.h" 34 #include "../GPUCommon/IndexIntrinsicsOpLowering.h" 35 #include "../GPUCommon/OpToFuncCallLowering.h" 36 #include "../PassDetail.h" 37 38 using namespace mlir; 39 40 namespace { 41 42 /// Import the GPU Ops to ROCDL Patterns. 43 #include "GPUToROCDL.cpp.inc" 44 45 // A pass that replaces all occurrences of GPU device operations with their 46 // corresponding ROCDL equivalent. 47 // 48 // This pass only handles device code and is not meant to be run on GPU host 49 // code. 50 struct LowerGpuOpsToROCDLOpsPass 51 : public ConvertGpuOpsToROCDLOpsBase<LowerGpuOpsToROCDLOpsPass> { 52 LowerGpuOpsToROCDLOpsPass() = default; 53 LowerGpuOpsToROCDLOpsPass(unsigned indexBitwidth) { 54 this->indexBitwidth = indexBitwidth; 55 } 56 57 void runOnOperation() override { 58 gpu::GPUModuleOp m = getOperation(); 59 60 /// Customize the bitwidth used for the device side index computations. 61 LowerToLLVMOptions options( 62 m.getContext(), 63 DataLayout(cast<DataLayoutOpInterface>(m.getOperation()))); 64 options.emitCWrappers = true; 65 if (indexBitwidth != kDeriveIndexBitwidthFromDataLayout) 66 options.overrideIndexBitwidth(indexBitwidth); 67 LLVMTypeConverter converter(m.getContext(), options); 68 69 RewritePatternSet patterns(m.getContext()); 70 RewritePatternSet llvmPatterns(m.getContext()); 71 72 populateGpuRewritePatterns(patterns); 73 (void)applyPatternsAndFoldGreedily(m, std::move(patterns)); 74 75 populateVectorToLLVMConversionPatterns(converter, llvmPatterns); 76 populateVectorToROCDLConversionPatterns(converter, llvmPatterns); 77 populateStdToLLVMConversionPatterns(converter, llvmPatterns); 78 populateMemRefToLLVMConversionPatterns(converter, llvmPatterns); 79 populateGpuToROCDLConversionPatterns(converter, llvmPatterns); 80 LLVMConversionTarget target(getContext()); 81 configureGpuToROCDLConversionLegality(target); 82 if (failed(applyPartialConversion(m, target, std::move(llvmPatterns)))) 83 signalPassFailure(); 84 } 85 }; 86 87 } // anonymous namespace 88 89 void mlir::configureGpuToROCDLConversionLegality(ConversionTarget &target) { 90 target.addIllegalOp<FuncOp>(); 91 target.addLegalDialect<::mlir::LLVM::LLVMDialect>(); 92 target.addLegalDialect<ROCDL::ROCDLDialect>(); 93 target.addIllegalDialect<gpu::GPUDialect>(); 94 target.addIllegalOp<LLVM::CosOp, LLVM::ExpOp, LLVM::Exp2Op, LLVM::FAbsOp, 95 LLVM::FCeilOp, LLVM::FFloorOp, LLVM::LogOp, LLVM::Log10Op, 96 LLVM::Log2Op, LLVM::PowOp, LLVM::SinOp, LLVM::SqrtOp>(); 97 98 // TODO: Remove once we support replacing non-root ops. 99 target.addLegalOp<gpu::YieldOp, gpu::GPUModuleOp, gpu::ModuleEndOp>(); 100 } 101 102 void mlir::populateGpuToROCDLConversionPatterns(LLVMTypeConverter &converter, 103 RewritePatternSet &patterns) { 104 populateWithGenerated(patterns); 105 patterns 106 .add<GPUIndexIntrinsicOpLowering<gpu::ThreadIdOp, ROCDL::ThreadIdXOp, 107 ROCDL::ThreadIdYOp, ROCDL::ThreadIdZOp>, 108 GPUIndexIntrinsicOpLowering<gpu::BlockDimOp, ROCDL::BlockDimXOp, 109 ROCDL::BlockDimYOp, ROCDL::BlockDimZOp>, 110 GPUIndexIntrinsicOpLowering<gpu::BlockIdOp, ROCDL::BlockIdXOp, 111 ROCDL::BlockIdYOp, ROCDL::BlockIdZOp>, 112 GPUIndexIntrinsicOpLowering<gpu::GridDimOp, ROCDL::GridDimXOp, 113 ROCDL::GridDimYOp, ROCDL::GridDimZOp>, 114 GPUReturnOpLowering>(converter); 115 patterns.add<GPUFuncOpLowering>( 116 converter, /*allocaAddrSpace=*/5, 117 Identifier::get(ROCDL::ROCDLDialect::getKernelFuncAttrName(), 118 &converter.getContext())); 119 patterns.add<OpToFuncCallLowering<AbsFOp>>(converter, "__ocml_fabs_f32", 120 "__ocml_fabs_f64"); 121 patterns.add<OpToFuncCallLowering<math::AtanOp>>(converter, "__ocml_atan_f32", 122 "__ocml_atan_f64"); 123 patterns.add<OpToFuncCallLowering<math::Atan2Op>>( 124 converter, "__ocml_atan2_f32", "__ocml_atan2_f64"); 125 patterns.add<OpToFuncCallLowering<CeilFOp>>(converter, "__ocml_ceil_f32", 126 "__ocml_ceil_f64"); 127 patterns.add<OpToFuncCallLowering<math::CosOp>>(converter, "__ocml_cos_f32", 128 "__ocml_cos_f64"); 129 patterns.add<OpToFuncCallLowering<math::ExpOp>>(converter, "__ocml_exp_f32", 130 "__ocml_exp_f64"); 131 patterns.add<OpToFuncCallLowering<math::Exp2Op>>(converter, "__ocml_exp2_f32", 132 "__ocml_exp2_f64"); 133 patterns.add<OpToFuncCallLowering<math::ExpM1Op>>( 134 converter, "__ocml_expm1_f32", "__ocml_expm1_f64"); 135 patterns.add<OpToFuncCallLowering<FloorFOp>>(converter, "__ocml_floor_f32", 136 "__ocml_floor_f64"); 137 patterns.add<OpToFuncCallLowering<math::LogOp>>(converter, "__ocml_log_f32", 138 "__ocml_log_f64"); 139 patterns.add<OpToFuncCallLowering<math::Log10Op>>( 140 converter, "__ocml_log10_f32", "__ocml_log10_f64"); 141 patterns.add<OpToFuncCallLowering<math::Log1pOp>>( 142 converter, "__ocml_log1p_f32", "__ocml_log1p_f64"); 143 patterns.add<OpToFuncCallLowering<math::Log2Op>>(converter, "__ocml_log2_f32", 144 "__ocml_log2_f64"); 145 patterns.add<OpToFuncCallLowering<math::PowFOp>>(converter, "__ocml_pow_f32", 146 "__ocml_pow_f64"); 147 patterns.add<OpToFuncCallLowering<math::RsqrtOp>>( 148 converter, "__ocml_rsqrt_f32", "__ocml_rsqrt_f64"); 149 patterns.add<OpToFuncCallLowering<math::SinOp>>(converter, "__ocml_sin_f32", 150 "__ocml_sin_f64"); 151 patterns.add<OpToFuncCallLowering<math::SqrtOp>>(converter, "__ocml_sqrt_f32", 152 "__ocml_sqrt_f64"); 153 patterns.add<OpToFuncCallLowering<math::TanhOp>>(converter, "__ocml_tanh_f32", 154 "__ocml_tanh_f64"); 155 } 156 157 std::unique_ptr<OperationPass<gpu::GPUModuleOp>> 158 mlir::createLowerGpuOpsToROCDLOpsPass(unsigned indexBitwidth) { 159 return std::make_unique<LowerGpuOpsToROCDLOpsPass>(indexBitwidth); 160 } 161