1 //===-- SnippetGeneratorTest.cpp --------------------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "../Common/AssemblerUtils.h" 10 #include "LlvmState.h" 11 #include "MCInstrDescView.h" 12 #include "PPCInstrInfo.h" 13 #include "ParallelSnippetGenerator.h" 14 #include "RegisterAliasing.h" 15 #include "SerialSnippetGenerator.h" 16 #include "TestBase.h" 17 18 #include <unordered_set> 19 20 namespace llvm { 21 namespace exegesis { 22 namespace { 23 24 using testing::AnyOf; 25 using testing::ElementsAre; 26 using testing::HasSubstr; 27 using testing::SizeIs; 28 29 MATCHER(IsInvalid, "") { return !arg.isValid(); } 30 MATCHER(IsReg, "") { return arg.isReg(); } 31 32 template <typename SnippetGeneratorT> 33 class PPCSnippetGeneratorTest : public PPCTestBase { 34 protected: 35 PPCSnippetGeneratorTest() : Generator(State, SnippetGenerator::Options()) {} 36 37 std::vector<CodeTemplate> checkAndGetCodeTemplates(unsigned Opcode) { 38 randomGenerator().seed(0); // Initialize seed. 39 const Instruction &Instr = State.getIC().getInstr(Opcode); 40 auto CodeTemplateOrError = Generator.generateCodeTemplates( 41 &Instr, State.getRATC().emptyRegisters()); 42 EXPECT_FALSE(CodeTemplateOrError.takeError()); // Valid configuration. 43 return std::move(CodeTemplateOrError.get()); 44 } 45 46 SnippetGeneratorT Generator; 47 }; 48 49 using PPCSerialSnippetGeneratorTest = PPCSnippetGeneratorTest<SerialSnippetGenerator>; 50 51 using PPCParallelSnippetGeneratorTest = 52 PPCSnippetGeneratorTest<ParallelSnippetGenerator>; 53 54 TEST_F(PPCSerialSnippetGeneratorTest, ImplicitSelfDependencyThroughExplicitRegs) { 55 // - ADD8 56 // - Op0 Explicit Def RegClass(G8RC) 57 // - Op1 Explicit Use RegClass(G8RC) 58 // - Op2 Explicit Use RegClass(G8RC) 59 // - Var0 [Op0] 60 // - Var1 [Op1] 61 // - Var2 [Op2] 62 // - hasAliasingRegisters 63 const unsigned Opcode = PPC::ADD8; 64 const auto CodeTemplates = checkAndGetCodeTemplates(Opcode); 65 ASSERT_THAT(CodeTemplates, SizeIs(1)); 66 const auto &CT = CodeTemplates[0]; 67 EXPECT_THAT(CT.Execution, ExecutionMode::SERIAL_VIA_EXPLICIT_REGS); 68 ASSERT_THAT(CT.Instructions, SizeIs(1)); 69 const InstructionTemplate &IT = CT.Instructions[0]; 70 EXPECT_THAT(IT.getOpcode(), Opcode); 71 ASSERT_THAT(IT.getVariableValues(), SizeIs(3)); 72 EXPECT_THAT(IT.getVariableValues(), 73 AnyOf(ElementsAre(IsReg(), IsInvalid(), IsReg()), 74 ElementsAre(IsReg(), IsReg(), IsInvalid()))) 75 << "Op0 is either set to Op1 or to Op2"; 76 } 77 78 TEST_F(PPCSerialSnippetGeneratorTest, ImplicitSelfDependencyThroughTiedRegs) { 79 80 // - RLDIMI 81 // - Op0 Explicit Def RegClass(G8RC) 82 // - Op1 Explicit Use RegClass(G8RC) TiedToOp0 83 // - Op2 Explicit Use RegClass(G8RC) 84 // - Op3 Explicit Use Immediate 85 // - Op4 Explicit Use Immediate 86 // - Var0 [Op0,Op1] 87 // - Var1 [Op2] 88 // - Var2 [Op3] 89 // - Var3 [Op4] 90 // - hasTiedRegisters (execution is always serial) 91 // - hasAliasingRegisters 92 // - RLDIMI 93 const unsigned Opcode = PPC::RLDIMI; 94 const auto CodeTemplates = checkAndGetCodeTemplates(Opcode); 95 ASSERT_THAT(CodeTemplates, SizeIs(1)); 96 const auto &CT = CodeTemplates[0]; 97 EXPECT_THAT(CT.Execution, ExecutionMode::ALWAYS_SERIAL_TIED_REGS_ALIAS); 98 ASSERT_THAT(CT.Instructions, SizeIs(1)); 99 const InstructionTemplate &IT = CT.Instructions[0]; 100 EXPECT_THAT(IT.getOpcode(), Opcode); 101 ASSERT_THAT(IT.getVariableValues(), SizeIs(4)); 102 EXPECT_THAT(IT.getVariableValues()[2], IsInvalid()) << "Operand 1 is not set"; 103 EXPECT_THAT(IT.getVariableValues()[3], IsInvalid()) << "Operand 2 is not set"; 104 } 105 106 TEST_F(PPCParallelSnippetGeneratorTest, MemoryUse) { 107 // - LDX 108 // - Op0 Explicit Def RegClass(G8RC) 109 // - Op1 Explicit Use Memory RegClass(GPRC) 110 // - Op2 Explicit Use Memory RegClass(VSSRC) 111 // - Var0 [Op0] 112 // - Var1 [Op1] 113 // - Var2 [Op2] 114 // - hasMemoryOperands 115 // - hasAliasingRegisters 116 const unsigned Opcode = PPC::LDX; 117 const auto CodeTemplates = checkAndGetCodeTemplates(Opcode); 118 ASSERT_THAT(CodeTemplates, SizeIs(1)); 119 for (const auto &CT : CodeTemplates) { 120 EXPECT_THAT(CT.Info, HasSubstr("instruction has no tied variables")); 121 EXPECT_THAT(CT.Execution, ExecutionMode::UNKNOWN); 122 ASSERT_THAT(CT.Instructions, 123 SizeIs(ParallelSnippetGenerator::kMinNumDifferentAddresses)); 124 const InstructionTemplate &IT = CT.Instructions[0]; 125 EXPECT_THAT(IT.getOpcode(), Opcode); 126 ASSERT_THAT(IT.getVariableValues(), SizeIs(3)); 127 EXPECT_EQ(IT.getVariableValues()[1].getReg(), PPC::X1); 128 EXPECT_EQ(IT.getVariableValues()[2].getReg(), PPC::X13); 129 } 130 } 131 132 } // namespace 133 } // namespace exegesis 134 } // namespace llvm 135