xref: /llvm-project/llvm/unittests/tools/llvm-exegesis/Mips/TargetTest.cpp (revision cf1ba238d4f752133897af1773e85056b1492803)
1 //===-- TargetTest.cpp ------------------------------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "Target.h"
10 
11 #include <cassert>
12 #include <memory>
13 
14 #include "MCTargetDesc/MipsMCTargetDesc.h"
15 #include "llvm/Support/TargetRegistry.h"
16 #include "llvm/Support/TargetSelect.h"
17 #include "gmock/gmock.h"
18 #include "gtest/gtest.h"
19 
20 namespace llvm {
21 namespace exegesis {
22 
23 void InitializeMipsExegesisTarget();
24 
25 namespace {
26 
27 using testing::AllOf;
28 using testing::ElementsAre;
29 using testing::Eq;
30 using testing::Matcher;
31 using testing::Property;
32 
33 Matcher<MCOperand> IsImm(int64_t Value) {
34   return AllOf(Property(&MCOperand::isImm, Eq(true)),
35                Property(&MCOperand::getImm, Eq(Value)));
36 }
37 
38 Matcher<MCOperand> IsReg(unsigned Reg) {
39   return AllOf(Property(&MCOperand::isReg, Eq(true)),
40                Property(&MCOperand::getReg, Eq(Reg)));
41 }
42 
43 Matcher<MCInst> OpcodeIs(unsigned Opcode) {
44   return Property(&MCInst::getOpcode, Eq(Opcode));
45 }
46 
47 Matcher<MCInst> IsLoadLowImm(int64_t Reg, int64_t Value) {
48   return AllOf(OpcodeIs(Mips::ORi),
49                ElementsAre(IsReg(Reg), IsReg(Mips::ZERO), IsImm(Value)));
50 }
51 
52 constexpr const char kTriple[] = "mips-unknown-linux";
53 
54 class MipsTargetTest : public ::testing::Test {
55 protected:
56   MipsTargetTest() : State(kTriple, "mips32", "") {}
57 
58   static void SetUpTestCase() {
59     LLVMInitializeMipsTargetInfo();
60     LLVMInitializeMipsTarget();
61     LLVMInitializeMipsTargetMC();
62     InitializeMipsExegesisTarget();
63   }
64 
65   std::vector<MCInst> setRegTo(unsigned Reg, const APInt &Value) {
66     return State.getExegesisTarget().setRegTo(State.getSubtargetInfo(), Reg,
67                                               Value);
68   }
69 
70   LLVMState State;
71 };
72 
73 TEST_F(MipsTargetTest, SetRegToConstant) {
74   const uint16_t Value = 0xFFFFU;
75   const unsigned Reg = Mips::T0;
76   EXPECT_THAT(setRegTo(Reg, APInt(16, Value)),
77               ElementsAre(IsLoadLowImm(Reg, Value)));
78 }
79 
80 TEST_F(MipsTargetTest, DefaultPfmCounters) {
81   const std::string Expected = "CYCLES";
82   EXPECT_EQ(State.getExegesisTarget().getPfmCounters("").CycleCounter,
83             Expected);
84   EXPECT_EQ(
85       State.getExegesisTarget().getPfmCounters("unknown_cpu").CycleCounter,
86       Expected);
87 }
88 
89 } // namespace
90 } // namespace exegesis
91 } // namespace llvm
92