xref: /llvm-project/llvm/unittests/Target/ARM/MachineInstrTest.cpp (revision 84593f058b97d6470156e68841cfacee48af39a7) 
1 #include "ARMBaseInstrInfo.h"
2 #include "ARMSubtarget.h"
3 #include "ARMTargetMachine.h"
4 #include "llvm/Support/TargetRegistry.h"
5 #include "llvm/Support/TargetSelect.h"
6 #include "llvm/Target/TargetMachine.h"
7 #include "llvm/Target/TargetOptions.h"
8 
9 #include "gtest/gtest.h"
10 
11 using namespace llvm;
12 
13 // Test for instructions that aren't immediately obviously valid within a
14 // tail-predicated loop. This should be marked up in their tablegen
15 // descriptions. Currently we, conservatively, disallow:
16 // - cross beat carries.
17 // - narrowing of results.
18 // - top/bottom operations.
19 // - complex operations.
20 // - horizontal operations.
21 // - byte swapping.
22 // - interleaved memory instructions.
23 // TODO: Add to this list once we can handle them safely.
24 TEST(MachineInstrValidTailPredication, IsCorrect) {
25 
26   using namespace ARM;
27 
28   auto IsValidTPOpcode = [](unsigned Opcode) {
29     switch (Opcode) {
30     default:
31       return false;
32     case MVE_ASRLi:
33     case MVE_ASRLr:
34     case MVE_LSRL:
35     case MVE_SQRSHR:
36     case MVE_SQSHL:
37     case MVE_SRSHR:
38     case MVE_UQRSHL:
39     case MVE_UQSHL:
40     case MVE_URSHR:
41     case MVE_VABDf16:
42     case MVE_VABDf32:
43     case MVE_VABDs16:
44     case MVE_VABDs32:
45     case MVE_VABDs8:
46     case MVE_VABDu16:
47     case MVE_VABDu32:
48     case MVE_VABDu8:
49     case MVE_VABSf16:
50     case MVE_VABSf32:
51     case MVE_VABSs16:
52     case MVE_VABSs32:
53     case MVE_VABSs8:
54     case MVE_VADD_qr_f16:
55     case MVE_VADD_qr_f32:
56     case MVE_VADD_qr_i16:
57     case MVE_VADD_qr_i32:
58     case MVE_VADD_qr_i8:
59     case MVE_VADDf16:
60     case MVE_VADDf32:
61     case MVE_VADDi16:
62     case MVE_VADDi32:
63     case MVE_VADDi8:
64     case MVE_VAND:
65     case MVE_VBIC:
66     case MVE_VBICIZ0v4i32:
67     case MVE_VBICIZ0v8i16:
68     case MVE_VBICIZ16v4i32:
69     case MVE_VBICIZ24v4i32:
70     case MVE_VBICIZ8v4i32:
71     case MVE_VBICIZ8v8i16:
72     case MVE_VBRSR16:
73     case MVE_VBRSR32:
74     case MVE_VBRSR8:
75     case MVE_VCLSs16:
76     case MVE_VCLSs32:
77     case MVE_VCLSs8:
78     case MVE_VCLZs16:
79     case MVE_VCLZs32:
80     case MVE_VCLZs8:
81     case MVE_VCMPf16:
82     case MVE_VCMPf16r:
83     case MVE_VCMPf32:
84     case MVE_VCMPf32r:
85     case MVE_VCMPi16:
86     case MVE_VCMPi16r:
87     case MVE_VCMPi32:
88     case MVE_VCMPi32r:
89     case MVE_VCMPi8:
90     case MVE_VCMPi8r:
91     case MVE_VCMPs16:
92     case MVE_VCMPs16r:
93     case MVE_VCMPs32:
94     case MVE_VCMPs32r:
95     case MVE_VCMPs8:
96     case MVE_VCMPs8r:
97     case MVE_VCMPu16:
98     case MVE_VCMPu16r:
99     case MVE_VCMPu32:
100     case MVE_VCMPu32r:
101     case MVE_VCMPu8:
102     case MVE_VCMPu8r:
103     case MVE_VCTP16:
104     case MVE_VCTP32:
105     case MVE_VCTP64:
106     case MVE_VCTP8:
107     case MVE_VCVTf16s16_fix:
108     case MVE_VCVTf16s16n:
109     case MVE_VCVTf16u16_fix:
110     case MVE_VCVTf16u16n:
111     case MVE_VCVTf32s32_fix:
112     case MVE_VCVTf32s32n:
113     case MVE_VCVTf32u32_fix:
114     case MVE_VCVTf32u32n:
115     case MVE_VCVTs16f16_fix:
116     case MVE_VCVTs16f16a:
117     case MVE_VCVTs16f16m:
118     case MVE_VCVTs16f16n:
119     case MVE_VCVTs16f16p:
120     case MVE_VCVTs16f16z:
121     case MVE_VCVTs32f32_fix:
122     case MVE_VCVTs32f32a:
123     case MVE_VCVTs32f32m:
124     case MVE_VCVTs32f32n:
125     case MVE_VCVTs32f32p:
126     case MVE_VCVTs32f32z:
127     case MVE_VCVTu16f16_fix:
128     case MVE_VCVTu16f16a:
129     case MVE_VCVTu16f16m:
130     case MVE_VCVTu16f16n:
131     case MVE_VCVTu16f16p:
132     case MVE_VCVTu16f16z:
133     case MVE_VCVTu32f32_fix:
134     case MVE_VCVTu32f32a:
135     case MVE_VCVTu32f32m:
136     case MVE_VCVTu32f32n:
137     case MVE_VCVTu32f32p:
138     case MVE_VCVTu32f32z:
139     case MVE_VDDUPu16:
140     case MVE_VDDUPu32:
141     case MVE_VDDUPu8:
142     case MVE_VDUP16:
143     case MVE_VDUP32:
144     case MVE_VDUP8:
145     case MVE_VDWDUPu16:
146     case MVE_VDWDUPu32:
147     case MVE_VDWDUPu8:
148     case MVE_VEOR:
149     case MVE_VFMA_qr_Sf16:
150     case MVE_VFMA_qr_Sf32:
151     case MVE_VFMA_qr_f16:
152     case MVE_VFMA_qr_f32:
153     case MVE_VMLAS_qr_s16:
154     case MVE_VMLAS_qr_s32:
155     case MVE_VMLAS_qr_s8:
156     case MVE_VMLAS_qr_u16:
157     case MVE_VMLAS_qr_u32:
158     case MVE_VMLAS_qr_u8:
159     case MVE_VMLA_qr_s16:
160     case MVE_VMLA_qr_s32:
161     case MVE_VMLA_qr_s8:
162     case MVE_VMLA_qr_u16:
163     case MVE_VMLA_qr_u32:
164     case MVE_VMLA_qr_u8:
165     case MVE_VHADD_qr_s16:
166     case MVE_VHADD_qr_s32:
167     case MVE_VHADD_qr_s8:
168     case MVE_VHADD_qr_u16:
169     case MVE_VHADD_qr_u32:
170     case MVE_VHADD_qr_u8:
171     case MVE_VHADDs16:
172     case MVE_VHADDs32:
173     case MVE_VHADDs8:
174     case MVE_VHADDu16:
175     case MVE_VHADDu32:
176     case MVE_VHADDu8:
177     case MVE_VHSUB_qr_s16:
178     case MVE_VHSUB_qr_s32:
179     case MVE_VHSUB_qr_s8:
180     case MVE_VHSUB_qr_u16:
181     case MVE_VHSUB_qr_u32:
182     case MVE_VHSUB_qr_u8:
183     case MVE_VHSUBs16:
184     case MVE_VHSUBs32:
185     case MVE_VHSUBs8:
186     case MVE_VHSUBu16:
187     case MVE_VHSUBu32:
188     case MVE_VHSUBu8:
189     case MVE_VIDUPu16:
190     case MVE_VIDUPu32:
191     case MVE_VIDUPu8:
192     case MVE_VIWDUPu16:
193     case MVE_VIWDUPu32:
194     case MVE_VIWDUPu8:
195     case MVE_VLDRBS16:
196     case MVE_VLDRBS16_post:
197     case MVE_VLDRBS16_pre:
198     case MVE_VLDRBS16_rq:
199     case MVE_VLDRBS32:
200     case MVE_VLDRBS32_post:
201     case MVE_VLDRBS32_pre:
202     case MVE_VLDRBS32_rq:
203     case MVE_VLDRBU16:
204     case MVE_VLDRBU16_post:
205     case MVE_VLDRBU16_pre:
206     case MVE_VLDRBU16_rq:
207     case MVE_VLDRBU32:
208     case MVE_VLDRBU32_post:
209     case MVE_VLDRBU32_pre:
210     case MVE_VLDRBU32_rq:
211     case MVE_VLDRBU8:
212     case MVE_VLDRBU8_post:
213     case MVE_VLDRBU8_pre:
214     case MVE_VLDRBU8_rq:
215     case MVE_VLDRDU64_qi:
216     case MVE_VLDRDU64_qi_pre:
217     case MVE_VLDRDU64_rq:
218     case MVE_VLDRDU64_rq_u:
219     case MVE_VLDRHS32:
220     case MVE_VLDRHS32_post:
221     case MVE_VLDRHS32_pre:
222     case MVE_VLDRHS32_rq:
223     case MVE_VLDRHS32_rq_u:
224     case MVE_VLDRHU16:
225     case MVE_VLDRHU16_post:
226     case MVE_VLDRHU16_pre:
227     case MVE_VLDRHU16_rq:
228     case MVE_VLDRHU16_rq_u:
229     case MVE_VLDRHU32:
230     case MVE_VLDRHU32_post:
231     case MVE_VLDRHU32_pre:
232     case MVE_VLDRHU32_rq:
233     case MVE_VLDRHU32_rq_u:
234     case MVE_VLDRWU32:
235     case MVE_VLDRWU32_post:
236     case MVE_VLDRWU32_pre:
237     case MVE_VLDRWU32_qi:
238     case MVE_VLDRWU32_qi_pre:
239     case MVE_VLDRWU32_rq:
240     case MVE_VLDRWU32_rq_u:
241     case MVE_VMOVimmf32:
242     case MVE_VMOVimmi16:
243     case MVE_VMOVimmi32:
244     case MVE_VMOVimmi64:
245     case MVE_VMOVimmi8:
246     case MVE_VMUL_qr_f16:
247     case MVE_VMUL_qr_f32:
248     case MVE_VMUL_qr_i16:
249     case MVE_VMUL_qr_i32:
250     case MVE_VMUL_qr_i8:
251     case MVE_VMULf16:
252     case MVE_VMULf32:
253     case MVE_VMULi16:
254     case MVE_VMULi8:
255     case MVE_VMULi32:
256     case MVE_VMVN:
257     case MVE_VMVNimmi16:
258     case MVE_VMVNimmi32:
259     case MVE_VNEGf16:
260     case MVE_VNEGf32:
261     case MVE_VNEGs16:
262     case MVE_VNEGs32:
263     case MVE_VNEGs8:
264     case MVE_VORN:
265     case MVE_VORR:
266     case MVE_VORRIZ0v4i32:
267     case MVE_VORRIZ0v8i16:
268     case MVE_VORRIZ16v4i32:
269     case MVE_VORRIZ24v4i32:
270     case MVE_VORRIZ8v4i32:
271     case MVE_VORRIZ8v8i16:
272     case MVE_VPNOT:
273     case MVE_VPSEL:
274     case MVE_VPST:
275     case MVE_VQABSs16:
276     case MVE_VQABSs32:
277     case MVE_VQABSs8:
278     case MVE_VQADD_qr_s16:
279     case MVE_VQADD_qr_s32:
280     case MVE_VQADD_qr_s8:
281     case MVE_VQADD_qr_u16:
282     case MVE_VQADD_qr_u32:
283     case MVE_VQADD_qr_u8:
284     case MVE_VQADDs16:
285     case MVE_VQADDs32:
286     case MVE_VQADDs8:
287     case MVE_VQADDu16:
288     case MVE_VQADDu32:
289     case MVE_VQADDu8:
290     case MVE_VQNEGs16:
291     case MVE_VQNEGs32:
292     case MVE_VQNEGs8:
293     case MVE_VQRSHL_by_vecs16:
294     case MVE_VQRSHL_by_vecs32:
295     case MVE_VQRSHL_by_vecs8:
296     case MVE_VQRSHL_by_vecu16:
297     case MVE_VQRSHL_by_vecu32:
298     case MVE_VQRSHL_by_vecu8:
299     case MVE_VQRSHL_qrs16:
300     case MVE_VQRSHL_qrs32:
301     case MVE_VQRSHL_qrs8:
302     case MVE_VQRSHL_qru16:
303     case MVE_VQRSHL_qru8:
304     case MVE_VQRSHL_qru32:
305     case MVE_VQSHLU_imms16:
306     case MVE_VQSHLU_imms32:
307     case MVE_VQSHLU_imms8:
308     case MVE_VQSHLimms16:
309     case MVE_VQSHLimms32:
310     case MVE_VQSHLimms8:
311     case MVE_VQSHLimmu16:
312     case MVE_VQSHLimmu32:
313     case MVE_VQSHLimmu8:
314     case MVE_VQSHL_by_vecs16:
315     case MVE_VQSHL_by_vecs32:
316     case MVE_VQSHL_by_vecs8:
317     case MVE_VQSHL_by_vecu16:
318     case MVE_VQSHL_by_vecu32:
319     case MVE_VQSHL_by_vecu8:
320     case MVE_VQSHL_qrs16:
321     case MVE_VQSHL_qrs32:
322     case MVE_VQSHL_qrs8:
323     case MVE_VQSHL_qru16:
324     case MVE_VQSHL_qru32:
325     case MVE_VQSHL_qru8:
326     case MVE_VQSUB_qr_s16:
327     case MVE_VQSUB_qr_s32:
328     case MVE_VQSUB_qr_s8:
329     case MVE_VQSUB_qr_u16:
330     case MVE_VQSUB_qr_u32:
331     case MVE_VQSUB_qr_u8:
332     case MVE_VQSUBs16:
333     case MVE_VQSUBs32:
334     case MVE_VQSUBs8:
335     case MVE_VQSUBu16:
336     case MVE_VQSUBu32:
337     case MVE_VQSUBu8:
338     case MVE_VRHADDs16:
339     case MVE_VRHADDs32:
340     case MVE_VRHADDs8:
341     case MVE_VRHADDu16:
342     case MVE_VRHADDu32:
343     case MVE_VRHADDu8:
344     case MVE_VRINTf16A:
345     case MVE_VRINTf16M:
346     case MVE_VRINTf16N:
347     case MVE_VRINTf16P:
348     case MVE_VRINTf16X:
349     case MVE_VRINTf16Z:
350     case MVE_VRINTf32A:
351     case MVE_VRINTf32M:
352     case MVE_VRINTf32N:
353     case MVE_VRINTf32P:
354     case MVE_VRINTf32X:
355     case MVE_VRINTf32Z:
356     case MVE_VRSHL_by_vecs16:
357     case MVE_VRSHL_by_vecs32:
358     case MVE_VRSHL_by_vecs8:
359     case MVE_VRSHL_by_vecu16:
360     case MVE_VRSHL_by_vecu32:
361     case MVE_VRSHL_by_vecu8:
362     case MVE_VRSHL_qrs16:
363     case MVE_VRSHL_qrs32:
364     case MVE_VRSHL_qrs8:
365     case MVE_VRSHL_qru16:
366     case MVE_VRSHL_qru32:
367     case MVE_VRSHL_qru8:
368     case MVE_VRSHR_imms16:
369     case MVE_VRSHR_imms32:
370     case MVE_VRSHR_imms8:
371     case MVE_VRSHR_immu16:
372     case MVE_VRSHR_immu32:
373     case MVE_VRSHR_immu8:
374     case MVE_VSHL_by_vecs16:
375     case MVE_VSHL_by_vecs32:
376     case MVE_VSHL_by_vecs8:
377     case MVE_VSHL_by_vecu16:
378     case MVE_VSHL_by_vecu32:
379     case MVE_VSHL_by_vecu8:
380     case MVE_VSHL_immi16:
381     case MVE_VSHL_immi32:
382     case MVE_VSHL_immi8:
383     case MVE_VSHL_qrs16:
384     case MVE_VSHL_qrs32:
385     case MVE_VSHL_qrs8:
386     case MVE_VSHL_qru16:
387     case MVE_VSHL_qru32:
388     case MVE_VSHL_qru8:
389     case MVE_VSHR_imms16:
390     case MVE_VSHR_imms32:
391     case MVE_VSHR_imms8:
392     case MVE_VSHR_immu16:
393     case MVE_VSHR_immu32:
394     case MVE_VSHR_immu8:
395     case MVE_VSLIimm16:
396     case MVE_VSLIimm32:
397     case MVE_VSLIimm8:
398     case MVE_VSRIimm16:
399     case MVE_VSRIimm32:
400     case MVE_VSRIimm8:
401     case MVE_VSTRB16:
402     case MVE_VSTRB16_post:
403     case MVE_VSTRB16_pre:
404     case MVE_VSTRB16_rq:
405     case MVE_VSTRB32:
406     case MVE_VSTRB32_post:
407     case MVE_VSTRB32_pre:
408     case MVE_VSTRB32_rq:
409     case MVE_VSTRB8_rq:
410     case MVE_VSTRBU8:
411     case MVE_VSTRBU8_post:
412     case MVE_VSTRBU8_pre:
413     case MVE_VSTRD64_qi:
414     case MVE_VSTRD64_qi_pre:
415     case MVE_VSTRD64_rq:
416     case MVE_VSTRD64_rq_u:
417     case MVE_VSTRH16_rq:
418     case MVE_VSTRH16_rq_u:
419     case MVE_VSTRH32:
420     case MVE_VSTRH32_post:
421     case MVE_VSTRH32_pre:
422     case MVE_VSTRH32_rq:
423     case MVE_VSTRH32_rq_u:
424     case MVE_VSTRHU16:
425     case MVE_VSTRHU16_post:
426     case MVE_VSTRHU16_pre:
427     case MVE_VSTRW32_qi:
428     case MVE_VSTRW32_qi_pre:
429     case MVE_VSTRW32_rq:
430     case MVE_VSTRW32_rq_u:
431     case MVE_VSTRWU32:
432     case MVE_VSTRWU32_post:
433     case MVE_VSTRWU32_pre:
434     case MVE_VSUB_qr_f16:
435     case MVE_VSUB_qr_f32:
436     case MVE_VSUB_qr_i16:
437     case MVE_VSUB_qr_i32:
438     case MVE_VSUB_qr_i8:
439     case MVE_VSUBf16:
440     case MVE_VSUBf32:
441     case MVE_VSUBi16:
442     case MVE_VSUBi32:
443     case MVE_VSUBi8:
444       return true;
445     }
446   };
447 
448   LLVMInitializeARMTargetInfo();
449   LLVMInitializeARMTarget();
450   LLVMInitializeARMTargetMC();
451 
452   auto TT(Triple::normalize("thumbv8.1m.main-arm-none-eabi"));
453   std::string Error;
454   const Target *T = TargetRegistry::lookupTarget(TT, Error);
455   if (!T) {
456     dbgs() << Error;
457     return;
458   }
459 
460   TargetOptions Options;
461   auto TM = std::unique_ptr<LLVMTargetMachine>(
462     static_cast<LLVMTargetMachine*>(
463       T->createTargetMachine(TT, "generic", "", Options, None, None,
464                              CodeGenOpt::Default)));
465   ARMSubtarget ST(TM->getTargetTriple(), TM->getTargetCPU(),
466                   TM->getTargetFeatureString(),
467                   *static_cast<const ARMBaseTargetMachine*>(TM.get()), false);
468   const ARMBaseInstrInfo *TII = ST.getInstrInfo();
469   auto MII = TM->getMCInstrInfo();
470 
471   for (unsigned i = 0; i < ARM::INSTRUCTION_LIST_END; ++i) {
472     const MCInstrDesc &Desc = TII->get(i);
473 
474     for (auto &Op : Desc.operands()) {
475       // Only check instructions that access the MQPR regs.
476       if ((Op.OperandType & MCOI::OPERAND_REGISTER) == 0 ||
477           Op.RegClass != ARM::MQPRRegClassID)
478         continue;
479 
480       uint64_t Flags = MII->get(i).TSFlags;
481       bool Valid = (Flags & ARMII::ValidForTailPredication) != 0;
482       ASSERT_EQ(IsValidTPOpcode(i), Valid)
483                 << MII->getName(i)
484                 << ": mismatched expectation for tail-predicated safety\n";
485       break;
486     }
487   }
488 }
489