xref: /llvm-project/llvm/unittests/Target/ARM/MachineInstrTest.cpp (revision 77e30758ddfc3b8168493f9233c63c8849145082) 
1 #include "ARMBaseInstrInfo.h"
2 #include "ARMSubtarget.h"
3 #include "ARMTargetMachine.h"
4 #include "llvm/Support/TargetRegistry.h"
5 #include "llvm/Support/TargetSelect.h"
6 #include "llvm/Target/TargetMachine.h"
7 #include "llvm/Target/TargetOptions.h"
8 
9 #include "gtest/gtest.h"
10 
11 using namespace llvm;
12 
13 // Test for instructions that aren't immediately obviously valid within a
14 // tail-predicated loop. This should be marked up in their tablegen
15 // descriptions. Currently we, conservatively, disallow:
16 // - cross beat carries.
17 // - narrowing of results.
18 // - complex operations.
19 // - horizontal operations.
20 // - byte swapping.
21 // - interleaved memory instructions.
22 // TODO: Add to this list once we can handle them safely.
23 TEST(MachineInstrValidTailPredication, IsCorrect) {
24 
25   using namespace ARM;
26 
27   auto IsValidTPOpcode = [](unsigned Opcode) {
28     switch (Opcode) {
29     default:
30       return false;
31     case MVE_ASRLi:
32     case MVE_ASRLr:
33     case MVE_LSRL:
34     case MVE_SQRSHR:
35     case MVE_SQSHL:
36     case MVE_SRSHR:
37     case MVE_UQRSHL:
38     case MVE_UQSHL:
39     case MVE_URSHR:
40     case MVE_VABDf16:
41     case MVE_VABDf32:
42     case MVE_VABDs16:
43     case MVE_VABDs32:
44     case MVE_VABDs8:
45     case MVE_VABDu16:
46     case MVE_VABDu32:
47     case MVE_VABDu8:
48     case MVE_VABSf16:
49     case MVE_VABSf32:
50     case MVE_VABSs16:
51     case MVE_VABSs32:
52     case MVE_VABSs8:
53     case MVE_VADD_qr_f16:
54     case MVE_VADD_qr_f32:
55     case MVE_VADD_qr_i16:
56     case MVE_VADD_qr_i32:
57     case MVE_VADD_qr_i8:
58     case MVE_VADDf16:
59     case MVE_VADDf32:
60     case MVE_VADDi16:
61     case MVE_VADDi32:
62     case MVE_VADDi8:
63     case MVE_VAND:
64     case MVE_VBIC:
65     case MVE_VBICimmi16:
66     case MVE_VBICimmi32:
67     case MVE_VBRSR16:
68     case MVE_VBRSR32:
69     case MVE_VBRSR8:
70     case MVE_VCLSs16:
71     case MVE_VCLSs32:
72     case MVE_VCLSs8:
73     case MVE_VCLZs16:
74     case MVE_VCLZs32:
75     case MVE_VCLZs8:
76     case MVE_VCMPf16:
77     case MVE_VCMPf16r:
78     case MVE_VCMPf32:
79     case MVE_VCMPf32r:
80     case MVE_VCMPi16:
81     case MVE_VCMPi16r:
82     case MVE_VCMPi32:
83     case MVE_VCMPi32r:
84     case MVE_VCMPi8:
85     case MVE_VCMPi8r:
86     case MVE_VCMPs16:
87     case MVE_VCMPs16r:
88     case MVE_VCMPs32:
89     case MVE_VCMPs32r:
90     case MVE_VCMPs8:
91     case MVE_VCMPs8r:
92     case MVE_VCMPu16:
93     case MVE_VCMPu16r:
94     case MVE_VCMPu32:
95     case MVE_VCMPu32r:
96     case MVE_VCMPu8:
97     case MVE_VCMPu8r:
98     case MVE_VCTP16:
99     case MVE_VCTP32:
100     case MVE_VCTP64:
101     case MVE_VCTP8:
102     case MVE_VCVTf16s16_fix:
103     case MVE_VCVTf16s16n:
104     case MVE_VCVTf16u16_fix:
105     case MVE_VCVTf16u16n:
106     case MVE_VCVTf32s32_fix:
107     case MVE_VCVTf32s32n:
108     case MVE_VCVTf32u32_fix:
109     case MVE_VCVTf32u32n:
110     case MVE_VCVTs16f16_fix:
111     case MVE_VCVTs16f16a:
112     case MVE_VCVTs16f16m:
113     case MVE_VCVTs16f16n:
114     case MVE_VCVTs16f16p:
115     case MVE_VCVTs16f16z:
116     case MVE_VCVTs32f32_fix:
117     case MVE_VCVTs32f32a:
118     case MVE_VCVTs32f32m:
119     case MVE_VCVTs32f32n:
120     case MVE_VCVTs32f32p:
121     case MVE_VCVTs32f32z:
122     case MVE_VCVTu16f16_fix:
123     case MVE_VCVTu16f16a:
124     case MVE_VCVTu16f16m:
125     case MVE_VCVTu16f16n:
126     case MVE_VCVTu16f16p:
127     case MVE_VCVTu16f16z:
128     case MVE_VCVTu32f32_fix:
129     case MVE_VCVTu32f32a:
130     case MVE_VCVTu32f32m:
131     case MVE_VCVTu32f32n:
132     case MVE_VCVTu32f32p:
133     case MVE_VCVTu32f32z:
134     case MVE_VDDUPu16:
135     case MVE_VDDUPu32:
136     case MVE_VDDUPu8:
137     case MVE_VDUP16:
138     case MVE_VDUP32:
139     case MVE_VDUP8:
140     case MVE_VDWDUPu16:
141     case MVE_VDWDUPu32:
142     case MVE_VDWDUPu8:
143     case MVE_VEOR:
144     case MVE_VFMA_qr_Sf16:
145     case MVE_VFMA_qr_Sf32:
146     case MVE_VFMA_qr_f16:
147     case MVE_VFMA_qr_f32:
148     case MVE_VMAXAs16:
149     case MVE_VMAXAs32:
150     case MVE_VMAXAs8:
151     case MVE_VMAXs16:
152     case MVE_VMAXs32:
153     case MVE_VMAXs8:
154     case MVE_VMAXu16:
155     case MVE_VMAXu32:
156     case MVE_VMAXu8:
157     case MVE_VMINAs16:
158     case MVE_VMINAs32:
159     case MVE_VMINAs8:
160     case MVE_VMINs16:
161     case MVE_VMINs32:
162     case MVE_VMINs8:
163     case MVE_VMINu16:
164     case MVE_VMINu32:
165     case MVE_VMINu8:
166     case MVE_VMLAS_qr_s16:
167     case MVE_VMLAS_qr_s32:
168     case MVE_VMLAS_qr_s8:
169     case MVE_VMLAS_qr_u16:
170     case MVE_VMLAS_qr_u32:
171     case MVE_VMLAS_qr_u8:
172     case MVE_VMLA_qr_s16:
173     case MVE_VMLA_qr_s32:
174     case MVE_VMLA_qr_s8:
175     case MVE_VMLA_qr_u16:
176     case MVE_VMLA_qr_u32:
177     case MVE_VMLA_qr_u8:
178     case MVE_VHADD_qr_s16:
179     case MVE_VHADD_qr_s32:
180     case MVE_VHADD_qr_s8:
181     case MVE_VHADD_qr_u16:
182     case MVE_VHADD_qr_u32:
183     case MVE_VHADD_qr_u8:
184     case MVE_VHADDs16:
185     case MVE_VHADDs32:
186     case MVE_VHADDs8:
187     case MVE_VHADDu16:
188     case MVE_VHADDu32:
189     case MVE_VHADDu8:
190     case MVE_VHSUB_qr_s16:
191     case MVE_VHSUB_qr_s32:
192     case MVE_VHSUB_qr_s8:
193     case MVE_VHSUB_qr_u16:
194     case MVE_VHSUB_qr_u32:
195     case MVE_VHSUB_qr_u8:
196     case MVE_VHSUBs16:
197     case MVE_VHSUBs32:
198     case MVE_VHSUBs8:
199     case MVE_VHSUBu16:
200     case MVE_VHSUBu32:
201     case MVE_VHSUBu8:
202     case MVE_VIDUPu16:
203     case MVE_VIDUPu32:
204     case MVE_VIDUPu8:
205     case MVE_VIWDUPu16:
206     case MVE_VIWDUPu32:
207     case MVE_VIWDUPu8:
208     case MVE_VLDRBS16:
209     case MVE_VLDRBS16_post:
210     case MVE_VLDRBS16_pre:
211     case MVE_VLDRBS16_rq:
212     case MVE_VLDRBS32:
213     case MVE_VLDRBS32_post:
214     case MVE_VLDRBS32_pre:
215     case MVE_VLDRBS32_rq:
216     case MVE_VLDRBU16:
217     case MVE_VLDRBU16_post:
218     case MVE_VLDRBU16_pre:
219     case MVE_VLDRBU16_rq:
220     case MVE_VLDRBU32:
221     case MVE_VLDRBU32_post:
222     case MVE_VLDRBU32_pre:
223     case MVE_VLDRBU32_rq:
224     case MVE_VLDRBU8:
225     case MVE_VLDRBU8_post:
226     case MVE_VLDRBU8_pre:
227     case MVE_VLDRBU8_rq:
228     case MVE_VLDRDU64_qi:
229     case MVE_VLDRDU64_qi_pre:
230     case MVE_VLDRDU64_rq:
231     case MVE_VLDRDU64_rq_u:
232     case MVE_VLDRHS32:
233     case MVE_VLDRHS32_post:
234     case MVE_VLDRHS32_pre:
235     case MVE_VLDRHS32_rq:
236     case MVE_VLDRHS32_rq_u:
237     case MVE_VLDRHU16:
238     case MVE_VLDRHU16_post:
239     case MVE_VLDRHU16_pre:
240     case MVE_VLDRHU16_rq:
241     case MVE_VLDRHU16_rq_u:
242     case MVE_VLDRHU32:
243     case MVE_VLDRHU32_post:
244     case MVE_VLDRHU32_pre:
245     case MVE_VLDRHU32_rq:
246     case MVE_VLDRHU32_rq_u:
247     case MVE_VLDRWU32:
248     case MVE_VLDRWU32_post:
249     case MVE_VLDRWU32_pre:
250     case MVE_VLDRWU32_qi:
251     case MVE_VLDRWU32_qi_pre:
252     case MVE_VLDRWU32_rq:
253     case MVE_VLDRWU32_rq_u:
254     case MVE_VMOVimmf32:
255     case MVE_VMOVimmi16:
256     case MVE_VMOVimmi32:
257     case MVE_VMOVimmi64:
258     case MVE_VMOVimmi8:
259     case MVE_VMULLBp16:
260     case MVE_VMULLBp8:
261     case MVE_VMULLBs16:
262     case MVE_VMULLBs32:
263     case MVE_VMULLBs8:
264     case MVE_VMULLBu16:
265     case MVE_VMULLBu32:
266     case MVE_VMULLBu8:
267     case MVE_VMULLTp16:
268     case MVE_VMULLTp8:
269     case MVE_VMULLTs16:
270     case MVE_VMULLTs32:
271     case MVE_VMULLTs8:
272     case MVE_VMULLTu16:
273     case MVE_VMULLTu32:
274     case MVE_VMULLTu8:
275     case MVE_VMUL_qr_f16:
276     case MVE_VMUL_qr_f32:
277     case MVE_VMUL_qr_i16:
278     case MVE_VMUL_qr_i32:
279     case MVE_VMUL_qr_i8:
280     case MVE_VMULf16:
281     case MVE_VMULf32:
282     case MVE_VMULi16:
283     case MVE_VMULi8:
284     case MVE_VMULi32:
285     case MVE_VMVN:
286     case MVE_VMVNimmi16:
287     case MVE_VMVNimmi32:
288     case MVE_VNEGf16:
289     case MVE_VNEGf32:
290     case MVE_VNEGs16:
291     case MVE_VNEGs32:
292     case MVE_VNEGs8:
293     case MVE_VORN:
294     case MVE_VORR:
295     case MVE_VORRimmi16:
296     case MVE_VORRimmi32:
297     case MVE_VPST:
298     case MVE_VQABSs16:
299     case MVE_VQABSs32:
300     case MVE_VQABSs8:
301     case MVE_VQADD_qr_s16:
302     case MVE_VQADD_qr_s32:
303     case MVE_VQADD_qr_s8:
304     case MVE_VQADD_qr_u16:
305     case MVE_VQADD_qr_u32:
306     case MVE_VQADD_qr_u8:
307     case MVE_VQADDs16:
308     case MVE_VQADDs32:
309     case MVE_VQADDs8:
310     case MVE_VQADDu16:
311     case MVE_VQADDu32:
312     case MVE_VQADDu8:
313     case MVE_VQDMULL_qr_s16bh:
314     case MVE_VQDMULL_qr_s16th:
315     case MVE_VQDMULL_qr_s32bh:
316     case MVE_VQDMULL_qr_s32th:
317     case MVE_VQDMULLs16bh:
318     case MVE_VQDMULLs16th:
319     case MVE_VQDMULLs32bh:
320     case MVE_VQDMULLs32th:
321     case MVE_VQNEGs16:
322     case MVE_VQNEGs32:
323     case MVE_VQNEGs8:
324     case MVE_VQRSHL_by_vecs16:
325     case MVE_VQRSHL_by_vecs32:
326     case MVE_VQRSHL_by_vecs8:
327     case MVE_VQRSHL_by_vecu16:
328     case MVE_VQRSHL_by_vecu32:
329     case MVE_VQRSHL_by_vecu8:
330     case MVE_VQRSHL_qrs16:
331     case MVE_VQRSHL_qrs32:
332     case MVE_VQRSHL_qrs8:
333     case MVE_VQRSHL_qru16:
334     case MVE_VQRSHL_qru8:
335     case MVE_VQRSHL_qru32:
336     case MVE_VQSHLU_imms16:
337     case MVE_VQSHLU_imms32:
338     case MVE_VQSHLU_imms8:
339     case MVE_VQSHLimms16:
340     case MVE_VQSHLimms32:
341     case MVE_VQSHLimms8:
342     case MVE_VQSHLimmu16:
343     case MVE_VQSHLimmu32:
344     case MVE_VQSHLimmu8:
345     case MVE_VQSHL_by_vecs16:
346     case MVE_VQSHL_by_vecs32:
347     case MVE_VQSHL_by_vecs8:
348     case MVE_VQSHL_by_vecu16:
349     case MVE_VQSHL_by_vecu32:
350     case MVE_VQSHL_by_vecu8:
351     case MVE_VQSHL_qrs16:
352     case MVE_VQSHL_qrs32:
353     case MVE_VQSHL_qrs8:
354     case MVE_VQSHL_qru16:
355     case MVE_VQSHL_qru32:
356     case MVE_VQSHL_qru8:
357     case MVE_VQRSHRNbhs16:
358     case MVE_VQRSHRNbhs32:
359     case MVE_VQRSHRNbhu16:
360     case MVE_VQRSHRNbhu32:
361     case MVE_VQRSHRNths16:
362     case MVE_VQRSHRNths32:
363     case MVE_VQRSHRNthu16:
364     case MVE_VQRSHRNthu32:
365     case MVE_VQRSHRUNs16bh:
366     case MVE_VQRSHRUNs16th:
367     case MVE_VQRSHRUNs32bh:
368     case MVE_VQRSHRUNs32th:
369     case MVE_VQSHRNbhs16:
370     case MVE_VQSHRNbhs32:
371     case MVE_VQSHRNbhu16:
372     case MVE_VQSHRNbhu32:
373     case MVE_VQSHRNths16:
374     case MVE_VQSHRNths32:
375     case MVE_VQSHRNthu16:
376     case MVE_VQSHRNthu32:
377     case MVE_VQSHRUNs16bh:
378     case MVE_VQSHRUNs16th:
379     case MVE_VQSHRUNs32bh:
380     case MVE_VQSHRUNs32th:
381     case MVE_VQSUB_qr_s16:
382     case MVE_VQSUB_qr_s32:
383     case MVE_VQSUB_qr_s8:
384     case MVE_VQSUB_qr_u16:
385     case MVE_VQSUB_qr_u32:
386     case MVE_VQSUB_qr_u8:
387     case MVE_VQSUBs16:
388     case MVE_VQSUBs32:
389     case MVE_VQSUBs8:
390     case MVE_VQSUBu16:
391     case MVE_VQSUBu32:
392     case MVE_VQSUBu8:
393     case MVE_VRHADDs16:
394     case MVE_VRHADDs32:
395     case MVE_VRHADDs8:
396     case MVE_VRHADDu16:
397     case MVE_VRHADDu32:
398     case MVE_VRHADDu8:
399     case MVE_VRINTf16A:
400     case MVE_VRINTf16M:
401     case MVE_VRINTf16N:
402     case MVE_VRINTf16P:
403     case MVE_VRINTf16X:
404     case MVE_VRINTf16Z:
405     case MVE_VRINTf32A:
406     case MVE_VRINTf32M:
407     case MVE_VRINTf32N:
408     case MVE_VRINTf32P:
409     case MVE_VRINTf32X:
410     case MVE_VRINTf32Z:
411     case MVE_VRSHL_by_vecs16:
412     case MVE_VRSHL_by_vecs32:
413     case MVE_VRSHL_by_vecs8:
414     case MVE_VRSHL_by_vecu16:
415     case MVE_VRSHL_by_vecu32:
416     case MVE_VRSHL_by_vecu8:
417     case MVE_VRSHL_qrs16:
418     case MVE_VRSHL_qrs32:
419     case MVE_VRSHL_qrs8:
420     case MVE_VRSHL_qru16:
421     case MVE_VRSHL_qru32:
422     case MVE_VRSHL_qru8:
423     case MVE_VRSHR_imms16:
424     case MVE_VRSHR_imms32:
425     case MVE_VRSHR_imms8:
426     case MVE_VRSHR_immu16:
427     case MVE_VRSHR_immu32:
428     case MVE_VRSHR_immu8:
429     case MVE_VRSHRNi16bh:
430     case MVE_VRSHRNi16th:
431     case MVE_VRSHRNi32bh:
432     case MVE_VRSHRNi32th:
433     case MVE_VSHL_by_vecs16:
434     case MVE_VSHL_by_vecs32:
435     case MVE_VSHL_by_vecs8:
436     case MVE_VSHL_by_vecu16:
437     case MVE_VSHL_by_vecu32:
438     case MVE_VSHL_by_vecu8:
439     case MVE_VSHL_immi16:
440     case MVE_VSHL_immi32:
441     case MVE_VSHL_immi8:
442     case MVE_VSHL_qrs16:
443     case MVE_VSHL_qrs32:
444     case MVE_VSHL_qrs8:
445     case MVE_VSHL_qru16:
446     case MVE_VSHL_qru32:
447     case MVE_VSHL_qru8:
448     case MVE_VSHR_imms16:
449     case MVE_VSHR_imms32:
450     case MVE_VSHR_imms8:
451     case MVE_VSHR_immu16:
452     case MVE_VSHR_immu32:
453     case MVE_VSHR_immu8:
454     case MVE_VSHRNi16bh:
455     case MVE_VSHRNi16th:
456     case MVE_VSHRNi32bh:
457     case MVE_VSHRNi32th:
458     case MVE_VSLIimm16:
459     case MVE_VSLIimm32:
460     case MVE_VSLIimm8:
461     case MVE_VSRIimm16:
462     case MVE_VSRIimm32:
463     case MVE_VSRIimm8:
464     case MVE_VSTRB16:
465     case MVE_VSTRB16_post:
466     case MVE_VSTRB16_pre:
467     case MVE_VSTRB16_rq:
468     case MVE_VSTRB32:
469     case MVE_VSTRB32_post:
470     case MVE_VSTRB32_pre:
471     case MVE_VSTRB32_rq:
472     case MVE_VSTRB8_rq:
473     case MVE_VSTRBU8:
474     case MVE_VSTRBU8_post:
475     case MVE_VSTRBU8_pre:
476     case MVE_VSTRD64_qi:
477     case MVE_VSTRD64_qi_pre:
478     case MVE_VSTRD64_rq:
479     case MVE_VSTRD64_rq_u:
480     case MVE_VSTRH16_rq:
481     case MVE_VSTRH16_rq_u:
482     case MVE_VSTRH32:
483     case MVE_VSTRH32_post:
484     case MVE_VSTRH32_pre:
485     case MVE_VSTRH32_rq:
486     case MVE_VSTRH32_rq_u:
487     case MVE_VSTRHU16:
488     case MVE_VSTRHU16_post:
489     case MVE_VSTRHU16_pre:
490     case MVE_VSTRW32_qi:
491     case MVE_VSTRW32_qi_pre:
492     case MVE_VSTRW32_rq:
493     case MVE_VSTRW32_rq_u:
494     case MVE_VSTRWU32:
495     case MVE_VSTRWU32_post:
496     case MVE_VSTRWU32_pre:
497     case MVE_VSUB_qr_f16:
498     case MVE_VSUB_qr_f32:
499     case MVE_VSUB_qr_i16:
500     case MVE_VSUB_qr_i32:
501     case MVE_VSUB_qr_i8:
502     case MVE_VSUBf16:
503     case MVE_VSUBf32:
504     case MVE_VSUBi16:
505     case MVE_VSUBi32:
506     case MVE_VSUBi8:
507       return true;
508     }
509   };
510 
511   LLVMInitializeARMTargetInfo();
512   LLVMInitializeARMTarget();
513   LLVMInitializeARMTargetMC();
514 
515   auto TT(Triple::normalize("thumbv8.1m.main-arm-none-eabi"));
516   std::string Error;
517   const Target *T = TargetRegistry::lookupTarget(TT, Error);
518   if (!T) {
519     dbgs() << Error;
520     return;
521   }
522 
523   TargetOptions Options;
524   auto TM = std::unique_ptr<LLVMTargetMachine>(
525     static_cast<LLVMTargetMachine*>(
526       T->createTargetMachine(TT, "generic", "", Options, None, None,
527                              CodeGenOpt::Default)));
528   ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
529                   std::string(TM->getTargetFeatureString()),
530                   *static_cast<const ARMBaseTargetMachine *>(TM.get()), false);
531   const ARMBaseInstrInfo *TII = ST.getInstrInfo();
532   auto MII = TM->getMCInstrInfo();
533 
534   for (unsigned i = 0; i < ARM::INSTRUCTION_LIST_END; ++i) {
535     const MCInstrDesc &Desc = TII->get(i);
536 
537     for (auto &Op : Desc.operands()) {
538       // Only check instructions that access the MQPR regs.
539       if ((Op.OperandType & MCOI::OPERAND_REGISTER) == 0 ||
540           Op.RegClass != ARM::MQPRRegClassID)
541         continue;
542 
543       uint64_t Flags = MII->get(i).TSFlags;
544       bool Valid = (Flags & ARMII::ValidForTailPredication) != 0;
545       ASSERT_EQ(IsValidTPOpcode(i), Valid)
546                 << MII->getName(i)
547                 << ": mismatched expectation for tail-predicated safety\n";
548       break;
549     }
550   }
551 }
552 
553 TEST(MachineInstr, HasSideEffects) {
554   using namespace ARM;
555   unsigned Opcodes[] = {
556       // MVE Loads/Stores
557       MVE_VLDRBS16,        MVE_VLDRBS16_post,   MVE_VLDRBS16_pre,
558       MVE_VLDRBS16_rq,     MVE_VLDRBS32,        MVE_VLDRBS32_post,
559       MVE_VLDRBS32_pre,    MVE_VLDRBS32_rq,     MVE_VLDRBU16,
560       MVE_VLDRBU16_post,   MVE_VLDRBU16_pre,    MVE_VLDRBU16_rq,
561       MVE_VLDRBU32,        MVE_VLDRBU32_post,   MVE_VLDRBU32_pre,
562       MVE_VLDRBU32_rq,     MVE_VLDRBU8,         MVE_VLDRBU8_post,
563       MVE_VLDRBU8_pre,     MVE_VLDRBU8_rq,      MVE_VLDRDU64_qi,
564       MVE_VLDRDU64_qi_pre, MVE_VLDRDU64_rq,     MVE_VLDRDU64_rq_u,
565       MVE_VLDRHS32,        MVE_VLDRHS32_post,   MVE_VLDRHS32_pre,
566       MVE_VLDRHS32_rq,     MVE_VLDRHS32_rq_u,   MVE_VLDRHU16,
567       MVE_VLDRHU16_post,   MVE_VLDRHU16_pre,    MVE_VLDRHU16_rq,
568       MVE_VLDRHU16_rq_u,   MVE_VLDRHU32,        MVE_VLDRHU32_post,
569       MVE_VLDRHU32_pre,    MVE_VLDRHU32_rq,     MVE_VLDRHU32_rq_u,
570       MVE_VLDRWU32,        MVE_VLDRWU32_post,   MVE_VLDRWU32_pre,
571       MVE_VLDRWU32_qi,     MVE_VLDRWU32_qi_pre, MVE_VLDRWU32_rq,
572       MVE_VLDRWU32_rq_u,   MVE_VLD20_16,        MVE_VLD20_16_wb,
573       MVE_VLD20_32,        MVE_VLD20_32_wb,     MVE_VLD20_8,
574       MVE_VLD20_8_wb,      MVE_VLD21_16,        MVE_VLD21_16_wb,
575       MVE_VLD21_32,        MVE_VLD21_32_wb,     MVE_VLD21_8,
576       MVE_VLD21_8_wb,      MVE_VLD40_16,        MVE_VLD40_16_wb,
577       MVE_VLD40_32,        MVE_VLD40_32_wb,     MVE_VLD40_8,
578       MVE_VLD40_8_wb,      MVE_VLD41_16,        MVE_VLD41_16_wb,
579       MVE_VLD41_32,        MVE_VLD41_32_wb,     MVE_VLD41_8,
580       MVE_VLD41_8_wb,      MVE_VLD42_16,        MVE_VLD42_16_wb,
581       MVE_VLD42_32,        MVE_VLD42_32_wb,     MVE_VLD42_8,
582       MVE_VLD42_8_wb,      MVE_VLD43_16,        MVE_VLD43_16_wb,
583       MVE_VLD43_32,        MVE_VLD43_32_wb,     MVE_VLD43_8,
584       MVE_VLD43_8_wb,      MVE_VSTRB16,         MVE_VSTRB16_post,
585       MVE_VSTRB16_pre,     MVE_VSTRB16_rq,      MVE_VSTRB32,
586       MVE_VSTRB32_post,    MVE_VSTRB32_pre,     MVE_VSTRB32_rq,
587       MVE_VSTRB8_rq,       MVE_VSTRBU8,         MVE_VSTRBU8_post,
588       MVE_VSTRBU8_pre,     MVE_VSTRD64_qi,      MVE_VSTRD64_qi_pre,
589       MVE_VSTRD64_rq,      MVE_VSTRD64_rq_u,    MVE_VSTRH16_rq,
590       MVE_VSTRH16_rq_u,    MVE_VSTRH32,         MVE_VSTRH32_post,
591       MVE_VSTRH32_pre,     MVE_VSTRH32_rq,      MVE_VSTRH32_rq_u,
592       MVE_VSTRHU16,        MVE_VSTRHU16_post,   MVE_VSTRHU16_pre,
593       MVE_VSTRW32_qi,      MVE_VSTRW32_qi_pre,  MVE_VSTRW32_rq,
594       MVE_VSTRW32_rq_u,    MVE_VSTRWU32,        MVE_VSTRWU32_post,
595       MVE_VSTRWU32_pre,    MVE_VST20_16,        MVE_VST20_16_wb,
596       MVE_VST20_32,        MVE_VST20_32_wb,     MVE_VST20_8,
597       MVE_VST20_8_wb,      MVE_VST21_16,        MVE_VST21_16_wb,
598       MVE_VST21_32,        MVE_VST21_32_wb,     MVE_VST21_8,
599       MVE_VST21_8_wb,      MVE_VST40_16,        MVE_VST40_16_wb,
600       MVE_VST40_32,        MVE_VST40_32_wb,     MVE_VST40_8,
601       MVE_VST40_8_wb,      MVE_VST41_16,        MVE_VST41_16_wb,
602       MVE_VST41_32,        MVE_VST41_32_wb,     MVE_VST41_8,
603       MVE_VST41_8_wb,      MVE_VST42_16,        MVE_VST42_16_wb,
604       MVE_VST42_32,        MVE_VST42_32_wb,     MVE_VST42_8,
605       MVE_VST42_8_wb,      MVE_VST43_16,        MVE_VST43_16_wb,
606       MVE_VST43_32,        MVE_VST43_32_wb,     MVE_VST43_8,
607       MVE_VST43_8_wb,
608   };
609 
610   LLVMInitializeARMTargetInfo();
611   LLVMInitializeARMTarget();
612   LLVMInitializeARMTargetMC();
613 
614   auto TT(Triple::normalize("thumbv8.1m.main-arm-none-eabi"));
615   std::string Error;
616   const Target *T = TargetRegistry::lookupTarget(TT, Error);
617   if (!T) {
618     dbgs() << Error;
619     return;
620   }
621 
622   TargetOptions Options;
623   auto TM = std::unique_ptr<LLVMTargetMachine>(
624       static_cast<LLVMTargetMachine *>(T->createTargetMachine(
625           TT, "generic", "", Options, None, None, CodeGenOpt::Default)));
626   ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
627                   std::string(TM->getTargetFeatureString()),
628                   *static_cast<const ARMBaseTargetMachine *>(TM.get()), false);
629   const ARMBaseInstrInfo *TII = ST.getInstrInfo();
630   auto MII = TM->getMCInstrInfo();
631 
632   for (unsigned Op : Opcodes) {
633     const MCInstrDesc &Desc = TII->get(Op);
634     ASSERT_FALSE(Desc.hasUnmodeledSideEffects())
635         << MII->getName(Op) << " has unexpected side effects";
636   }
637 }
638