xref: /llvm-project/llvm/unittests/Target/ARM/MachineInstrTest.cpp (revision 73346f58486d29c0d2687af1208fa146168d62d8) 
1 #include "ARMBaseInstrInfo.h"
2 #include "ARMSubtarget.h"
3 #include "ARMTargetMachine.h"
4 #include "llvm/Support/TargetRegistry.h"
5 #include "llvm/Support/TargetSelect.h"
6 #include "llvm/Target/TargetMachine.h"
7 #include "llvm/Target/TargetOptions.h"
8 
9 #include "gtest/gtest.h"
10 
11 using namespace llvm;
12 
13 TEST(MachineInstructionDoubleWidthResult, IsCorrect) {
14   using namespace ARM;
15 
16   auto DoubleWidthResult = [](unsigned Opcode) {
17     switch (Opcode) {
18     default:
19       break;
20     case MVE_VMULLBp16:
21     case MVE_VMULLBp8:
22     case MVE_VMULLBs16:
23     case MVE_VMULLBs32:
24     case MVE_VMULLBs8:
25     case MVE_VMULLBu16:
26     case MVE_VMULLBu32:
27     case MVE_VMULLBu8:
28     case MVE_VMULLTp16:
29     case MVE_VMULLTp8:
30     case MVE_VMULLTs16:
31     case MVE_VMULLTs32:
32     case MVE_VMULLTs8:
33     case MVE_VMULLTu16:
34     case MVE_VMULLTu32:
35     case MVE_VMULLTu8:
36     case MVE_VQDMULL_qr_s16bh:
37     case MVE_VQDMULL_qr_s16th:
38     case MVE_VQDMULL_qr_s32bh:
39     case MVE_VQDMULL_qr_s32th:
40     case MVE_VQDMULLs16bh:
41     case MVE_VQDMULLs16th:
42     case MVE_VQDMULLs32bh:
43     case MVE_VQDMULLs32th:
44     case MVE_VMOVLs16bh:
45     case MVE_VMOVLs16th:
46     case MVE_VMOVLs8bh:
47     case MVE_VMOVLs8th:
48     case MVE_VMOVLu16bh:
49     case MVE_VMOVLu16th:
50     case MVE_VMOVLu8bh:
51     case MVE_VMOVLu8th:
52     case MVE_VSHLL_imms16bh:
53     case MVE_VSHLL_imms16th:
54     case MVE_VSHLL_imms8bh:
55     case MVE_VSHLL_imms8th:
56     case MVE_VSHLL_immu16bh:
57     case MVE_VSHLL_immu16th:
58     case MVE_VSHLL_immu8bh:
59     case MVE_VSHLL_immu8th:
60     case MVE_VSHLL_lws16bh:
61     case MVE_VSHLL_lws16th:
62     case MVE_VSHLL_lws8bh:
63     case MVE_VSHLL_lws8th:
64     case MVE_VSHLL_lwu16bh:
65     case MVE_VSHLL_lwu16th:
66     case MVE_VSHLL_lwu8bh:
67     case MVE_VSHLL_lwu8th:
68       return true;
69     }
70     return false;
71   };
72 
73   LLVMInitializeARMTargetInfo();
74   LLVMInitializeARMTarget();
75   LLVMInitializeARMTargetMC();
76 
77   auto TT(Triple::normalize("thumbv8.1m.main-none-none-eabi"));
78   std::string Error;
79   const Target *T = TargetRegistry::lookupTarget(TT, Error);
80   if (!T) {
81     dbgs() << Error;
82     return;
83   }
84 
85   TargetOptions Options;
86   auto TM = std::unique_ptr<LLVMTargetMachine>(
87     static_cast<LLVMTargetMachine*>(
88       T->createTargetMachine(TT, "generic", "", Options, None, None,
89                              CodeGenOpt::Default)));
90   ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
91                   std::string(TM->getTargetFeatureString()),
92                   *static_cast<const ARMBaseTargetMachine *>(TM.get()), false);
93   const ARMBaseInstrInfo *TII = ST.getInstrInfo();
94   auto MII = TM->getMCInstrInfo();
95 
96   for (unsigned i = 0; i < ARM::INSTRUCTION_LIST_END; ++i) {
97     const MCInstrDesc &Desc = TII->get(i);
98 
99     uint64_t Flags = Desc.TSFlags;
100     if ((Flags & ARMII::DomainMask) != ARMII::DomainMVE)
101       continue;
102 
103     bool Valid = (Flags & ARMII::DoubleWidthResult) != 0;
104     ASSERT_EQ(DoubleWidthResult(i), Valid)
105               << MII->getName(i)
106               << ": mismatched expectation for tail-predicated safety\n";
107   }
108 }
109 
110 TEST(MachineInstructionHorizontalReduction, IsCorrect) {
111   using namespace ARM;
112 
113   auto HorizontalReduction = [](unsigned Opcode) {
114     switch (Opcode) {
115     default:
116       break;
117     case MVE_VABAVs16:
118     case MVE_VABAVs32:
119     case MVE_VABAVs8:
120     case MVE_VABAVu16:
121     case MVE_VABAVu32:
122     case MVE_VABAVu8:
123     case MVE_VADDLVs32acc:
124     case MVE_VADDLVs32no_acc:
125     case MVE_VADDLVu32acc:
126     case MVE_VADDLVu32no_acc:
127     case MVE_VADDVs16acc:
128     case MVE_VADDVs16no_acc:
129     case MVE_VADDVs32acc:
130     case MVE_VADDVs32no_acc:
131     case MVE_VADDVs8acc:
132     case MVE_VADDVs8no_acc:
133     case MVE_VADDVu16acc:
134     case MVE_VADDVu16no_acc:
135     case MVE_VADDVu32acc:
136     case MVE_VADDVu32no_acc:
137     case MVE_VADDVu8acc:
138     case MVE_VADDVu8no_acc:
139     case MVE_VMAXAVs16:
140     case MVE_VMAXAVs32:
141     case MVE_VMAXAVs8:
142     case MVE_VMAXNMAVf16:
143     case MVE_VMAXNMAVf32:
144     case MVE_VMAXNMVf16:
145     case MVE_VMAXNMVf32:
146     case MVE_VMAXVs16:
147     case MVE_VMAXVs32:
148     case MVE_VMAXVs8:
149     case MVE_VMAXVu16:
150     case MVE_VMAXVu32:
151     case MVE_VMAXVu8:
152     case MVE_VMINAVs16:
153     case MVE_VMINAVs32:
154     case MVE_VMINAVs8:
155     case MVE_VMINNMAVf16:
156     case MVE_VMINNMAVf32:
157     case MVE_VMINNMVf16:
158     case MVE_VMINNMVf32:
159     case MVE_VMINVs16:
160     case MVE_VMINVs32:
161     case MVE_VMINVs8:
162     case MVE_VMINVu16:
163     case MVE_VMINVu32:
164     case MVE_VMINVu8:
165     case MVE_VMLADAVas16:
166     case MVE_VMLADAVas32:
167     case MVE_VMLADAVas8:
168     case MVE_VMLADAVau16:
169     case MVE_VMLADAVau32:
170     case MVE_VMLADAVau8:
171     case MVE_VMLADAVaxs16:
172     case MVE_VMLADAVaxs32:
173     case MVE_VMLADAVaxs8:
174     case MVE_VMLADAVs16:
175     case MVE_VMLADAVs32:
176     case MVE_VMLADAVs8:
177     case MVE_VMLADAVu16:
178     case MVE_VMLADAVu32:
179     case MVE_VMLADAVu8:
180     case MVE_VMLADAVxs16:
181     case MVE_VMLADAVxs32:
182     case MVE_VMLADAVxs8:
183     case MVE_VMLALDAVas16:
184     case MVE_VMLALDAVas32:
185     case MVE_VMLALDAVau16:
186     case MVE_VMLALDAVau32:
187     case MVE_VMLALDAVaxs16:
188     case MVE_VMLALDAVaxs32:
189     case MVE_VMLALDAVs16:
190     case MVE_VMLALDAVs32:
191     case MVE_VMLALDAVu16:
192     case MVE_VMLALDAVu32:
193     case MVE_VMLALDAVxs16:
194     case MVE_VMLALDAVxs32:
195     case MVE_VMLSDAVas16:
196     case MVE_VMLSDAVas32:
197     case MVE_VMLSDAVas8:
198     case MVE_VMLSDAVaxs16:
199     case MVE_VMLSDAVaxs32:
200     case MVE_VMLSDAVaxs8:
201     case MVE_VMLSDAVs16:
202     case MVE_VMLSDAVs32:
203     case MVE_VMLSDAVs8:
204     case MVE_VMLSDAVxs16:
205     case MVE_VMLSDAVxs32:
206     case MVE_VMLSDAVxs8:
207     case MVE_VMLSLDAVas16:
208     case MVE_VMLSLDAVas32:
209     case MVE_VMLSLDAVaxs16:
210     case MVE_VMLSLDAVaxs32:
211     case MVE_VMLSLDAVs16:
212     case MVE_VMLSLDAVs32:
213     case MVE_VMLSLDAVxs16:
214     case MVE_VMLSLDAVxs32:
215     case MVE_VRMLALDAVHas32:
216     case MVE_VRMLALDAVHau32:
217     case MVE_VRMLALDAVHaxs32:
218     case MVE_VRMLALDAVHs32:
219     case MVE_VRMLALDAVHu32:
220     case MVE_VRMLALDAVHxs32:
221     case MVE_VRMLSLDAVHas32:
222     case MVE_VRMLSLDAVHaxs32:
223     case MVE_VRMLSLDAVHs32:
224     case MVE_VRMLSLDAVHxs32:
225       return true;
226     }
227     return false;
228   };
229 
230   LLVMInitializeARMTargetInfo();
231   LLVMInitializeARMTarget();
232   LLVMInitializeARMTargetMC();
233 
234   auto TT(Triple::normalize("thumbv8.1m.main-none-none-eabi"));
235   std::string Error;
236   const Target *T = TargetRegistry::lookupTarget(TT, Error);
237   if (!T) {
238     dbgs() << Error;
239     return;
240   }
241 
242   TargetOptions Options;
243   auto TM = std::unique_ptr<LLVMTargetMachine>(
244     static_cast<LLVMTargetMachine*>(
245       T->createTargetMachine(TT, "generic", "", Options, None, None,
246                              CodeGenOpt::Default)));
247   ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
248                   std::string(TM->getTargetFeatureString()),
249                   *static_cast<const ARMBaseTargetMachine *>(TM.get()), false);
250   const ARMBaseInstrInfo *TII = ST.getInstrInfo();
251   auto MII = TM->getMCInstrInfo();
252 
253   for (unsigned i = 0; i < ARM::INSTRUCTION_LIST_END; ++i) {
254     const MCInstrDesc &Desc = TII->get(i);
255 
256     uint64_t Flags = Desc.TSFlags;
257     if ((Flags & ARMII::DomainMask) != ARMII::DomainMVE)
258       continue;
259     bool Valid = (Flags & ARMII::HorizontalReduction) != 0;
260     ASSERT_EQ(HorizontalReduction(i), Valid)
261               << MII->getName(i)
262               << ": mismatched expectation for tail-predicated safety\n";
263   }
264 }
265 
266 TEST(MachineInstructionRetainsPreviousHalfElement, IsCorrect) {
267   using namespace ARM;
268 
269   auto RetainsPreviousHalfElement = [](unsigned Opcode) {
270     switch (Opcode) {
271     default:
272       break;
273     case MVE_VMOVNi16bh:
274     case MVE_VMOVNi16th:
275     case MVE_VMOVNi32bh:
276     case MVE_VMOVNi32th:
277     case MVE_VQMOVNs16bh:
278     case MVE_VQMOVNs16th:
279     case MVE_VQMOVNs32bh:
280     case MVE_VQMOVNs32th:
281     case MVE_VQMOVNu16bh:
282     case MVE_VQMOVNu16th:
283     case MVE_VQMOVNu32bh:
284     case MVE_VQMOVNu32th:
285     case MVE_VQMOVUNs16bh:
286     case MVE_VQMOVUNs16th:
287     case MVE_VQMOVUNs32bh:
288     case MVE_VQMOVUNs32th:
289     case MVE_VQRSHRNbhs16:
290     case MVE_VQRSHRNbhs32:
291     case MVE_VQRSHRNbhu16:
292     case MVE_VQRSHRNbhu32:
293     case MVE_VQRSHRNths16:
294     case MVE_VQRSHRNths32:
295     case MVE_VQRSHRNthu16:
296     case MVE_VQRSHRNthu32:
297     case MVE_VQRSHRUNs16bh:
298     case MVE_VQRSHRUNs16th:
299     case MVE_VQRSHRUNs32bh:
300     case MVE_VQRSHRUNs32th:
301     case MVE_VQSHRNbhs16:
302     case MVE_VQSHRNbhs32:
303     case MVE_VQSHRNbhu16:
304     case MVE_VQSHRNbhu32:
305     case MVE_VQSHRNths16:
306     case MVE_VQSHRNths32:
307     case MVE_VQSHRNthu16:
308     case MVE_VQSHRNthu32:
309     case MVE_VQSHRUNs16bh:
310     case MVE_VQSHRUNs16th:
311     case MVE_VQSHRUNs32bh:
312     case MVE_VQSHRUNs32th:
313     case MVE_VRSHRNi16bh:
314     case MVE_VRSHRNi16th:
315     case MVE_VRSHRNi32bh:
316     case MVE_VRSHRNi32th:
317     case MVE_VSHRNi16bh:
318     case MVE_VSHRNi16th:
319     case MVE_VSHRNi32bh:
320     case MVE_VSHRNi32th:
321     case MVE_VCVTf16f32bh:
322     case MVE_VCVTf16f32th:
323     case MVE_VCVTf32f16bh:
324     case MVE_VCVTf32f16th:
325       return true;
326     }
327     return false;
328   };
329 
330   LLVMInitializeARMTargetInfo();
331   LLVMInitializeARMTarget();
332   LLVMInitializeARMTargetMC();
333 
334   auto TT(Triple::normalize("thumbv8.1m.main-none-none-eabi"));
335   std::string Error;
336   const Target *T = TargetRegistry::lookupTarget(TT, Error);
337   if (!T) {
338     dbgs() << Error;
339     return;
340   }
341 
342   TargetOptions Options;
343   auto TM = std::unique_ptr<LLVMTargetMachine>(
344     static_cast<LLVMTargetMachine*>(
345       T->createTargetMachine(TT, "generic", "", Options, None, None,
346                              CodeGenOpt::Default)));
347   ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
348                   std::string(TM->getTargetFeatureString()),
349                   *static_cast<const ARMBaseTargetMachine *>(TM.get()), false);
350   const ARMBaseInstrInfo *TII = ST.getInstrInfo();
351   auto MII = TM->getMCInstrInfo();
352 
353   for (unsigned i = 0; i < ARM::INSTRUCTION_LIST_END; ++i) {
354     const MCInstrDesc &Desc = TII->get(i);
355 
356     uint64_t Flags = Desc.TSFlags;
357     if ((Flags & ARMII::DomainMask) != ARMII::DomainMVE)
358       continue;
359 
360     bool Valid = (Flags & ARMII::RetainsPreviousHalfElement) != 0;
361     ASSERT_EQ(RetainsPreviousHalfElement(i), Valid)
362               << MII->getName(i)
363               << ": mismatched expectation for tail-predicated safety\n";
364   }
365 }
366 // Test for instructions that aren't immediately obviously valid within a
367 // tail-predicated loop. This should be marked up in their tablegen
368 // descriptions. Currently we, conservatively, disallow:
369 // - cross beat carries.
370 // - complex operations.
371 // - horizontal operations with exchange.
372 // - byte swapping.
373 // - interleaved memory instructions.
374 // TODO: Add to this list once we can handle them safely.
375 TEST(MachineInstrValidTailPredication, IsCorrect) {
376 
377   using namespace ARM;
378 
379   auto IsValidTPOpcode = [](unsigned Opcode) {
380     switch (Opcode) {
381     default:
382       return false;
383     case MVE_ASRLi:
384     case MVE_ASRLr:
385     case MVE_LSRL:
386     case MVE_LSLLi:
387     case MVE_LSLLr:
388     case MVE_SQRSHR:
389     case MVE_SQRSHRL:
390     case MVE_SQSHL:
391     case MVE_SQSHLL:
392     case MVE_SRSHR:
393     case MVE_SRSHRL:
394     case MVE_UQRSHL:
395     case MVE_UQRSHLL:
396     case MVE_UQSHL:
397     case MVE_UQSHLL:
398     case MVE_URSHR:
399     case MVE_URSHRL:
400     case MVE_VABDf16:
401     case MVE_VABDf32:
402     case MVE_VABDs16:
403     case MVE_VABDs32:
404     case MVE_VABDs8:
405     case MVE_VABDu16:
406     case MVE_VABDu32:
407     case MVE_VABDu8:
408     case MVE_VABSf16:
409     case MVE_VABSf32:
410     case MVE_VABSs16:
411     case MVE_VABSs32:
412     case MVE_VABSs8:
413     case MVE_VADD_qr_f16:
414     case MVE_VADD_qr_f32:
415     case MVE_VADD_qr_i16:
416     case MVE_VADD_qr_i32:
417     case MVE_VADD_qr_i8:
418     case MVE_VADDVs16acc:
419     case MVE_VADDVs16no_acc:
420     case MVE_VADDVs32acc:
421     case MVE_VADDVs32no_acc:
422     case MVE_VADDVs8acc:
423     case MVE_VADDVs8no_acc:
424     case MVE_VADDVu16acc:
425     case MVE_VADDVu16no_acc:
426     case MVE_VADDVu32acc:
427     case MVE_VADDVu32no_acc:
428     case MVE_VADDVu8acc:
429     case MVE_VADDVu8no_acc:
430     case MVE_VADDf16:
431     case MVE_VADDf32:
432     case MVE_VADDi16:
433     case MVE_VADDi32:
434     case MVE_VADDi8:
435     case MVE_VAND:
436     case MVE_VBIC:
437     case MVE_VBICimmi16:
438     case MVE_VBICimmi32:
439     case MVE_VBRSR16:
440     case MVE_VBRSR32:
441     case MVE_VBRSR8:
442     case MVE_VCLSs16:
443     case MVE_VCLSs32:
444     case MVE_VCLSs8:
445     case MVE_VCLZs16:
446     case MVE_VCLZs32:
447     case MVE_VCLZs8:
448     case MVE_VCMPf16:
449     case MVE_VCMPf16r:
450     case MVE_VCMPf32:
451     case MVE_VCMPf32r:
452     case MVE_VCMPi16:
453     case MVE_VCMPi16r:
454     case MVE_VCMPi32:
455     case MVE_VCMPi32r:
456     case MVE_VCMPi8:
457     case MVE_VCMPi8r:
458     case MVE_VCMPs16:
459     case MVE_VCMPs16r:
460     case MVE_VCMPs32:
461     case MVE_VCMPs32r:
462     case MVE_VCMPs8:
463     case MVE_VCMPs8r:
464     case MVE_VCMPu16:
465     case MVE_VCMPu16r:
466     case MVE_VCMPu32:
467     case MVE_VCMPu32r:
468     case MVE_VCMPu8:
469     case MVE_VCMPu8r:
470     case MVE_VCTP16:
471     case MVE_VCTP32:
472     case MVE_VCTP64:
473     case MVE_VCTP8:
474     case MVE_VCVTf16s16_fix:
475     case MVE_VCVTf16s16n:
476     case MVE_VCVTf16u16_fix:
477     case MVE_VCVTf16u16n:
478     case MVE_VCVTf32s32_fix:
479     case MVE_VCVTf32s32n:
480     case MVE_VCVTf32u32_fix:
481     case MVE_VCVTf32u32n:
482     case MVE_VCVTs16f16_fix:
483     case MVE_VCVTs16f16a:
484     case MVE_VCVTs16f16m:
485     case MVE_VCVTs16f16n:
486     case MVE_VCVTs16f16p:
487     case MVE_VCVTs16f16z:
488     case MVE_VCVTs32f32_fix:
489     case MVE_VCVTs32f32a:
490     case MVE_VCVTs32f32m:
491     case MVE_VCVTs32f32n:
492     case MVE_VCVTs32f32p:
493     case MVE_VCVTs32f32z:
494     case MVE_VCVTu16f16_fix:
495     case MVE_VCVTu16f16a:
496     case MVE_VCVTu16f16m:
497     case MVE_VCVTu16f16n:
498     case MVE_VCVTu16f16p:
499     case MVE_VCVTu16f16z:
500     case MVE_VCVTu32f32_fix:
501     case MVE_VCVTu32f32a:
502     case MVE_VCVTu32f32m:
503     case MVE_VCVTu32f32n:
504     case MVE_VCVTu32f32p:
505     case MVE_VCVTu32f32z:
506     case MVE_VDDUPu16:
507     case MVE_VDDUPu32:
508     case MVE_VDDUPu8:
509     case MVE_VDUP16:
510     case MVE_VDUP32:
511     case MVE_VDUP8:
512     case MVE_VDWDUPu16:
513     case MVE_VDWDUPu32:
514     case MVE_VDWDUPu8:
515     case MVE_VEOR:
516     case MVE_VFMA_qr_Sf16:
517     case MVE_VFMA_qr_Sf32:
518     case MVE_VFMA_qr_f16:
519     case MVE_VFMA_qr_f32:
520     case MVE_VFMAf16:
521     case MVE_VFMAf32:
522     case MVE_VFMSf16:
523     case MVE_VFMSf32:
524     case MVE_VMAXAs16:
525     case MVE_VMAXAs32:
526     case MVE_VMAXAs8:
527     case MVE_VMAXs16:
528     case MVE_VMAXs32:
529     case MVE_VMAXs8:
530     case MVE_VMAXu16:
531     case MVE_VMAXu32:
532     case MVE_VMAXu8:
533     case MVE_VMAXNMf16:
534     case MVE_VMAXNMf32:
535     case MVE_VMAXNMAf16:
536     case MVE_VMAXNMAf32:
537     case MVE_VMINAs16:
538     case MVE_VMINAs32:
539     case MVE_VMINAs8:
540     case MVE_VMINs16:
541     case MVE_VMINs32:
542     case MVE_VMINs8:
543     case MVE_VMINu16:
544     case MVE_VMINu32:
545     case MVE_VMINu8:
546     case MVE_VMINNMf16:
547     case MVE_VMINNMf32:
548     case MVE_VMINNMAf16:
549     case MVE_VMINNMAf32:
550     case MVE_VMLADAVas16:
551     case MVE_VMLADAVas32:
552     case MVE_VMLADAVas8:
553     case MVE_VMLADAVau16:
554     case MVE_VMLADAVau32:
555     case MVE_VMLADAVau8:
556     case MVE_VMLADAVs16:
557     case MVE_VMLADAVs32:
558     case MVE_VMLADAVs8:
559     case MVE_VMLADAVu16:
560     case MVE_VMLADAVu32:
561     case MVE_VMLADAVu8:
562     case MVE_VMLALDAVs16:
563     case MVE_VMLALDAVs32:
564     case MVE_VMLALDAVu16:
565     case MVE_VMLALDAVu32:
566     case MVE_VMLALDAVas16:
567     case MVE_VMLALDAVas32:
568     case MVE_VMLALDAVau16:
569     case MVE_VMLALDAVau32:
570     case MVE_VMLSDAVas16:
571     case MVE_VMLSDAVas32:
572     case MVE_VMLSDAVas8:
573     case MVE_VMLSDAVs16:
574     case MVE_VMLSDAVs32:
575     case MVE_VMLSDAVs8:
576     case MVE_VMLSLDAVas16:
577     case MVE_VMLSLDAVas32:
578     case MVE_VMLSLDAVs16:
579     case MVE_VMLSLDAVs32:
580     case MVE_VRMLALDAVHas32:
581     case MVE_VRMLALDAVHau32:
582     case MVE_VRMLALDAVHs32:
583     case MVE_VRMLALDAVHu32:
584     case MVE_VRMLSLDAVHas32:
585     case MVE_VRMLSLDAVHs32:
586     case MVE_VMLAS_qr_s16:
587     case MVE_VMLAS_qr_s32:
588     case MVE_VMLAS_qr_s8:
589     case MVE_VMLAS_qr_u16:
590     case MVE_VMLAS_qr_u32:
591     case MVE_VMLAS_qr_u8:
592     case MVE_VMLA_qr_s16:
593     case MVE_VMLA_qr_s32:
594     case MVE_VMLA_qr_s8:
595     case MVE_VMLA_qr_u16:
596     case MVE_VMLA_qr_u32:
597     case MVE_VMLA_qr_u8:
598     case MVE_VHADD_qr_s16:
599     case MVE_VHADD_qr_s32:
600     case MVE_VHADD_qr_s8:
601     case MVE_VHADD_qr_u16:
602     case MVE_VHADD_qr_u32:
603     case MVE_VHADD_qr_u8:
604     case MVE_VHADDs16:
605     case MVE_VHADDs32:
606     case MVE_VHADDs8:
607     case MVE_VHADDu16:
608     case MVE_VHADDu32:
609     case MVE_VHADDu8:
610     case MVE_VHSUB_qr_s16:
611     case MVE_VHSUB_qr_s32:
612     case MVE_VHSUB_qr_s8:
613     case MVE_VHSUB_qr_u16:
614     case MVE_VHSUB_qr_u32:
615     case MVE_VHSUB_qr_u8:
616     case MVE_VHSUBs16:
617     case MVE_VHSUBs32:
618     case MVE_VHSUBs8:
619     case MVE_VHSUBu16:
620     case MVE_VHSUBu32:
621     case MVE_VHSUBu8:
622     case MVE_VIDUPu16:
623     case MVE_VIDUPu32:
624     case MVE_VIDUPu8:
625     case MVE_VIWDUPu16:
626     case MVE_VIWDUPu32:
627     case MVE_VIWDUPu8:
628     case MVE_VLD20_8:
629     case MVE_VLD21_8:
630     case MVE_VLD20_16:
631     case MVE_VLD21_16:
632     case MVE_VLD20_32:
633     case MVE_VLD21_32:
634     case MVE_VLD20_8_wb:
635     case MVE_VLD21_8_wb:
636     case MVE_VLD20_16_wb:
637     case MVE_VLD21_16_wb:
638     case MVE_VLD20_32_wb:
639     case MVE_VLD21_32_wb:
640     case MVE_VLD40_8:
641     case MVE_VLD41_8:
642     case MVE_VLD42_8:
643     case MVE_VLD43_8:
644     case MVE_VLD40_16:
645     case MVE_VLD41_16:
646     case MVE_VLD42_16:
647     case MVE_VLD43_16:
648     case MVE_VLD40_32:
649     case MVE_VLD41_32:
650     case MVE_VLD42_32:
651     case MVE_VLD43_32:
652     case MVE_VLD40_8_wb:
653     case MVE_VLD41_8_wb:
654     case MVE_VLD42_8_wb:
655     case MVE_VLD43_8_wb:
656     case MVE_VLD40_16_wb:
657     case MVE_VLD41_16_wb:
658     case MVE_VLD42_16_wb:
659     case MVE_VLD43_16_wb:
660     case MVE_VLD40_32_wb:
661     case MVE_VLD41_32_wb:
662     case MVE_VLD42_32_wb:
663     case MVE_VLD43_32_wb:
664     case MVE_VLDRBS16:
665     case MVE_VLDRBS16_post:
666     case MVE_VLDRBS16_pre:
667     case MVE_VLDRBS16_rq:
668     case MVE_VLDRBS32:
669     case MVE_VLDRBS32_post:
670     case MVE_VLDRBS32_pre:
671     case MVE_VLDRBS32_rq:
672     case MVE_VLDRBU16:
673     case MVE_VLDRBU16_post:
674     case MVE_VLDRBU16_pre:
675     case MVE_VLDRBU16_rq:
676     case MVE_VLDRBU32:
677     case MVE_VLDRBU32_post:
678     case MVE_VLDRBU32_pre:
679     case MVE_VLDRBU32_rq:
680     case MVE_VLDRBU8:
681     case MVE_VLDRBU8_post:
682     case MVE_VLDRBU8_pre:
683     case MVE_VLDRBU8_rq:
684     case MVE_VLDRDU64_qi:
685     case MVE_VLDRDU64_qi_pre:
686     case MVE_VLDRDU64_rq:
687     case MVE_VLDRDU64_rq_u:
688     case MVE_VLDRHS32:
689     case MVE_VLDRHS32_post:
690     case MVE_VLDRHS32_pre:
691     case MVE_VLDRHS32_rq:
692     case MVE_VLDRHS32_rq_u:
693     case MVE_VLDRHU16:
694     case MVE_VLDRHU16_post:
695     case MVE_VLDRHU16_pre:
696     case MVE_VLDRHU16_rq:
697     case MVE_VLDRHU16_rq_u:
698     case MVE_VLDRHU32:
699     case MVE_VLDRHU32_post:
700     case MVE_VLDRHU32_pre:
701     case MVE_VLDRHU32_rq:
702     case MVE_VLDRHU32_rq_u:
703     case MVE_VLDRWU32:
704     case MVE_VLDRWU32_post:
705     case MVE_VLDRWU32_pre:
706     case MVE_VLDRWU32_qi:
707     case MVE_VLDRWU32_qi_pre:
708     case MVE_VLDRWU32_rq:
709     case MVE_VLDRWU32_rq_u:
710     case MVE_VMOVimmf32:
711     case MVE_VMOVimmi16:
712     case MVE_VMOVimmi32:
713     case MVE_VMOVimmi64:
714     case MVE_VMOVimmi8:
715     case MVE_VMOVNi16bh:
716     case MVE_VMOVNi16th:
717     case MVE_VMOVNi32bh:
718     case MVE_VMOVNi32th:
719     case MVE_VMULLBp16:
720     case MVE_VMULLBp8:
721     case MVE_VMULLBs16:
722     case MVE_VMULLBs32:
723     case MVE_VMULLBs8:
724     case MVE_VMULLBu16:
725     case MVE_VMULLBu32:
726     case MVE_VMULLBu8:
727     case MVE_VMULLTp16:
728     case MVE_VMULLTp8:
729     case MVE_VMULLTs16:
730     case MVE_VMULLTs32:
731     case MVE_VMULLTs8:
732     case MVE_VMULLTu16:
733     case MVE_VMULLTu32:
734     case MVE_VMULLTu8:
735     case MVE_VMUL_qr_f16:
736     case MVE_VMUL_qr_f32:
737     case MVE_VMUL_qr_i16:
738     case MVE_VMUL_qr_i32:
739     case MVE_VMUL_qr_i8:
740     case MVE_VMULf16:
741     case MVE_VMULf32:
742     case MVE_VMULi16:
743     case MVE_VMULi8:
744     case MVE_VMULi32:
745     case MVE_VMULHs32:
746     case MVE_VMULHs16:
747     case MVE_VMULHs8:
748     case MVE_VMULHu32:
749     case MVE_VMULHu16:
750     case MVE_VMULHu8:
751     case MVE_VMVN:
752     case MVE_VMVNimmi16:
753     case MVE_VMVNimmi32:
754     case MVE_VNEGf16:
755     case MVE_VNEGf32:
756     case MVE_VNEGs16:
757     case MVE_VNEGs32:
758     case MVE_VNEGs8:
759     case MVE_VORN:
760     case MVE_VORR:
761     case MVE_VORRimmi16:
762     case MVE_VORRimmi32:
763     case MVE_VPST:
764     case MVE_VPTv16i8:
765     case MVE_VPTv8i16:
766     case MVE_VPTv4i32:
767     case MVE_VPTv16i8r:
768     case MVE_VPTv8i16r:
769     case MVE_VPTv4i32r:
770     case MVE_VPTv16s8:
771     case MVE_VPTv8s16:
772     case MVE_VPTv4s32:
773     case MVE_VPTv16s8r:
774     case MVE_VPTv8s16r:
775     case MVE_VPTv4s32r:
776     case MVE_VPTv16u8:
777     case MVE_VPTv8u16:
778     case MVE_VPTv4u32:
779     case MVE_VPTv16u8r:
780     case MVE_VPTv8u16r:
781     case MVE_VPTv4u32r:
782     case MVE_VPTv8f16:
783     case MVE_VPTv4f32:
784     case MVE_VPTv8f16r:
785     case MVE_VPTv4f32r:
786     case MVE_VQABSs16:
787     case MVE_VQABSs32:
788     case MVE_VQABSs8:
789     case MVE_VQADD_qr_s16:
790     case MVE_VQADD_qr_s32:
791     case MVE_VQADD_qr_s8:
792     case MVE_VQADD_qr_u16:
793     case MVE_VQADD_qr_u32:
794     case MVE_VQADD_qr_u8:
795     case MVE_VQADDs16:
796     case MVE_VQADDs32:
797     case MVE_VQADDs8:
798     case MVE_VQADDu16:
799     case MVE_VQADDu32:
800     case MVE_VQADDu8:
801     case MVE_VQDMULH_qr_s16:
802     case MVE_VQDMULH_qr_s32:
803     case MVE_VQDMULH_qr_s8:
804     case MVE_VQDMULHi16:
805     case MVE_VQDMULHi32:
806     case MVE_VQDMULHi8:
807     case MVE_VQDMULL_qr_s16bh:
808     case MVE_VQDMULL_qr_s16th:
809     case MVE_VQDMULL_qr_s32bh:
810     case MVE_VQDMULL_qr_s32th:
811     case MVE_VQDMULLs16bh:
812     case MVE_VQDMULLs16th:
813     case MVE_VQDMULLs32bh:
814     case MVE_VQDMULLs32th:
815     case MVE_VQRDMULH_qr_s16:
816     case MVE_VQRDMULH_qr_s32:
817     case MVE_VQRDMULH_qr_s8:
818     case MVE_VQRDMULHi16:
819     case MVE_VQRDMULHi32:
820     case MVE_VQRDMULHi8:
821     case MVE_VQNEGs16:
822     case MVE_VQNEGs32:
823     case MVE_VQNEGs8:
824     case MVE_VQMOVNs16bh:
825     case MVE_VQMOVNs16th:
826     case MVE_VQMOVNs32bh:
827     case MVE_VQMOVNs32th:
828     case MVE_VQMOVNu16bh:
829     case MVE_VQMOVNu16th:
830     case MVE_VQMOVNu32bh:
831     case MVE_VQMOVNu32th:
832     case MVE_VQMOVUNs16bh:
833     case MVE_VQMOVUNs16th:
834     case MVE_VQMOVUNs32bh:
835     case MVE_VQMOVUNs32th:
836     case MVE_VQRSHL_by_vecs16:
837     case MVE_VQRSHL_by_vecs32:
838     case MVE_VQRSHL_by_vecs8:
839     case MVE_VQRSHL_by_vecu16:
840     case MVE_VQRSHL_by_vecu32:
841     case MVE_VQRSHL_by_vecu8:
842     case MVE_VQRSHL_qrs16:
843     case MVE_VQRSHL_qrs32:
844     case MVE_VQRSHL_qrs8:
845     case MVE_VQRSHL_qru16:
846     case MVE_VQRSHL_qru8:
847     case MVE_VQRSHL_qru32:
848     case MVE_VQSHLU_imms16:
849     case MVE_VQSHLU_imms32:
850     case MVE_VQSHLU_imms8:
851     case MVE_VQSHLimms16:
852     case MVE_VQSHLimms32:
853     case MVE_VQSHLimms8:
854     case MVE_VQSHLimmu16:
855     case MVE_VQSHLimmu32:
856     case MVE_VQSHLimmu8:
857     case MVE_VQSHL_by_vecs16:
858     case MVE_VQSHL_by_vecs32:
859     case MVE_VQSHL_by_vecs8:
860     case MVE_VQSHL_by_vecu16:
861     case MVE_VQSHL_by_vecu32:
862     case MVE_VQSHL_by_vecu8:
863     case MVE_VQSHL_qrs16:
864     case MVE_VQSHL_qrs32:
865     case MVE_VQSHL_qrs8:
866     case MVE_VQSHL_qru16:
867     case MVE_VQSHL_qru32:
868     case MVE_VQSHL_qru8:
869     case MVE_VQRSHRNbhs16:
870     case MVE_VQRSHRNbhs32:
871     case MVE_VQRSHRNbhu16:
872     case MVE_VQRSHRNbhu32:
873     case MVE_VQRSHRNths16:
874     case MVE_VQRSHRNths32:
875     case MVE_VQRSHRNthu16:
876     case MVE_VQRSHRNthu32:
877     case MVE_VQRSHRUNs16bh:
878     case MVE_VQRSHRUNs16th:
879     case MVE_VQRSHRUNs32bh:
880     case MVE_VQRSHRUNs32th:
881     case MVE_VQSHRNbhs16:
882     case MVE_VQSHRNbhs32:
883     case MVE_VQSHRNbhu16:
884     case MVE_VQSHRNbhu32:
885     case MVE_VQSHRNths16:
886     case MVE_VQSHRNths32:
887     case MVE_VQSHRNthu16:
888     case MVE_VQSHRNthu32:
889     case MVE_VQSHRUNs16bh:
890     case MVE_VQSHRUNs16th:
891     case MVE_VQSHRUNs32bh:
892     case MVE_VQSHRUNs32th:
893     case MVE_VQSUB_qr_s16:
894     case MVE_VQSUB_qr_s32:
895     case MVE_VQSUB_qr_s8:
896     case MVE_VQSUB_qr_u16:
897     case MVE_VQSUB_qr_u32:
898     case MVE_VQSUB_qr_u8:
899     case MVE_VQSUBs16:
900     case MVE_VQSUBs32:
901     case MVE_VQSUBs8:
902     case MVE_VQSUBu16:
903     case MVE_VQSUBu32:
904     case MVE_VQSUBu8:
905     case MVE_VRHADDs16:
906     case MVE_VRHADDs32:
907     case MVE_VRHADDs8:
908     case MVE_VRHADDu16:
909     case MVE_VRHADDu32:
910     case MVE_VRHADDu8:
911     case MVE_VRINTf16A:
912     case MVE_VRINTf16M:
913     case MVE_VRINTf16N:
914     case MVE_VRINTf16P:
915     case MVE_VRINTf16X:
916     case MVE_VRINTf16Z:
917     case MVE_VRINTf32A:
918     case MVE_VRINTf32M:
919     case MVE_VRINTf32N:
920     case MVE_VRINTf32P:
921     case MVE_VRINTf32X:
922     case MVE_VRINTf32Z:
923     case MVE_VRMULHs32:
924     case MVE_VRMULHs16:
925     case MVE_VRMULHs8:
926     case MVE_VRMULHu32:
927     case MVE_VRMULHu16:
928     case MVE_VRMULHu8:
929     case MVE_VRSHL_by_vecs16:
930     case MVE_VRSHL_by_vecs32:
931     case MVE_VRSHL_by_vecs8:
932     case MVE_VRSHL_by_vecu16:
933     case MVE_VRSHL_by_vecu32:
934     case MVE_VRSHL_by_vecu8:
935     case MVE_VRSHL_qrs16:
936     case MVE_VRSHL_qrs32:
937     case MVE_VRSHL_qrs8:
938     case MVE_VRSHL_qru16:
939     case MVE_VRSHL_qru32:
940     case MVE_VRSHL_qru8:
941     case MVE_VRSHR_imms16:
942     case MVE_VRSHR_imms32:
943     case MVE_VRSHR_imms8:
944     case MVE_VRSHR_immu16:
945     case MVE_VRSHR_immu32:
946     case MVE_VRSHR_immu8:
947     case MVE_VRSHRNi16bh:
948     case MVE_VRSHRNi16th:
949     case MVE_VRSHRNi32bh:
950     case MVE_VRSHRNi32th:
951     case MVE_VSHL_by_vecs16:
952     case MVE_VSHL_by_vecs32:
953     case MVE_VSHL_by_vecs8:
954     case MVE_VSHL_by_vecu16:
955     case MVE_VSHL_by_vecu32:
956     case MVE_VSHL_by_vecu8:
957     case MVE_VSHL_immi16:
958     case MVE_VSHL_immi32:
959     case MVE_VSHL_immi8:
960     case MVE_VSHL_qrs16:
961     case MVE_VSHL_qrs32:
962     case MVE_VSHL_qrs8:
963     case MVE_VSHL_qru16:
964     case MVE_VSHL_qru32:
965     case MVE_VSHL_qru8:
966     case MVE_VSHR_imms16:
967     case MVE_VSHR_imms32:
968     case MVE_VSHR_imms8:
969     case MVE_VSHR_immu16:
970     case MVE_VSHR_immu32:
971     case MVE_VSHR_immu8:
972     case MVE_VSHRNi16bh:
973     case MVE_VSHRNi16th:
974     case MVE_VSHRNi32bh:
975     case MVE_VSHRNi32th:
976     case MVE_VSLIimm16:
977     case MVE_VSLIimm32:
978     case MVE_VSLIimm8:
979     case MVE_VSRIimm16:
980     case MVE_VSRIimm32:
981     case MVE_VSRIimm8:
982     case MVE_VSTRB16:
983     case MVE_VSTRB16_post:
984     case MVE_VSTRB16_pre:
985     case MVE_VSTRB16_rq:
986     case MVE_VSTRB32:
987     case MVE_VSTRB32_post:
988     case MVE_VSTRB32_pre:
989     case MVE_VSTRB32_rq:
990     case MVE_VSTRB8_rq:
991     case MVE_VSTRBU8:
992     case MVE_VSTRBU8_post:
993     case MVE_VSTRBU8_pre:
994     case MVE_VSTRD64_qi:
995     case MVE_VSTRD64_qi_pre:
996     case MVE_VSTRD64_rq:
997     case MVE_VSTRD64_rq_u:
998     case MVE_VSTRH16_rq:
999     case MVE_VSTRH16_rq_u:
1000     case MVE_VSTRH32:
1001     case MVE_VSTRH32_post:
1002     case MVE_VSTRH32_pre:
1003     case MVE_VSTRH32_rq:
1004     case MVE_VSTRH32_rq_u:
1005     case MVE_VSTRHU16:
1006     case MVE_VSTRHU16_post:
1007     case MVE_VSTRHU16_pre:
1008     case MVE_VSTRW32_qi:
1009     case MVE_VSTRW32_qi_pre:
1010     case MVE_VSTRW32_rq:
1011     case MVE_VSTRW32_rq_u:
1012     case MVE_VSTRWU32:
1013     case MVE_VSTRWU32_post:
1014     case MVE_VSTRWU32_pre:
1015     case MVE_VSUB_qr_f16:
1016     case MVE_VSUB_qr_f32:
1017     case MVE_VSUB_qr_i16:
1018     case MVE_VSUB_qr_i32:
1019     case MVE_VSUB_qr_i8:
1020     case MVE_VSUBf16:
1021     case MVE_VSUBf32:
1022     case MVE_VSUBi16:
1023     case MVE_VSUBi32:
1024     case MVE_VSUBi8:
1025     case VLDR_P0_off:
1026     case VLDR_P0_post:
1027     case VLDR_P0_pre:
1028     case VLDR_VPR_off:
1029     case VLDR_VPR_post:
1030     case VLDR_VPR_pre:
1031     case VSTR_P0_off:
1032     case VSTR_P0_post:
1033     case VSTR_P0_pre:
1034     case VSTR_VPR_off:
1035     case VSTR_VPR_post:
1036     case VSTR_VPR_pre:
1037     case VMRS_P0:
1038     case VMRS_VPR:
1039       return true;
1040     }
1041   };
1042 
1043   LLVMInitializeARMTargetInfo();
1044   LLVMInitializeARMTarget();
1045   LLVMInitializeARMTargetMC();
1046 
1047   auto TT(Triple::normalize("thumbv8.1m.main-none-none-eabi"));
1048   std::string Error;
1049   const Target *T = TargetRegistry::lookupTarget(TT, Error);
1050   if (!T) {
1051     dbgs() << Error;
1052     return;
1053   }
1054 
1055   TargetOptions Options;
1056   auto TM = std::unique_ptr<LLVMTargetMachine>(
1057     static_cast<LLVMTargetMachine*>(
1058       T->createTargetMachine(TT, "generic", "", Options, None, None,
1059                              CodeGenOpt::Default)));
1060   ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
1061                   std::string(TM->getTargetFeatureString()),
1062                   *static_cast<const ARMBaseTargetMachine *>(TM.get()), false);
1063 
1064   auto MII = TM->getMCInstrInfo();
1065   for (unsigned i = 0; i < ARM::INSTRUCTION_LIST_END; ++i) {
1066     uint64_t Flags = MII->get(i).TSFlags;
1067     if ((Flags & ARMII::DomainMask) != ARMII::DomainMVE)
1068       continue;
1069     bool Valid = (Flags & ARMII::ValidForTailPredication) != 0;
1070     ASSERT_EQ(IsValidTPOpcode(i), Valid)
1071               << MII->getName(i)
1072               << ": mismatched expectation for tail-predicated safety\n";
1073   }
1074 }
1075 
1076 TEST(MachineInstr, HasSideEffects) {
1077   using namespace ARM;
1078   std::set<unsigned> UnpredictableOpcodes = {
1079       // MVE Instructions
1080       MVE_VCTP8,
1081       MVE_VCTP16,
1082       MVE_VCTP32,
1083       MVE_VCTP64,
1084       MVE_VPST,
1085       MVE_VPTv16i8,
1086       MVE_VPTv8i16,
1087       MVE_VPTv4i32,
1088       MVE_VPTv16i8r,
1089       MVE_VPTv8i16r,
1090       MVE_VPTv4i32r,
1091       MVE_VPTv16s8,
1092       MVE_VPTv8s16,
1093       MVE_VPTv4s32,
1094       MVE_VPTv16s8r,
1095       MVE_VPTv8s16r,
1096       MVE_VPTv4s32r,
1097       MVE_VPTv16u8,
1098       MVE_VPTv8u16,
1099       MVE_VPTv4u32,
1100       MVE_VPTv16u8r,
1101       MVE_VPTv8u16r,
1102       MVE_VPTv4u32r,
1103       MVE_VPTv8f16,
1104       MVE_VPTv4f32,
1105       MVE_VPTv8f16r,
1106       MVE_VPTv4f32r,
1107       MVE_VADC,
1108       MVE_VADCI,
1109       MVE_VSBC,
1110       MVE_VSBCI,
1111       MVE_VSHLC,
1112       // FP Instructions
1113       FLDMXIA,
1114       FLDMXDB_UPD,
1115       FLDMXIA_UPD,
1116       FSTMXDB_UPD,
1117       FSTMXIA,
1118       FSTMXIA_UPD,
1119       VLDR_FPCXTNS_off,
1120       VLDR_FPCXTNS_off,
1121       VLDR_FPCXTNS_post,
1122       VLDR_FPCXTNS_pre,
1123       VLDR_FPCXTS_off,
1124       VLDR_FPCXTS_post,
1125       VLDR_FPCXTS_pre,
1126       VLDR_FPSCR_NZCVQC_off,
1127       VLDR_FPSCR_NZCVQC_post,
1128       VLDR_FPSCR_NZCVQC_pre,
1129       VLDR_FPSCR_off,
1130       VLDR_FPSCR_post,
1131       VLDR_FPSCR_pre,
1132       VLDR_P0_off,
1133       VLDR_P0_post,
1134       VLDR_P0_pre,
1135       VLDR_VPR_off,
1136       VLDR_VPR_post,
1137       VLDR_VPR_pre,
1138       VLLDM,
1139       VLSTM,
1140       VMRS,
1141       VMRS_FPCXTNS,
1142       VMRS_FPCXTS,
1143       VMRS_FPEXC,
1144       VMRS_FPINST,
1145       VMRS_FPINST2,
1146       VMRS_FPSCR_NZCVQC,
1147       VMRS_FPSID,
1148       VMRS_MVFR0,
1149       VMRS_MVFR1,
1150       VMRS_MVFR2,
1151       VMRS_P0,
1152       VMRS_VPR,
1153       VMSR,
1154       VMSR_FPCXTNS,
1155       VMSR_FPCXTS,
1156       VMSR_FPEXC,
1157       VMSR_FPINST,
1158       VMSR_FPINST2,
1159       VMSR_FPSCR_NZCVQC,
1160       VMSR_FPSID,
1161       VMSR_P0,
1162       VMSR_VPR,
1163       VSCCLRMD,
1164       VSCCLRMS,
1165       VSTR_FPCXTNS_off,
1166       VSTR_FPCXTNS_post,
1167       VSTR_FPCXTNS_pre,
1168       VSTR_FPCXTS_off,
1169       VSTR_FPCXTS_post,
1170       VSTR_FPCXTS_pre,
1171       VSTR_FPSCR_NZCVQC_off,
1172       VSTR_FPSCR_NZCVQC_post,
1173       VSTR_FPSCR_NZCVQC_pre,
1174       VSTR_FPSCR_off,
1175       VSTR_FPSCR_post,
1176       VSTR_FPSCR_pre,
1177       VSTR_P0_off,
1178       VSTR_P0_post,
1179       VSTR_P0_pre,
1180       VSTR_VPR_off,
1181       VSTR_VPR_post,
1182       VSTR_VPR_pre,
1183   };
1184 
1185   LLVMInitializeARMTargetInfo();
1186   LLVMInitializeARMTarget();
1187   LLVMInitializeARMTargetMC();
1188 
1189   auto TT(Triple::normalize("thumbv8.1m.main-none-none-eabi"));
1190   std::string Error;
1191   const Target *T = TargetRegistry::lookupTarget(TT, Error);
1192   if (!T) {
1193     dbgs() << Error;
1194     return;
1195   }
1196 
1197   TargetOptions Options;
1198   auto TM = std::unique_ptr<LLVMTargetMachine>(
1199       static_cast<LLVMTargetMachine *>(T->createTargetMachine(
1200           TT, "generic", "", Options, None, None, CodeGenOpt::Default)));
1201   ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
1202                   std::string(TM->getTargetFeatureString()),
1203                   *static_cast<const ARMBaseTargetMachine *>(TM.get()), false);
1204   const ARMBaseInstrInfo *TII = ST.getInstrInfo();
1205   auto MII = TM->getMCInstrInfo();
1206 
1207   for (unsigned Op = 0; Op < ARM::INSTRUCTION_LIST_END; ++Op) {
1208     const MCInstrDesc &Desc = TII->get(Op);
1209     if ((Desc.TSFlags &
1210          (ARMII::DomainMVE | ARMII::DomainVFP | ARMII::DomainNEONA8)) == 0)
1211       continue;
1212     if (UnpredictableOpcodes.count(Op))
1213       continue;
1214 
1215     ASSERT_FALSE(Desc.hasUnmodeledSideEffects())
1216         << MII->getName(Op) << " has unexpected side effects";
1217   }
1218 }
1219 
1220 TEST(MachineInstr, MVEVecSize) {
1221   using namespace ARM;
1222   auto MVEVecSize = [](unsigned Opcode) {
1223     switch (Opcode) {
1224     default:
1225     dbgs() << Opcode << "\n";
1226       llvm_unreachable("Unexpected MVE instruction!");
1227     case MVE_ASRLi:
1228     case MVE_ASRLr:
1229     case MVE_LSLLi:
1230     case MVE_LSLLr:
1231     case MVE_LSRL:
1232     case MVE_SQRSHR:
1233     case MVE_SQRSHRL:
1234     case MVE_SQSHL:
1235     case MVE_SQSHLL:
1236     case MVE_SRSHR:
1237     case MVE_SRSHRL:
1238     case MVE_UQRSHL:
1239     case MVE_UQRSHLL:
1240     case MVE_UQSHL:
1241     case MVE_UQSHLL:
1242     case MVE_URSHR:
1243     case MVE_URSHRL:
1244     case MVE_VABAVs8:
1245     case MVE_VABAVu8:
1246     case MVE_VABDs8:
1247     case MVE_VABDu8:
1248     case MVE_VABSs8:
1249     case MVE_VADDVs8acc:
1250     case MVE_VADDVs8no_acc:
1251     case MVE_VADDVu8acc:
1252     case MVE_VADDVu8no_acc:
1253     case MVE_VADD_qr_i8:
1254     case MVE_VADDi8:
1255     case MVE_VBRSR8:
1256     case MVE_VCADDi8:
1257     case MVE_VCLSs8:
1258     case MVE_VCLZs8:
1259     case MVE_VCMPi8:
1260     case MVE_VCMPi8r:
1261     case MVE_VCMPs8:
1262     case MVE_VCMPs8r:
1263     case MVE_VCMPu8:
1264     case MVE_VCMPu8r:
1265     case MVE_VCTP8:
1266     case MVE_VDDUPu8:
1267     case MVE_VDUP8:
1268     case MVE_VDWDUPu8:
1269     case MVE_VHADD_qr_s8:
1270     case MVE_VHADD_qr_u8:
1271     case MVE_VHADDs8:
1272     case MVE_VHADDu8:
1273     case MVE_VHCADDs8:
1274     case MVE_VHSUB_qr_s8:
1275     case MVE_VHSUB_qr_u8:
1276     case MVE_VHSUBs8:
1277     case MVE_VHSUBu8:
1278     case MVE_VIDUPu8:
1279     case MVE_VIWDUPu8:
1280     case MVE_VLD20_8:
1281     case MVE_VLD20_8_wb:
1282     case MVE_VLD21_8:
1283     case MVE_VLD21_8_wb:
1284     case MVE_VLD40_8:
1285     case MVE_VLD40_8_wb:
1286     case MVE_VLD41_8:
1287     case MVE_VLD41_8_wb:
1288     case MVE_VLD42_8:
1289     case MVE_VLD42_8_wb:
1290     case MVE_VLD43_8:
1291     case MVE_VLD43_8_wb:
1292     case MVE_VLDRBU8:
1293     case MVE_VLDRBU8_post:
1294     case MVE_VLDRBU8_pre:
1295     case MVE_VLDRBU8_rq:
1296     case MVE_VMAXAVs8:
1297     case MVE_VMAXAs8:
1298     case MVE_VMAXVs8:
1299     case MVE_VMAXVu8:
1300     case MVE_VMAXs8:
1301     case MVE_VMAXu8:
1302     case MVE_VMINAVs8:
1303     case MVE_VMINAs8:
1304     case MVE_VMINVs8:
1305     case MVE_VMINVu8:
1306     case MVE_VMINs8:
1307     case MVE_VMINu8:
1308     case MVE_VMLADAVas8:
1309     case MVE_VMLADAVau8:
1310     case MVE_VMLADAVaxs8:
1311     case MVE_VMLADAVs8:
1312     case MVE_VMLADAVu8:
1313     case MVE_VMLADAVxs8:
1314     case MVE_VMLAS_qr_s8:
1315     case MVE_VMLAS_qr_u8:
1316     case MVE_VMLA_qr_s8:
1317     case MVE_VMLA_qr_u8:
1318     case MVE_VMLSDAVas8:
1319     case MVE_VMLSDAVaxs8:
1320     case MVE_VMLSDAVs8:
1321     case MVE_VMLSDAVxs8:
1322     case MVE_VMOV_from_lane_s8:
1323     case MVE_VMOV_from_lane_u8:
1324     case MVE_VMOV_to_lane_8:
1325     case MVE_VMOVimmi8:
1326     case MVE_VMULHs8:
1327     case MVE_VMULHu8:
1328     case MVE_VMUL_qr_i8:
1329     case MVE_VMULi8:
1330     case MVE_VNEGs8:
1331     case MVE_VPTv16i8:
1332     case MVE_VPTv16i8r:
1333     case MVE_VPTv16s8:
1334     case MVE_VPTv16s8r:
1335     case MVE_VPTv16u8:
1336     case MVE_VPTv16u8r:
1337     case MVE_VQABSs8:
1338     case MVE_VQADD_qr_s8:
1339     case MVE_VQADD_qr_u8:
1340     case MVE_VQADDs8:
1341     case MVE_VQADDu8:
1342     case MVE_VQDMLADHXs8:
1343     case MVE_VQDMLADHs8:
1344     case MVE_VQDMLAH_qrs8:
1345     case MVE_VQDMLASH_qrs8:
1346     case MVE_VQDMLSDHXs8:
1347     case MVE_VQDMLSDHs8:
1348     case MVE_VQDMULH_qr_s8:
1349     case MVE_VQDMULHi8:
1350     case MVE_VQNEGs8:
1351     case MVE_VQRDMLADHXs8:
1352     case MVE_VQRDMLADHs8:
1353     case MVE_VQRDMLAH_qrs8:
1354     case MVE_VQRDMLASH_qrs8:
1355     case MVE_VQRDMLSDHXs8:
1356     case MVE_VQRDMLSDHs8:
1357     case MVE_VQRDMULH_qr_s8:
1358     case MVE_VQRDMULHi8:
1359     case MVE_VQRSHL_by_vecs8:
1360     case MVE_VQRSHL_by_vecu8:
1361     case MVE_VQRSHL_qrs8:
1362     case MVE_VQRSHL_qru8:
1363     case MVE_VQSHLU_imms8:
1364     case MVE_VQSHL_by_vecs8:
1365     case MVE_VQSHL_by_vecu8:
1366     case MVE_VQSHL_qrs8:
1367     case MVE_VQSHL_qru8:
1368     case MVE_VQSHLimms8:
1369     case MVE_VQSHLimmu8:
1370     case MVE_VQSUB_qr_s8:
1371     case MVE_VQSUB_qr_u8:
1372     case MVE_VQSUBs8:
1373     case MVE_VQSUBu8:
1374     case MVE_VRHADDs8:
1375     case MVE_VRHADDu8:
1376     case MVE_VRMULHs8:
1377     case MVE_VRMULHu8:
1378     case MVE_VRSHL_by_vecs8:
1379     case MVE_VRSHL_by_vecu8:
1380     case MVE_VRSHL_qrs8:
1381     case MVE_VRSHL_qru8:
1382     case MVE_VRSHR_imms8:
1383     case MVE_VRSHR_immu8:
1384     case MVE_VSHL_by_vecs8:
1385     case MVE_VSHL_by_vecu8:
1386     case MVE_VSHL_immi8:
1387     case MVE_VSHL_qru8:
1388     case MVE_VSHL_qrs8:
1389     case MVE_VSHR_imms8:
1390     case MVE_VSHR_immu8:
1391     case MVE_VSLIimm8:
1392     case MVE_VSRIimm8:
1393     case MVE_VST20_8:
1394     case MVE_VST20_8_wb:
1395     case MVE_VST21_8:
1396     case MVE_VST21_8_wb:
1397     case MVE_VST40_8:
1398     case MVE_VST40_8_wb:
1399     case MVE_VST41_8:
1400     case MVE_VST41_8_wb:
1401     case MVE_VST42_8:
1402     case MVE_VST42_8_wb:
1403     case MVE_VST43_8:
1404     case MVE_VST43_8_wb:
1405     case MVE_VSTRB8_rq:
1406     case MVE_VSTRBU8:
1407     case MVE_VSTRBU8_post:
1408     case MVE_VSTRBU8_pre:
1409     case MVE_VSUB_qr_i8:
1410     case MVE_VSUBi8:
1411     case MVE_VAND:
1412     case MVE_VBIC:
1413     case MVE_VEOR:
1414     case MVE_VMVN:
1415     case MVE_VORN:
1416     case MVE_VORR:
1417     case MVE_VPNOT:
1418     case MVE_VPSEL:
1419     case MVE_VPST:
1420     case MQPRCopy:
1421       return 0;
1422     case MVE_VABAVs16:
1423     case MVE_VABAVu16:
1424     case MVE_VABDf16:
1425     case MVE_VABDs16:
1426     case MVE_VABDu16:
1427     case MVE_VABSf16:
1428     case MVE_VABSs16:
1429     case MVE_VADDVs16acc:
1430     case MVE_VADDVs16no_acc:
1431     case MVE_VADDVu16acc:
1432     case MVE_VADDVu16no_acc:
1433     case MVE_VADD_qr_f16:
1434     case MVE_VADD_qr_i16:
1435     case MVE_VADDf16:
1436     case MVE_VADDi16:
1437     case MVE_VBICimmi16:
1438     case MVE_VBRSR16:
1439     case MVE_VCADDf16:
1440     case MVE_VCADDi16:
1441     case MVE_VCLSs16:
1442     case MVE_VCLZs16:
1443     case MVE_VCMLAf16:
1444     case MVE_VCMPf16:
1445     case MVE_VCMPf16r:
1446     case MVE_VCMPi16:
1447     case MVE_VCMPi16r:
1448     case MVE_VCMPs16:
1449     case MVE_VCMPs16r:
1450     case MVE_VCMPu16:
1451     case MVE_VCMPu16r:
1452     case MVE_VCMULf16:
1453     case MVE_VCTP16:
1454     case MVE_VCVTf16s16_fix:
1455     case MVE_VCVTf16s16n:
1456     case MVE_VCVTf16u16_fix:
1457     case MVE_VCVTf16u16n:
1458     case MVE_VCVTs16f16_fix:
1459     case MVE_VCVTs16f16a:
1460     case MVE_VCVTs16f16m:
1461     case MVE_VCVTs16f16n:
1462     case MVE_VCVTs16f16p:
1463     case MVE_VCVTs16f16z:
1464     case MVE_VCVTu16f16_fix:
1465     case MVE_VCVTu16f16a:
1466     case MVE_VCVTu16f16m:
1467     case MVE_VCVTu16f16n:
1468     case MVE_VCVTu16f16p:
1469     case MVE_VCVTu16f16z:
1470     case MVE_VDDUPu16:
1471     case MVE_VDUP16:
1472     case MVE_VDWDUPu16:
1473     case MVE_VFMA_qr_Sf16:
1474     case MVE_VFMA_qr_f16:
1475     case MVE_VFMAf16:
1476     case MVE_VFMSf16:
1477     case MVE_VHADD_qr_s16:
1478     case MVE_VHADD_qr_u16:
1479     case MVE_VHADDs16:
1480     case MVE_VHADDu16:
1481     case MVE_VHCADDs16:
1482     case MVE_VHSUB_qr_s16:
1483     case MVE_VHSUB_qr_u16:
1484     case MVE_VHSUBs16:
1485     case MVE_VHSUBu16:
1486     case MVE_VIDUPu16:
1487     case MVE_VIWDUPu16:
1488     case MVE_VLD20_16:
1489     case MVE_VLD20_16_wb:
1490     case MVE_VLD21_16:
1491     case MVE_VLD21_16_wb:
1492     case MVE_VLD40_16:
1493     case MVE_VLD40_16_wb:
1494     case MVE_VLD41_16:
1495     case MVE_VLD41_16_wb:
1496     case MVE_VLD42_16:
1497     case MVE_VLD42_16_wb:
1498     case MVE_VLD43_16:
1499     case MVE_VLD43_16_wb:
1500     case MVE_VLDRBS16:
1501     case MVE_VLDRBS16_post:
1502     case MVE_VLDRBS16_pre:
1503     case MVE_VLDRBS16_rq:
1504     case MVE_VLDRBU16:
1505     case MVE_VLDRBU16_post:
1506     case MVE_VLDRBU16_pre:
1507     case MVE_VLDRBU16_rq:
1508     case MVE_VLDRHU16:
1509     case MVE_VLDRHU16_post:
1510     case MVE_VLDRHU16_pre:
1511     case MVE_VLDRHU16_rq:
1512     case MVE_VLDRHU16_rq_u:
1513     case MVE_VMAXAVs16:
1514     case MVE_VMAXAs16:
1515     case MVE_VMAXNMAVf16:
1516     case MVE_VMAXNMAf16:
1517     case MVE_VMAXNMVf16:
1518     case MVE_VMAXNMf16:
1519     case MVE_VMAXVs16:
1520     case MVE_VMAXVu16:
1521     case MVE_VMAXs16:
1522     case MVE_VMAXu16:
1523     case MVE_VMINAVs16:
1524     case MVE_VMINAs16:
1525     case MVE_VMINNMAVf16:
1526     case MVE_VMINNMAf16:
1527     case MVE_VMINNMVf16:
1528     case MVE_VMINNMf16:
1529     case MVE_VMINVs16:
1530     case MVE_VMINVu16:
1531     case MVE_VMINs16:
1532     case MVE_VMINu16:
1533     case MVE_VMLADAVas16:
1534     case MVE_VMLADAVau16:
1535     case MVE_VMLADAVaxs16:
1536     case MVE_VMLADAVs16:
1537     case MVE_VMLADAVu16:
1538     case MVE_VMLADAVxs16:
1539     case MVE_VMLALDAVas16:
1540     case MVE_VMLALDAVau16:
1541     case MVE_VMLALDAVaxs16:
1542     case MVE_VMLALDAVs16:
1543     case MVE_VMLALDAVu16:
1544     case MVE_VMLALDAVxs16:
1545     case MVE_VMLAS_qr_s16:
1546     case MVE_VMLAS_qr_u16:
1547     case MVE_VMLA_qr_s16:
1548     case MVE_VMLA_qr_u16:
1549     case MVE_VMLSDAVas16:
1550     case MVE_VMLSDAVaxs16:
1551     case MVE_VMLSDAVs16:
1552     case MVE_VMLSDAVxs16:
1553     case MVE_VMLSLDAVas16:
1554     case MVE_VMLSLDAVaxs16:
1555     case MVE_VMLSLDAVs16:
1556     case MVE_VMLSLDAVxs16:
1557     case MVE_VMOVNi16bh:
1558     case MVE_VMOVNi16th:
1559     case MVE_VMOV_from_lane_s16:
1560     case MVE_VMOV_from_lane_u16:
1561     case MVE_VMOV_to_lane_16:
1562     case MVE_VMOVimmi16:
1563     case MVE_VMOVLs8bh:
1564     case MVE_VMOVLs8th:
1565     case MVE_VMOVLu8bh:
1566     case MVE_VMOVLu8th:
1567     case MVE_VMULLBp8:
1568     case MVE_VMULLBs8:
1569     case MVE_VMULLBu8:
1570     case MVE_VMULLTp8:
1571     case MVE_VMULLTs8:
1572     case MVE_VMULLTu8:
1573     case MVE_VMULHs16:
1574     case MVE_VMULHu16:
1575     case MVE_VMUL_qr_f16:
1576     case MVE_VMUL_qr_i16:
1577     case MVE_VMULf16:
1578     case MVE_VMULi16:
1579     case MVE_VMVNimmi16:
1580     case MVE_VNEGf16:
1581     case MVE_VNEGs16:
1582     case MVE_VORRimmi16:
1583     case MVE_VPTv8f16:
1584     case MVE_VPTv8f16r:
1585     case MVE_VPTv8i16:
1586     case MVE_VPTv8i16r:
1587     case MVE_VPTv8s16:
1588     case MVE_VPTv8s16r:
1589     case MVE_VPTv8u16:
1590     case MVE_VPTv8u16r:
1591     case MVE_VQABSs16:
1592     case MVE_VQADD_qr_s16:
1593     case MVE_VQADD_qr_u16:
1594     case MVE_VQADDs16:
1595     case MVE_VQADDu16:
1596     case MVE_VQDMLADHXs16:
1597     case MVE_VQDMLADHs16:
1598     case MVE_VQDMLAH_qrs16:
1599     case MVE_VQDMLASH_qrs16:
1600     case MVE_VQDMLSDHXs16:
1601     case MVE_VQDMLSDHs16:
1602     case MVE_VQDMULH_qr_s16:
1603     case MVE_VQDMULHi16:
1604     case MVE_VQDMULL_qr_s16bh:
1605     case MVE_VQDMULL_qr_s16th:
1606     case MVE_VQDMULLs16bh:
1607     case MVE_VQDMULLs16th:
1608     case MVE_VQMOVNs16bh:
1609     case MVE_VQMOVNs16th:
1610     case MVE_VQMOVNu16bh:
1611     case MVE_VQMOVNu16th:
1612     case MVE_VQMOVUNs16bh:
1613     case MVE_VQMOVUNs16th:
1614     case MVE_VQNEGs16:
1615     case MVE_VQRDMLADHXs16:
1616     case MVE_VQRDMLADHs16:
1617     case MVE_VQRDMLAH_qrs16:
1618     case MVE_VQRDMLASH_qrs16:
1619     case MVE_VQRDMLSDHXs16:
1620     case MVE_VQRDMLSDHs16:
1621     case MVE_VQRDMULH_qr_s16:
1622     case MVE_VQRDMULHi16:
1623     case MVE_VQRSHL_by_vecs16:
1624     case MVE_VQRSHL_by_vecu16:
1625     case MVE_VQRSHL_qrs16:
1626     case MVE_VQRSHL_qru16:
1627     case MVE_VQRSHRNbhs16:
1628     case MVE_VQRSHRNbhu16:
1629     case MVE_VQRSHRNths16:
1630     case MVE_VQRSHRNthu16:
1631     case MVE_VQRSHRUNs16bh:
1632     case MVE_VQRSHRUNs16th:
1633     case MVE_VQSHLU_imms16:
1634     case MVE_VQSHL_by_vecs16:
1635     case MVE_VQSHL_by_vecu16:
1636     case MVE_VQSHL_qrs16:
1637     case MVE_VQSHL_qru16:
1638     case MVE_VQSHLimms16:
1639     case MVE_VQSHLimmu16:
1640     case MVE_VQSHRNbhs16:
1641     case MVE_VQSHRNbhu16:
1642     case MVE_VQSHRNths16:
1643     case MVE_VQSHRNthu16:
1644     case MVE_VQSHRUNs16bh:
1645     case MVE_VQSHRUNs16th:
1646     case MVE_VQSUB_qr_s16:
1647     case MVE_VQSUB_qr_u16:
1648     case MVE_VQSUBs16:
1649     case MVE_VQSUBu16:
1650     case MVE_VREV16_8:
1651     case MVE_VRHADDs16:
1652     case MVE_VRHADDu16:
1653     case MVE_VRINTf16A:
1654     case MVE_VRINTf16M:
1655     case MVE_VRINTf16N:
1656     case MVE_VRINTf16P:
1657     case MVE_VRINTf16X:
1658     case MVE_VRINTf16Z:
1659     case MVE_VRMULHs16:
1660     case MVE_VRMULHu16:
1661     case MVE_VRSHL_by_vecs16:
1662     case MVE_VRSHL_by_vecu16:
1663     case MVE_VRSHL_qrs16:
1664     case MVE_VRSHL_qru16:
1665     case MVE_VRSHRNi16bh:
1666     case MVE_VRSHRNi16th:
1667     case MVE_VRSHR_imms16:
1668     case MVE_VRSHR_immu16:
1669     case MVE_VSHLL_imms8bh:
1670     case MVE_VSHLL_imms8th:
1671     case MVE_VSHLL_immu8bh:
1672     case MVE_VSHLL_immu8th:
1673     case MVE_VSHLL_lws8bh:
1674     case MVE_VSHLL_lws8th:
1675     case MVE_VSHLL_lwu8bh:
1676     case MVE_VSHLL_lwu8th:
1677     case MVE_VSHL_by_vecs16:
1678     case MVE_VSHL_by_vecu16:
1679     case MVE_VSHL_immi16:
1680     case MVE_VSHL_qrs16:
1681     case MVE_VSHL_qru16:
1682     case MVE_VSHRNi16bh:
1683     case MVE_VSHRNi16th:
1684     case MVE_VSHR_imms16:
1685     case MVE_VSHR_immu16:
1686     case MVE_VSLIimm16:
1687     case MVE_VSRIimm16:
1688     case MVE_VST20_16:
1689     case MVE_VST20_16_wb:
1690     case MVE_VST21_16:
1691     case MVE_VST21_16_wb:
1692     case MVE_VST40_16:
1693     case MVE_VST40_16_wb:
1694     case MVE_VST41_16:
1695     case MVE_VST41_16_wb:
1696     case MVE_VST42_16:
1697     case MVE_VST42_16_wb:
1698     case MVE_VST43_16:
1699     case MVE_VST43_16_wb:
1700     case MVE_VSTRB16:
1701     case MVE_VSTRB16_post:
1702     case MVE_VSTRB16_pre:
1703     case MVE_VSTRB16_rq:
1704     case MVE_VSTRH16_rq:
1705     case MVE_VSTRH16_rq_u:
1706     case MVE_VSTRHU16:
1707     case MVE_VSTRHU16_post:
1708     case MVE_VSTRHU16_pre:
1709     case MVE_VSUB_qr_f16:
1710     case MVE_VSUB_qr_i16:
1711     case MVE_VSUBf16:
1712     case MVE_VSUBi16:
1713       return 1;
1714     case MVE_VABAVs32:
1715     case MVE_VABAVu32:
1716     case MVE_VABDf32:
1717     case MVE_VABDs32:
1718     case MVE_VABDu32:
1719     case MVE_VABSf32:
1720     case MVE_VABSs32:
1721     case MVE_VADC:
1722     case MVE_VADCI:
1723     case MVE_VADDLVs32acc:
1724     case MVE_VADDLVs32no_acc:
1725     case MVE_VADDLVu32acc:
1726     case MVE_VADDLVu32no_acc:
1727     case MVE_VADDVs32acc:
1728     case MVE_VADDVs32no_acc:
1729     case MVE_VADDVu32acc:
1730     case MVE_VADDVu32no_acc:
1731     case MVE_VADD_qr_f32:
1732     case MVE_VADD_qr_i32:
1733     case MVE_VADDf32:
1734     case MVE_VADDi32:
1735     case MVE_VBICimmi32:
1736     case MVE_VBRSR32:
1737     case MVE_VCADDf32:
1738     case MVE_VCADDi32:
1739     case MVE_VCLSs32:
1740     case MVE_VCLZs32:
1741     case MVE_VCMLAf32:
1742     case MVE_VCMPf32:
1743     case MVE_VCMPf32r:
1744     case MVE_VCMPi32:
1745     case MVE_VCMPi32r:
1746     case MVE_VCMPs32:
1747     case MVE_VCMPs32r:
1748     case MVE_VCMPu32:
1749     case MVE_VCMPu32r:
1750     case MVE_VCMULf32:
1751     case MVE_VCTP32:
1752     case MVE_VCVTf16f32bh:
1753     case MVE_VCVTf16f32th:
1754     case MVE_VCVTf32f16bh:
1755     case MVE_VCVTf32f16th:
1756     case MVE_VCVTf32s32_fix:
1757     case MVE_VCVTf32s32n:
1758     case MVE_VCVTf32u32_fix:
1759     case MVE_VCVTf32u32n:
1760     case MVE_VCVTs32f32_fix:
1761     case MVE_VCVTs32f32a:
1762     case MVE_VCVTs32f32m:
1763     case MVE_VCVTs32f32n:
1764     case MVE_VCVTs32f32p:
1765     case MVE_VCVTs32f32z:
1766     case MVE_VCVTu32f32_fix:
1767     case MVE_VCVTu32f32a:
1768     case MVE_VCVTu32f32m:
1769     case MVE_VCVTu32f32n:
1770     case MVE_VCVTu32f32p:
1771     case MVE_VCVTu32f32z:
1772     case MVE_VDDUPu32:
1773     case MVE_VDUP32:
1774     case MVE_VDWDUPu32:
1775     case MVE_VFMA_qr_Sf32:
1776     case MVE_VFMA_qr_f32:
1777     case MVE_VFMAf32:
1778     case MVE_VFMSf32:
1779     case MVE_VHADD_qr_s32:
1780     case MVE_VHADD_qr_u32:
1781     case MVE_VHADDs32:
1782     case MVE_VHADDu32:
1783     case MVE_VHCADDs32:
1784     case MVE_VHSUB_qr_s32:
1785     case MVE_VHSUB_qr_u32:
1786     case MVE_VHSUBs32:
1787     case MVE_VHSUBu32:
1788     case MVE_VIDUPu32:
1789     case MVE_VIWDUPu32:
1790     case MVE_VLD20_32:
1791     case MVE_VLD20_32_wb:
1792     case MVE_VLD21_32:
1793     case MVE_VLD21_32_wb:
1794     case MVE_VLD40_32:
1795     case MVE_VLD40_32_wb:
1796     case MVE_VLD41_32:
1797     case MVE_VLD41_32_wb:
1798     case MVE_VLD42_32:
1799     case MVE_VLD42_32_wb:
1800     case MVE_VLD43_32:
1801     case MVE_VLD43_32_wb:
1802     case MVE_VLDRBS32:
1803     case MVE_VLDRBS32_post:
1804     case MVE_VLDRBS32_pre:
1805     case MVE_VLDRBS32_rq:
1806     case MVE_VLDRBU32:
1807     case MVE_VLDRBU32_post:
1808     case MVE_VLDRBU32_pre:
1809     case MVE_VLDRBU32_rq:
1810     case MVE_VLDRHS32:
1811     case MVE_VLDRHS32_post:
1812     case MVE_VLDRHS32_pre:
1813     case MVE_VLDRHS32_rq:
1814     case MVE_VLDRHS32_rq_u:
1815     case MVE_VLDRHU32:
1816     case MVE_VLDRHU32_post:
1817     case MVE_VLDRHU32_pre:
1818     case MVE_VLDRHU32_rq:
1819     case MVE_VLDRHU32_rq_u:
1820     case MVE_VLDRWU32:
1821     case MVE_VLDRWU32_post:
1822     case MVE_VLDRWU32_pre:
1823     case MVE_VLDRWU32_qi:
1824     case MVE_VLDRWU32_qi_pre:
1825     case MVE_VLDRWU32_rq:
1826     case MVE_VLDRWU32_rq_u:
1827     case MVE_VMAXAVs32:
1828     case MVE_VMAXAs32:
1829     case MVE_VMAXNMAVf32:
1830     case MVE_VMAXNMAf32:
1831     case MVE_VMAXNMVf32:
1832     case MVE_VMAXNMf32:
1833     case MVE_VMAXVs32:
1834     case MVE_VMAXVu32:
1835     case MVE_VMAXs32:
1836     case MVE_VMAXu32:
1837     case MVE_VMINAVs32:
1838     case MVE_VMINAs32:
1839     case MVE_VMINNMAVf32:
1840     case MVE_VMINNMAf32:
1841     case MVE_VMINNMVf32:
1842     case MVE_VMINNMf32:
1843     case MVE_VMINVs32:
1844     case MVE_VMINVu32:
1845     case MVE_VMINs32:
1846     case MVE_VMINu32:
1847     case MVE_VMLADAVas32:
1848     case MVE_VMLADAVau32:
1849     case MVE_VMLADAVaxs32:
1850     case MVE_VMLADAVs32:
1851     case MVE_VMLADAVu32:
1852     case MVE_VMLADAVxs32:
1853     case MVE_VMLALDAVas32:
1854     case MVE_VMLALDAVau32:
1855     case MVE_VMLALDAVaxs32:
1856     case MVE_VMLALDAVs32:
1857     case MVE_VMLALDAVu32:
1858     case MVE_VMLALDAVxs32:
1859     case MVE_VMLAS_qr_s32:
1860     case MVE_VMLAS_qr_u32:
1861     case MVE_VMLA_qr_s32:
1862     case MVE_VMLA_qr_u32:
1863     case MVE_VMLSDAVas32:
1864     case MVE_VMLSDAVaxs32:
1865     case MVE_VMLSDAVs32:
1866     case MVE_VMLSDAVxs32:
1867     case MVE_VMLSLDAVas32:
1868     case MVE_VMLSLDAVaxs32:
1869     case MVE_VMLSLDAVs32:
1870     case MVE_VMLSLDAVxs32:
1871     case MVE_VMOVNi32bh:
1872     case MVE_VMOVNi32th:
1873     case MVE_VMOV_from_lane_32:
1874     case MVE_VMOV_q_rr:
1875     case MVE_VMOV_rr_q:
1876     case MVE_VMOV_to_lane_32:
1877     case MVE_VMOVimmf32:
1878     case MVE_VMOVimmi32:
1879     case MVE_VMOVLs16bh:
1880     case MVE_VMOVLs16th:
1881     case MVE_VMOVLu16bh:
1882     case MVE_VMOVLu16th:
1883     case MVE_VMULHs32:
1884     case MVE_VMULHu32:
1885     case MVE_VMULLBp16:
1886     case MVE_VMULLBs16:
1887     case MVE_VMULLBu16:
1888     case MVE_VMULLTp16:
1889     case MVE_VMULLTs16:
1890     case MVE_VMULLTu16:
1891     case MVE_VMUL_qr_f32:
1892     case MVE_VMUL_qr_i32:
1893     case MVE_VMULf32:
1894     case MVE_VMULi32:
1895     case MVE_VMVNimmi32:
1896     case MVE_VNEGf32:
1897     case MVE_VNEGs32:
1898     case MVE_VORRimmi32:
1899     case MVE_VPTv4f32:
1900     case MVE_VPTv4f32r:
1901     case MVE_VPTv4i32:
1902     case MVE_VPTv4i32r:
1903     case MVE_VPTv4s32:
1904     case MVE_VPTv4s32r:
1905     case MVE_VPTv4u32:
1906     case MVE_VPTv4u32r:
1907     case MVE_VQABSs32:
1908     case MVE_VQADD_qr_s32:
1909     case MVE_VQADD_qr_u32:
1910     case MVE_VQADDs32:
1911     case MVE_VQADDu32:
1912     case MVE_VQDMLADHXs32:
1913     case MVE_VQDMLADHs32:
1914     case MVE_VQDMLAH_qrs32:
1915     case MVE_VQDMLASH_qrs32:
1916     case MVE_VQDMLSDHXs32:
1917     case MVE_VQDMLSDHs32:
1918     case MVE_VQDMULH_qr_s32:
1919     case MVE_VQDMULHi32:
1920     case MVE_VQDMULL_qr_s32bh:
1921     case MVE_VQDMULL_qr_s32th:
1922     case MVE_VQDMULLs32bh:
1923     case MVE_VQDMULLs32th:
1924     case MVE_VQMOVNs32bh:
1925     case MVE_VQMOVNs32th:
1926     case MVE_VQMOVNu32bh:
1927     case MVE_VQMOVNu32th:
1928     case MVE_VQMOVUNs32bh:
1929     case MVE_VQMOVUNs32th:
1930     case MVE_VQNEGs32:
1931     case MVE_VQRDMLADHXs32:
1932     case MVE_VQRDMLADHs32:
1933     case MVE_VQRDMLAH_qrs32:
1934     case MVE_VQRDMLASH_qrs32:
1935     case MVE_VQRDMLSDHXs32:
1936     case MVE_VQRDMLSDHs32:
1937     case MVE_VQRDMULH_qr_s32:
1938     case MVE_VQRDMULHi32:
1939     case MVE_VQRSHL_by_vecs32:
1940     case MVE_VQRSHL_by_vecu32:
1941     case MVE_VQRSHL_qrs32:
1942     case MVE_VQRSHL_qru32:
1943     case MVE_VQRSHRNbhs32:
1944     case MVE_VQRSHRNbhu32:
1945     case MVE_VQRSHRNths32:
1946     case MVE_VQRSHRNthu32:
1947     case MVE_VQRSHRUNs32bh:
1948     case MVE_VQRSHRUNs32th:
1949     case MVE_VQSHLU_imms32:
1950     case MVE_VQSHL_by_vecs32:
1951     case MVE_VQSHL_by_vecu32:
1952     case MVE_VQSHL_qrs32:
1953     case MVE_VQSHL_qru32:
1954     case MVE_VQSHLimms32:
1955     case MVE_VQSHLimmu32:
1956     case MVE_VQSHRNbhs32:
1957     case MVE_VQSHRNbhu32:
1958     case MVE_VQSHRNths32:
1959     case MVE_VQSHRNthu32:
1960     case MVE_VQSHRUNs32bh:
1961     case MVE_VQSHRUNs32th:
1962     case MVE_VQSUB_qr_s32:
1963     case MVE_VQSUB_qr_u32:
1964     case MVE_VQSUBs32:
1965     case MVE_VQSUBu32:
1966     case MVE_VREV32_16:
1967     case MVE_VREV32_8:
1968     case MVE_VRHADDs32:
1969     case MVE_VRHADDu32:
1970     case MVE_VRINTf32A:
1971     case MVE_VRINTf32M:
1972     case MVE_VRINTf32N:
1973     case MVE_VRINTf32P:
1974     case MVE_VRINTf32X:
1975     case MVE_VRINTf32Z:
1976     case MVE_VRMLALDAVHas32:
1977     case MVE_VRMLALDAVHau32:
1978     case MVE_VRMLALDAVHaxs32:
1979     case MVE_VRMLALDAVHs32:
1980     case MVE_VRMLALDAVHu32:
1981     case MVE_VRMLALDAVHxs32:
1982     case MVE_VRMLSLDAVHas32:
1983     case MVE_VRMLSLDAVHaxs32:
1984     case MVE_VRMLSLDAVHs32:
1985     case MVE_VRMLSLDAVHxs32:
1986     case MVE_VRMULHs32:
1987     case MVE_VRMULHu32:
1988     case MVE_VRSHL_by_vecs32:
1989     case MVE_VRSHL_by_vecu32:
1990     case MVE_VRSHL_qrs32:
1991     case MVE_VRSHL_qru32:
1992     case MVE_VRSHRNi32bh:
1993     case MVE_VRSHRNi32th:
1994     case MVE_VRSHR_imms32:
1995     case MVE_VRSHR_immu32:
1996     case MVE_VSBC:
1997     case MVE_VSBCI:
1998     case MVE_VSHLC:
1999     case MVE_VSHLL_imms16bh:
2000     case MVE_VSHLL_imms16th:
2001     case MVE_VSHLL_immu16bh:
2002     case MVE_VSHLL_immu16th:
2003     case MVE_VSHLL_lws16bh:
2004     case MVE_VSHLL_lws16th:
2005     case MVE_VSHLL_lwu16bh:
2006     case MVE_VSHLL_lwu16th:
2007     case MVE_VSHL_by_vecs32:
2008     case MVE_VSHL_by_vecu32:
2009     case MVE_VSHL_immi32:
2010     case MVE_VSHL_qrs32:
2011     case MVE_VSHL_qru32:
2012     case MVE_VSHRNi32bh:
2013     case MVE_VSHRNi32th:
2014     case MVE_VSHR_imms32:
2015     case MVE_VSHR_immu32:
2016     case MVE_VSLIimm32:
2017     case MVE_VSRIimm32:
2018     case MVE_VST20_32:
2019     case MVE_VST20_32_wb:
2020     case MVE_VST21_32:
2021     case MVE_VST21_32_wb:
2022     case MVE_VST40_32:
2023     case MVE_VST40_32_wb:
2024     case MVE_VST41_32:
2025     case MVE_VST41_32_wb:
2026     case MVE_VST42_32:
2027     case MVE_VST42_32_wb:
2028     case MVE_VST43_32:
2029     case MVE_VST43_32_wb:
2030     case MVE_VSTRB32:
2031     case MVE_VSTRB32_post:
2032     case MVE_VSTRB32_pre:
2033     case MVE_VSTRB32_rq:
2034     case MVE_VSTRH32:
2035     case MVE_VSTRH32_post:
2036     case MVE_VSTRH32_pre:
2037     case MVE_VSTRH32_rq:
2038     case MVE_VSTRH32_rq_u:
2039     case MVE_VSTRW32_qi:
2040     case MVE_VSTRW32_qi_pre:
2041     case MVE_VSTRW32_rq:
2042     case MVE_VSTRW32_rq_u:
2043     case MVE_VSTRWU32:
2044     case MVE_VSTRWU32_post:
2045     case MVE_VSTRWU32_pre:
2046     case MVE_VSUB_qr_f32:
2047     case MVE_VSUB_qr_i32:
2048     case MVE_VSUBf32:
2049     case MVE_VSUBi32:
2050       return 2;
2051     case MVE_VCTP64:
2052     case MVE_VLDRDU64_qi:
2053     case MVE_VLDRDU64_qi_pre:
2054     case MVE_VLDRDU64_rq:
2055     case MVE_VLDRDU64_rq_u:
2056     case MVE_VMULLBs32:
2057     case MVE_VMULLBu32:
2058     case MVE_VMULLTs32:
2059     case MVE_VMULLTu32:
2060     case MVE_VMOVimmi64:
2061     case MVE_VREV64_16:
2062     case MVE_VREV64_32:
2063     case MVE_VREV64_8:
2064     case MVE_VSTRD64_qi:
2065     case MVE_VSTRD64_qi_pre:
2066     case MVE_VSTRD64_rq:
2067     case MVE_VSTRD64_rq_u:
2068       return 3;
2069     }
2070   };
2071   LLVMInitializeARMTargetInfo();
2072   LLVMInitializeARMTarget();
2073   LLVMInitializeARMTargetMC();
2074 
2075   auto TT(Triple::normalize("thumbv8.1m.main-none-none-eabi"));
2076   std::string Error;
2077   const Target *T = TargetRegistry::lookupTarget(TT, Error);
2078   if (!T) {
2079     dbgs() << Error;
2080     return;
2081   }
2082 
2083   TargetOptions Options;
2084   auto TM = std::unique_ptr<LLVMTargetMachine>(
2085     static_cast<LLVMTargetMachine*>(
2086       T->createTargetMachine(TT, "generic", "", Options, None, None,
2087                              CodeGenOpt::Default)));
2088   ARMSubtarget ST(TM->getTargetTriple(), std::string(TM->getTargetCPU()),
2089                   std::string(TM->getTargetFeatureString()),
2090                   *static_cast<const ARMBaseTargetMachine *>(TM.get()), false);
2091 
2092   auto MII = TM->getMCInstrInfo();
2093   for (unsigned i = 0; i < ARM::INSTRUCTION_LIST_END; ++i) {
2094     uint64_t Flags = MII->get(i).TSFlags;
2095     if ((Flags & ARMII::DomainMask) != ARMII::DomainMVE)
2096       continue;
2097     int Size = (Flags & ARMII::VecSize) >> ARMII::VecSizeShift;
2098     ASSERT_EQ(MVEVecSize(i), Size)
2099               << MII->getName(i)
2100               << ": mismatched expectation for MVE vec size\n";
2101   }
2102 }
2103