xref: /llvm-project/llvm/unittests/Target/ARM/MachineInstrTest.cpp (revision 58991ba773774f7dbdf2844a737845298e9e71bb) 
1 #include "ARMBaseInstrInfo.h"
2 #include "ARMSubtarget.h"
3 #include "ARMTargetMachine.h"
4 #include "llvm/Support/TargetRegistry.h"
5 #include "llvm/Support/TargetSelect.h"
6 #include "llvm/Target/TargetMachine.h"
7 #include "llvm/Target/TargetOptions.h"
8 
9 #include "gtest/gtest.h"
10 
11 using namespace llvm;
12 
13 // Test for instructions that aren't immediately obviously valid within a
14 // tail-predicated loop. This should be marked up in their tablegen
15 // descriptions. Currently we, conservatively, disallow:
16 // - cross beat carries.
17 // - narrowing of results.
18 // - complex operations.
19 // - horizontal operations.
20 // - byte swapping.
21 // - interleaved memory instructions.
22 // TODO: Add to this list once we can handle them safely.
23 TEST(MachineInstrValidTailPredication, IsCorrect) {
24 
25   using namespace ARM;
26 
27   auto IsValidTPOpcode = [](unsigned Opcode) {
28     switch (Opcode) {
29     default:
30       return false;
31     case MVE_ASRLi:
32     case MVE_ASRLr:
33     case MVE_LSRL:
34     case MVE_SQRSHR:
35     case MVE_SQSHL:
36     case MVE_SRSHR:
37     case MVE_UQRSHL:
38     case MVE_UQSHL:
39     case MVE_URSHR:
40     case MVE_VABDf16:
41     case MVE_VABDf32:
42     case MVE_VABDs16:
43     case MVE_VABDs32:
44     case MVE_VABDs8:
45     case MVE_VABDu16:
46     case MVE_VABDu32:
47     case MVE_VABDu8:
48     case MVE_VABSf16:
49     case MVE_VABSf32:
50     case MVE_VABSs16:
51     case MVE_VABSs32:
52     case MVE_VABSs8:
53     case MVE_VADD_qr_f16:
54     case MVE_VADD_qr_f32:
55     case MVE_VADD_qr_i16:
56     case MVE_VADD_qr_i32:
57     case MVE_VADD_qr_i8:
58     case MVE_VADDf16:
59     case MVE_VADDf32:
60     case MVE_VADDi16:
61     case MVE_VADDi32:
62     case MVE_VADDi8:
63     case MVE_VAND:
64     case MVE_VBIC:
65     case MVE_VBICIZ0v4i32:
66     case MVE_VBICIZ0v8i16:
67     case MVE_VBICIZ16v4i32:
68     case MVE_VBICIZ24v4i32:
69     case MVE_VBICIZ8v4i32:
70     case MVE_VBICIZ8v8i16:
71     case MVE_VBRSR16:
72     case MVE_VBRSR32:
73     case MVE_VBRSR8:
74     case MVE_VCLSs16:
75     case MVE_VCLSs32:
76     case MVE_VCLSs8:
77     case MVE_VCLZs16:
78     case MVE_VCLZs32:
79     case MVE_VCLZs8:
80     case MVE_VCMPf16:
81     case MVE_VCMPf16r:
82     case MVE_VCMPf32:
83     case MVE_VCMPf32r:
84     case MVE_VCMPi16:
85     case MVE_VCMPi16r:
86     case MVE_VCMPi32:
87     case MVE_VCMPi32r:
88     case MVE_VCMPi8:
89     case MVE_VCMPi8r:
90     case MVE_VCMPs16:
91     case MVE_VCMPs16r:
92     case MVE_VCMPs32:
93     case MVE_VCMPs32r:
94     case MVE_VCMPs8:
95     case MVE_VCMPs8r:
96     case MVE_VCMPu16:
97     case MVE_VCMPu16r:
98     case MVE_VCMPu32:
99     case MVE_VCMPu32r:
100     case MVE_VCMPu8:
101     case MVE_VCMPu8r:
102     case MVE_VCTP16:
103     case MVE_VCTP32:
104     case MVE_VCTP64:
105     case MVE_VCTP8:
106     case MVE_VCVTf16s16_fix:
107     case MVE_VCVTf16s16n:
108     case MVE_VCVTf16u16_fix:
109     case MVE_VCVTf16u16n:
110     case MVE_VCVTf32s32_fix:
111     case MVE_VCVTf32s32n:
112     case MVE_VCVTf32u32_fix:
113     case MVE_VCVTf32u32n:
114     case MVE_VCVTs16f16_fix:
115     case MVE_VCVTs16f16a:
116     case MVE_VCVTs16f16m:
117     case MVE_VCVTs16f16n:
118     case MVE_VCVTs16f16p:
119     case MVE_VCVTs16f16z:
120     case MVE_VCVTs32f32_fix:
121     case MVE_VCVTs32f32a:
122     case MVE_VCVTs32f32m:
123     case MVE_VCVTs32f32n:
124     case MVE_VCVTs32f32p:
125     case MVE_VCVTs32f32z:
126     case MVE_VCVTu16f16_fix:
127     case MVE_VCVTu16f16a:
128     case MVE_VCVTu16f16m:
129     case MVE_VCVTu16f16n:
130     case MVE_VCVTu16f16p:
131     case MVE_VCVTu16f16z:
132     case MVE_VCVTu32f32_fix:
133     case MVE_VCVTu32f32a:
134     case MVE_VCVTu32f32m:
135     case MVE_VCVTu32f32n:
136     case MVE_VCVTu32f32p:
137     case MVE_VCVTu32f32z:
138     case MVE_VDDUPu16:
139     case MVE_VDDUPu32:
140     case MVE_VDDUPu8:
141     case MVE_VDUP16:
142     case MVE_VDUP32:
143     case MVE_VDUP8:
144     case MVE_VDWDUPu16:
145     case MVE_VDWDUPu32:
146     case MVE_VDWDUPu8:
147     case MVE_VEOR:
148     case MVE_VFMA_qr_Sf16:
149     case MVE_VFMA_qr_Sf32:
150     case MVE_VFMA_qr_f16:
151     case MVE_VFMA_qr_f32:
152     case MVE_VMAXAs16:
153     case MVE_VMAXAs32:
154     case MVE_VMAXAs8:
155     case MVE_VMAXs16:
156     case MVE_VMAXs32:
157     case MVE_VMAXs8:
158     case MVE_VMAXu16:
159     case MVE_VMAXu32:
160     case MVE_VMAXu8:
161     case MVE_VMINAs16:
162     case MVE_VMINAs32:
163     case MVE_VMINAs8:
164     case MVE_VMINs16:
165     case MVE_VMINs32:
166     case MVE_VMINs8:
167     case MVE_VMINu16:
168     case MVE_VMINu32:
169     case MVE_VMINu8:
170     case MVE_VMLAS_qr_s16:
171     case MVE_VMLAS_qr_s32:
172     case MVE_VMLAS_qr_s8:
173     case MVE_VMLAS_qr_u16:
174     case MVE_VMLAS_qr_u32:
175     case MVE_VMLAS_qr_u8:
176     case MVE_VMLA_qr_s16:
177     case MVE_VMLA_qr_s32:
178     case MVE_VMLA_qr_s8:
179     case MVE_VMLA_qr_u16:
180     case MVE_VMLA_qr_u32:
181     case MVE_VMLA_qr_u8:
182     case MVE_VHADD_qr_s16:
183     case MVE_VHADD_qr_s32:
184     case MVE_VHADD_qr_s8:
185     case MVE_VHADD_qr_u16:
186     case MVE_VHADD_qr_u32:
187     case MVE_VHADD_qr_u8:
188     case MVE_VHADDs16:
189     case MVE_VHADDs32:
190     case MVE_VHADDs8:
191     case MVE_VHADDu16:
192     case MVE_VHADDu32:
193     case MVE_VHADDu8:
194     case MVE_VHSUB_qr_s16:
195     case MVE_VHSUB_qr_s32:
196     case MVE_VHSUB_qr_s8:
197     case MVE_VHSUB_qr_u16:
198     case MVE_VHSUB_qr_u32:
199     case MVE_VHSUB_qr_u8:
200     case MVE_VHSUBs16:
201     case MVE_VHSUBs32:
202     case MVE_VHSUBs8:
203     case MVE_VHSUBu16:
204     case MVE_VHSUBu32:
205     case MVE_VHSUBu8:
206     case MVE_VIDUPu16:
207     case MVE_VIDUPu32:
208     case MVE_VIDUPu8:
209     case MVE_VIWDUPu16:
210     case MVE_VIWDUPu32:
211     case MVE_VIWDUPu8:
212     case MVE_VLDRBS16:
213     case MVE_VLDRBS16_post:
214     case MVE_VLDRBS16_pre:
215     case MVE_VLDRBS16_rq:
216     case MVE_VLDRBS32:
217     case MVE_VLDRBS32_post:
218     case MVE_VLDRBS32_pre:
219     case MVE_VLDRBS32_rq:
220     case MVE_VLDRBU16:
221     case MVE_VLDRBU16_post:
222     case MVE_VLDRBU16_pre:
223     case MVE_VLDRBU16_rq:
224     case MVE_VLDRBU32:
225     case MVE_VLDRBU32_post:
226     case MVE_VLDRBU32_pre:
227     case MVE_VLDRBU32_rq:
228     case MVE_VLDRBU8:
229     case MVE_VLDRBU8_post:
230     case MVE_VLDRBU8_pre:
231     case MVE_VLDRBU8_rq:
232     case MVE_VLDRDU64_qi:
233     case MVE_VLDRDU64_qi_pre:
234     case MVE_VLDRDU64_rq:
235     case MVE_VLDRDU64_rq_u:
236     case MVE_VLDRHS32:
237     case MVE_VLDRHS32_post:
238     case MVE_VLDRHS32_pre:
239     case MVE_VLDRHS32_rq:
240     case MVE_VLDRHS32_rq_u:
241     case MVE_VLDRHU16:
242     case MVE_VLDRHU16_post:
243     case MVE_VLDRHU16_pre:
244     case MVE_VLDRHU16_rq:
245     case MVE_VLDRHU16_rq_u:
246     case MVE_VLDRHU32:
247     case MVE_VLDRHU32_post:
248     case MVE_VLDRHU32_pre:
249     case MVE_VLDRHU32_rq:
250     case MVE_VLDRHU32_rq_u:
251     case MVE_VLDRWU32:
252     case MVE_VLDRWU32_post:
253     case MVE_VLDRWU32_pre:
254     case MVE_VLDRWU32_qi:
255     case MVE_VLDRWU32_qi_pre:
256     case MVE_VLDRWU32_rq:
257     case MVE_VLDRWU32_rq_u:
258     case MVE_VMOVimmf32:
259     case MVE_VMOVimmi16:
260     case MVE_VMOVimmi32:
261     case MVE_VMOVimmi64:
262     case MVE_VMOVimmi8:
263     case MVE_VMULLBp16:
264     case MVE_VMULLBp8:
265     case MVE_VMULLBs16:
266     case MVE_VMULLBs32:
267     case MVE_VMULLBs8:
268     case MVE_VMULLBu16:
269     case MVE_VMULLBu32:
270     case MVE_VMULLBu8:
271     case MVE_VMULLTp16:
272     case MVE_VMULLTp8:
273     case MVE_VMULLTs16:
274     case MVE_VMULLTs32:
275     case MVE_VMULLTs8:
276     case MVE_VMULLTu16:
277     case MVE_VMULLTu32:
278     case MVE_VMULLTu8:
279     case MVE_VMUL_qr_f16:
280     case MVE_VMUL_qr_f32:
281     case MVE_VMUL_qr_i16:
282     case MVE_VMUL_qr_i32:
283     case MVE_VMUL_qr_i8:
284     case MVE_VMULf16:
285     case MVE_VMULf32:
286     case MVE_VMULi16:
287     case MVE_VMULi8:
288     case MVE_VMULi32:
289     case MVE_VMVN:
290     case MVE_VMVNimmi16:
291     case MVE_VMVNimmi32:
292     case MVE_VNEGf16:
293     case MVE_VNEGf32:
294     case MVE_VNEGs16:
295     case MVE_VNEGs32:
296     case MVE_VNEGs8:
297     case MVE_VORN:
298     case MVE_VORR:
299     case MVE_VORRIZ0v4i32:
300     case MVE_VORRIZ0v8i16:
301     case MVE_VORRIZ16v4i32:
302     case MVE_VORRIZ24v4i32:
303     case MVE_VORRIZ8v4i32:
304     case MVE_VORRIZ8v8i16:
305     case MVE_VPST:
306     case MVE_VQABSs16:
307     case MVE_VQABSs32:
308     case MVE_VQABSs8:
309     case MVE_VQADD_qr_s16:
310     case MVE_VQADD_qr_s32:
311     case MVE_VQADD_qr_s8:
312     case MVE_VQADD_qr_u16:
313     case MVE_VQADD_qr_u32:
314     case MVE_VQADD_qr_u8:
315     case MVE_VQADDs16:
316     case MVE_VQADDs32:
317     case MVE_VQADDs8:
318     case MVE_VQADDu16:
319     case MVE_VQADDu32:
320     case MVE_VQADDu8:
321     case MVE_VQDMULL_qr_s16bh:
322     case MVE_VQDMULL_qr_s16th:
323     case MVE_VQDMULL_qr_s32bh:
324     case MVE_VQDMULL_qr_s32th:
325     case MVE_VQDMULLs16bh:
326     case MVE_VQDMULLs16th:
327     case MVE_VQDMULLs32bh:
328     case MVE_VQDMULLs32th:
329     case MVE_VQNEGs16:
330     case MVE_VQNEGs32:
331     case MVE_VQNEGs8:
332     case MVE_VQRSHL_by_vecs16:
333     case MVE_VQRSHL_by_vecs32:
334     case MVE_VQRSHL_by_vecs8:
335     case MVE_VQRSHL_by_vecu16:
336     case MVE_VQRSHL_by_vecu32:
337     case MVE_VQRSHL_by_vecu8:
338     case MVE_VQRSHL_qrs16:
339     case MVE_VQRSHL_qrs32:
340     case MVE_VQRSHL_qrs8:
341     case MVE_VQRSHL_qru16:
342     case MVE_VQRSHL_qru8:
343     case MVE_VQRSHL_qru32:
344     case MVE_VQSHLU_imms16:
345     case MVE_VQSHLU_imms32:
346     case MVE_VQSHLU_imms8:
347     case MVE_VQSHLimms16:
348     case MVE_VQSHLimms32:
349     case MVE_VQSHLimms8:
350     case MVE_VQSHLimmu16:
351     case MVE_VQSHLimmu32:
352     case MVE_VQSHLimmu8:
353     case MVE_VQSHL_by_vecs16:
354     case MVE_VQSHL_by_vecs32:
355     case MVE_VQSHL_by_vecs8:
356     case MVE_VQSHL_by_vecu16:
357     case MVE_VQSHL_by_vecu32:
358     case MVE_VQSHL_by_vecu8:
359     case MVE_VQSHL_qrs16:
360     case MVE_VQSHL_qrs32:
361     case MVE_VQSHL_qrs8:
362     case MVE_VQSHL_qru16:
363     case MVE_VQSHL_qru32:
364     case MVE_VQSHL_qru8:
365     case MVE_VQSUB_qr_s16:
366     case MVE_VQSUB_qr_s32:
367     case MVE_VQSUB_qr_s8:
368     case MVE_VQSUB_qr_u16:
369     case MVE_VQSUB_qr_u32:
370     case MVE_VQSUB_qr_u8:
371     case MVE_VQSUBs16:
372     case MVE_VQSUBs32:
373     case MVE_VQSUBs8:
374     case MVE_VQSUBu16:
375     case MVE_VQSUBu32:
376     case MVE_VQSUBu8:
377     case MVE_VRHADDs16:
378     case MVE_VRHADDs32:
379     case MVE_VRHADDs8:
380     case MVE_VRHADDu16:
381     case MVE_VRHADDu32:
382     case MVE_VRHADDu8:
383     case MVE_VRINTf16A:
384     case MVE_VRINTf16M:
385     case MVE_VRINTf16N:
386     case MVE_VRINTf16P:
387     case MVE_VRINTf16X:
388     case MVE_VRINTf16Z:
389     case MVE_VRINTf32A:
390     case MVE_VRINTf32M:
391     case MVE_VRINTf32N:
392     case MVE_VRINTf32P:
393     case MVE_VRINTf32X:
394     case MVE_VRINTf32Z:
395     case MVE_VRSHL_by_vecs16:
396     case MVE_VRSHL_by_vecs32:
397     case MVE_VRSHL_by_vecs8:
398     case MVE_VRSHL_by_vecu16:
399     case MVE_VRSHL_by_vecu32:
400     case MVE_VRSHL_by_vecu8:
401     case MVE_VRSHL_qrs16:
402     case MVE_VRSHL_qrs32:
403     case MVE_VRSHL_qrs8:
404     case MVE_VRSHL_qru16:
405     case MVE_VRSHL_qru32:
406     case MVE_VRSHL_qru8:
407     case MVE_VRSHR_imms16:
408     case MVE_VRSHR_imms32:
409     case MVE_VRSHR_imms8:
410     case MVE_VRSHR_immu16:
411     case MVE_VRSHR_immu32:
412     case MVE_VRSHR_immu8:
413     case MVE_VSHL_by_vecs16:
414     case MVE_VSHL_by_vecs32:
415     case MVE_VSHL_by_vecs8:
416     case MVE_VSHL_by_vecu16:
417     case MVE_VSHL_by_vecu32:
418     case MVE_VSHL_by_vecu8:
419     case MVE_VSHL_immi16:
420     case MVE_VSHL_immi32:
421     case MVE_VSHL_immi8:
422     case MVE_VSHL_qrs16:
423     case MVE_VSHL_qrs32:
424     case MVE_VSHL_qrs8:
425     case MVE_VSHL_qru16:
426     case MVE_VSHL_qru32:
427     case MVE_VSHL_qru8:
428     case MVE_VSHR_imms16:
429     case MVE_VSHR_imms32:
430     case MVE_VSHR_imms8:
431     case MVE_VSHR_immu16:
432     case MVE_VSHR_immu32:
433     case MVE_VSHR_immu8:
434     case MVE_VSLIimm16:
435     case MVE_VSLIimm32:
436     case MVE_VSLIimm8:
437     case MVE_VSRIimm16:
438     case MVE_VSRIimm32:
439     case MVE_VSRIimm8:
440     case MVE_VSTRB16:
441     case MVE_VSTRB16_post:
442     case MVE_VSTRB16_pre:
443     case MVE_VSTRB16_rq:
444     case MVE_VSTRB32:
445     case MVE_VSTRB32_post:
446     case MVE_VSTRB32_pre:
447     case MVE_VSTRB32_rq:
448     case MVE_VSTRB8_rq:
449     case MVE_VSTRBU8:
450     case MVE_VSTRBU8_post:
451     case MVE_VSTRBU8_pre:
452     case MVE_VSTRD64_qi:
453     case MVE_VSTRD64_qi_pre:
454     case MVE_VSTRD64_rq:
455     case MVE_VSTRD64_rq_u:
456     case MVE_VSTRH16_rq:
457     case MVE_VSTRH16_rq_u:
458     case MVE_VSTRH32:
459     case MVE_VSTRH32_post:
460     case MVE_VSTRH32_pre:
461     case MVE_VSTRH32_rq:
462     case MVE_VSTRH32_rq_u:
463     case MVE_VSTRHU16:
464     case MVE_VSTRHU16_post:
465     case MVE_VSTRHU16_pre:
466     case MVE_VSTRW32_qi:
467     case MVE_VSTRW32_qi_pre:
468     case MVE_VSTRW32_rq:
469     case MVE_VSTRW32_rq_u:
470     case MVE_VSTRWU32:
471     case MVE_VSTRWU32_post:
472     case MVE_VSTRWU32_pre:
473     case MVE_VSUB_qr_f16:
474     case MVE_VSUB_qr_f32:
475     case MVE_VSUB_qr_i16:
476     case MVE_VSUB_qr_i32:
477     case MVE_VSUB_qr_i8:
478     case MVE_VSUBf16:
479     case MVE_VSUBf32:
480     case MVE_VSUBi16:
481     case MVE_VSUBi32:
482     case MVE_VSUBi8:
483       return true;
484     }
485   };
486 
487   LLVMInitializeARMTargetInfo();
488   LLVMInitializeARMTarget();
489   LLVMInitializeARMTargetMC();
490 
491   auto TT(Triple::normalize("thumbv8.1m.main-arm-none-eabi"));
492   std::string Error;
493   const Target *T = TargetRegistry::lookupTarget(TT, Error);
494   if (!T) {
495     dbgs() << Error;
496     return;
497   }
498 
499   TargetOptions Options;
500   auto TM = std::unique_ptr<LLVMTargetMachine>(
501     static_cast<LLVMTargetMachine*>(
502       T->createTargetMachine(TT, "generic", "", Options, None, None,
503                              CodeGenOpt::Default)));
504   ARMSubtarget ST(TM->getTargetTriple(), TM->getTargetCPU(),
505                   TM->getTargetFeatureString(),
506                   *static_cast<const ARMBaseTargetMachine*>(TM.get()), false);
507   const ARMBaseInstrInfo *TII = ST.getInstrInfo();
508   auto MII = TM->getMCInstrInfo();
509 
510   for (unsigned i = 0; i < ARM::INSTRUCTION_LIST_END; ++i) {
511     const MCInstrDesc &Desc = TII->get(i);
512 
513     for (auto &Op : Desc.operands()) {
514       // Only check instructions that access the MQPR regs.
515       if ((Op.OperandType & MCOI::OPERAND_REGISTER) == 0 ||
516           Op.RegClass != ARM::MQPRRegClassID)
517         continue;
518 
519       uint64_t Flags = MII->get(i).TSFlags;
520       bool Valid = (Flags & ARMII::ValidForTailPredication) != 0;
521       ASSERT_EQ(IsValidTPOpcode(i), Valid)
522                 << MII->getName(i)
523                 << ": mismatched expectation for tail-predicated safety\n";
524       break;
525     }
526   }
527 }
528 
529 TEST(MachineInstr, HasSideEffects) {
530   using namespace ARM;
531   unsigned Opcodes[] = {
532       // MVE Loads/Stores
533       MVE_VLDRBS16,        MVE_VLDRBS16_post,   MVE_VLDRBS16_pre,
534       MVE_VLDRBS16_rq,     MVE_VLDRBS32,        MVE_VLDRBS32_post,
535       MVE_VLDRBS32_pre,    MVE_VLDRBS32_rq,     MVE_VLDRBU16,
536       MVE_VLDRBU16_post,   MVE_VLDRBU16_pre,    MVE_VLDRBU16_rq,
537       MVE_VLDRBU32,        MVE_VLDRBU32_post,   MVE_VLDRBU32_pre,
538       MVE_VLDRBU32_rq,     MVE_VLDRBU8,         MVE_VLDRBU8_post,
539       MVE_VLDRBU8_pre,     MVE_VLDRBU8_rq,      MVE_VLDRDU64_qi,
540       MVE_VLDRDU64_qi_pre, MVE_VLDRDU64_rq,     MVE_VLDRDU64_rq_u,
541       MVE_VLDRHS32,        MVE_VLDRHS32_post,   MVE_VLDRHS32_pre,
542       MVE_VLDRHS32_rq,     MVE_VLDRHS32_rq_u,   MVE_VLDRHU16,
543       MVE_VLDRHU16_post,   MVE_VLDRHU16_pre,    MVE_VLDRHU16_rq,
544       MVE_VLDRHU16_rq_u,   MVE_VLDRHU32,        MVE_VLDRHU32_post,
545       MVE_VLDRHU32_pre,    MVE_VLDRHU32_rq,     MVE_VLDRHU32_rq_u,
546       MVE_VLDRWU32,        MVE_VLDRWU32_post,   MVE_VLDRWU32_pre,
547       MVE_VLDRWU32_qi,     MVE_VLDRWU32_qi_pre, MVE_VLDRWU32_rq,
548       MVE_VLDRWU32_rq_u,   MVE_VLD20_16,        MVE_VLD20_16_wb,
549       MVE_VLD20_32,        MVE_VLD20_32_wb,     MVE_VLD20_8,
550       MVE_VLD20_8_wb,      MVE_VLD21_16,        MVE_VLD21_16_wb,
551       MVE_VLD21_32,        MVE_VLD21_32_wb,     MVE_VLD21_8,
552       MVE_VLD21_8_wb,      MVE_VLD40_16,        MVE_VLD40_16_wb,
553       MVE_VLD40_32,        MVE_VLD40_32_wb,     MVE_VLD40_8,
554       MVE_VLD40_8_wb,      MVE_VLD41_16,        MVE_VLD41_16_wb,
555       MVE_VLD41_32,        MVE_VLD41_32_wb,     MVE_VLD41_8,
556       MVE_VLD41_8_wb,      MVE_VLD42_16,        MVE_VLD42_16_wb,
557       MVE_VLD42_32,        MVE_VLD42_32_wb,     MVE_VLD42_8,
558       MVE_VLD42_8_wb,      MVE_VLD43_16,        MVE_VLD43_16_wb,
559       MVE_VLD43_32,        MVE_VLD43_32_wb,     MVE_VLD43_8,
560       MVE_VLD43_8_wb,      MVE_VSTRB16,         MVE_VSTRB16_post,
561       MVE_VSTRB16_pre,     MVE_VSTRB16_rq,      MVE_VSTRB32,
562       MVE_VSTRB32_post,    MVE_VSTRB32_pre,     MVE_VSTRB32_rq,
563       MVE_VSTRB8_rq,       MVE_VSTRBU8,         MVE_VSTRBU8_post,
564       MVE_VSTRBU8_pre,     MVE_VSTRD64_qi,      MVE_VSTRD64_qi_pre,
565       MVE_VSTRD64_rq,      MVE_VSTRD64_rq_u,    MVE_VSTRH16_rq,
566       MVE_VSTRH16_rq_u,    MVE_VSTRH32,         MVE_VSTRH32_post,
567       MVE_VSTRH32_pre,     MVE_VSTRH32_rq,      MVE_VSTRH32_rq_u,
568       MVE_VSTRHU16,        MVE_VSTRHU16_post,   MVE_VSTRHU16_pre,
569       MVE_VSTRW32_qi,      MVE_VSTRW32_qi_pre,  MVE_VSTRW32_rq,
570       MVE_VSTRW32_rq_u,    MVE_VSTRWU32,        MVE_VSTRWU32_post,
571       MVE_VSTRWU32_pre,    MVE_VST20_16,        MVE_VST20_16_wb,
572       MVE_VST20_32,        MVE_VST20_32_wb,     MVE_VST20_8,
573       MVE_VST20_8_wb,      MVE_VST21_16,        MVE_VST21_16_wb,
574       MVE_VST21_32,        MVE_VST21_32_wb,     MVE_VST21_8,
575       MVE_VST21_8_wb,      MVE_VST40_16,        MVE_VST40_16_wb,
576       MVE_VST40_32,        MVE_VST40_32_wb,     MVE_VST40_8,
577       MVE_VST40_8_wb,      MVE_VST41_16,        MVE_VST41_16_wb,
578       MVE_VST41_32,        MVE_VST41_32_wb,     MVE_VST41_8,
579       MVE_VST41_8_wb,      MVE_VST42_16,        MVE_VST42_16_wb,
580       MVE_VST42_32,        MVE_VST42_32_wb,     MVE_VST42_8,
581       MVE_VST42_8_wb,      MVE_VST43_16,        MVE_VST43_16_wb,
582       MVE_VST43_32,        MVE_VST43_32_wb,     MVE_VST43_8,
583       MVE_VST43_8_wb,
584   };
585 
586   LLVMInitializeARMTargetInfo();
587   LLVMInitializeARMTarget();
588   LLVMInitializeARMTargetMC();
589 
590   auto TT(Triple::normalize("thumbv8.1m.main-arm-none-eabi"));
591   std::string Error;
592   const Target *T = TargetRegistry::lookupTarget(TT, Error);
593   if (!T) {
594     dbgs() << Error;
595     return;
596   }
597 
598   TargetOptions Options;
599   auto TM = std::unique_ptr<LLVMTargetMachine>(
600       static_cast<LLVMTargetMachine *>(T->createTargetMachine(
601           TT, "generic", "", Options, None, None, CodeGenOpt::Default)));
602   ARMSubtarget ST(TM->getTargetTriple(), TM->getTargetCPU(),
603                   TM->getTargetFeatureString(),
604                   *static_cast<const ARMBaseTargetMachine *>(TM.get()), false);
605   const ARMBaseInstrInfo *TII = ST.getInstrInfo();
606   auto MII = TM->getMCInstrInfo();
607 
608   for (unsigned Op : Opcodes) {
609     const MCInstrDesc &Desc = TII->get(Op);
610     ASSERT_FALSE(Desc.hasUnmodeledSideEffects())
611         << MII->getName(Op) << " has unexpected side effects";
612   }
613 }
614