1 //===---- llvm/unittest/CodeGen/SelectionDAGPatternMatchTest.cpp ---------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "llvm/Analysis/OptimizationRemarkEmitter.h" 10 #include "llvm/AsmParser/Parser.h" 11 #include "llvm/CodeGen/MachineModuleInfo.h" 12 #include "llvm/CodeGen/SDPatternMatch.h" 13 #include "llvm/CodeGen/TargetLowering.h" 14 #include "llvm/MC/TargetRegistry.h" 15 #include "llvm/Support/SourceMgr.h" 16 #include "llvm/Support/TargetSelect.h" 17 #include "llvm/Target/TargetMachine.h" 18 #include "gtest/gtest.h" 19 20 using namespace llvm; 21 22 class SelectionDAGPatternMatchTest : public testing::Test { 23 protected: 24 static void SetUpTestCase() { 25 InitializeAllTargets(); 26 InitializeAllTargetMCs(); 27 } 28 29 void SetUp() override { 30 StringRef Assembly = "@g = global i32 0\n" 31 "@g_alias = alias i32, i32* @g\n" 32 "define i32 @f() {\n" 33 " %1 = load i32, i32* @g\n" 34 " ret i32 %1\n" 35 "}"; 36 37 Triple TargetTriple("riscv64--"); 38 std::string Error; 39 const Target *T = TargetRegistry::lookupTarget("", TargetTriple, Error); 40 // FIXME: These tests do not depend on RISCV specifically, but we have to 41 // initialize a target. A skeleton Target for unittests would allow us to 42 // always run these tests. 43 if (!T) 44 GTEST_SKIP(); 45 46 TargetOptions Options; 47 TM = std::unique_ptr<LLVMTargetMachine>(static_cast<LLVMTargetMachine *>( 48 T->createTargetMachine("riscv64", "", "+m,+f,+d,+v", Options, 49 std::nullopt, std::nullopt, 50 CodeGenOptLevel::Aggressive))); 51 if (!TM) 52 GTEST_SKIP(); 53 54 SMDiagnostic SMError; 55 M = parseAssemblyString(Assembly, SMError, Context); 56 if (!M) 57 report_fatal_error(SMError.getMessage()); 58 M->setDataLayout(TM->createDataLayout()); 59 60 F = M->getFunction("f"); 61 if (!F) 62 report_fatal_error("F?"); 63 G = M->getGlobalVariable("g"); 64 if (!G) 65 report_fatal_error("G?"); 66 AliasedG = M->getNamedAlias("g_alias"); 67 if (!AliasedG) 68 report_fatal_error("AliasedG?"); 69 70 MachineModuleInfo MMI(TM.get()); 71 72 MF = std::make_unique<MachineFunction>(*F, *TM, *TM->getSubtargetImpl(*F), 73 0, MMI); 74 75 DAG = std::make_unique<SelectionDAG>(*TM, CodeGenOptLevel::None); 76 if (!DAG) 77 report_fatal_error("DAG?"); 78 OptimizationRemarkEmitter ORE(F); 79 DAG->init(*MF, ORE, nullptr, nullptr, nullptr, nullptr, nullptr, nullptr); 80 } 81 82 TargetLoweringBase::LegalizeTypeAction getTypeAction(EVT VT) { 83 return DAG->getTargetLoweringInfo().getTypeAction(Context, VT); 84 } 85 86 EVT getTypeToTransformTo(EVT VT) { 87 return DAG->getTargetLoweringInfo().getTypeToTransformTo(Context, VT); 88 } 89 90 LLVMContext Context; 91 std::unique_ptr<LLVMTargetMachine> TM; 92 std::unique_ptr<Module> M; 93 Function *F; 94 GlobalVariable *G; 95 GlobalAlias *AliasedG; 96 std::unique_ptr<MachineFunction> MF; 97 std::unique_ptr<SelectionDAG> DAG; 98 }; 99 100 TEST_F(SelectionDAGPatternMatchTest, matchValueType) { 101 SDLoc DL; 102 auto Int32VT = EVT::getIntegerVT(Context, 32); 103 auto Float32VT = EVT::getFloatingPointVT(32); 104 auto VInt32VT = EVT::getVectorVT(Context, Int32VT, 4); 105 106 SDValue Op0 = DAG->getCopyFromReg(DAG->getEntryNode(), DL, 1, Int32VT); 107 SDValue Op1 = DAG->getCopyFromReg(DAG->getEntryNode(), DL, 2, Float32VT); 108 SDValue Op2 = DAG->getCopyFromReg(DAG->getEntryNode(), DL, 2, VInt32VT); 109 110 using namespace SDPatternMatch; 111 EXPECT_TRUE(sd_match(Op0, m_SpecificVT(Int32VT))); 112 EVT BindVT; 113 EXPECT_TRUE(sd_match(Op1, m_VT(BindVT))); 114 EXPECT_EQ(BindVT, Float32VT); 115 EXPECT_TRUE(sd_match(Op0, m_IntegerVT())); 116 EXPECT_TRUE(sd_match(Op1, m_FloatingPointVT())); 117 EXPECT_TRUE(sd_match(Op2, m_VectorVT())); 118 EXPECT_FALSE(sd_match(Op2, m_ScalableVectorVT())); 119 } 120 121 TEST_F(SelectionDAGPatternMatchTest, matchBinaryOp) { 122 SDLoc DL; 123 auto Int32VT = EVT::getIntegerVT(Context, 32); 124 auto Float32VT = EVT::getFloatingPointVT(32); 125 126 SDValue Op0 = DAG->getCopyFromReg(DAG->getEntryNode(), DL, 1, Int32VT); 127 SDValue Op1 = DAG->getCopyFromReg(DAG->getEntryNode(), DL, 2, Int32VT); 128 SDValue Op2 = DAG->getCopyFromReg(DAG->getEntryNode(), DL, 3, Float32VT); 129 130 SDValue Add = DAG->getNode(ISD::ADD, DL, Int32VT, Op0, Op1); 131 SDValue Sub = DAG->getNode(ISD::SUB, DL, Int32VT, Add, Op0); 132 SDValue Mul = DAG->getNode(ISD::MUL, DL, Int32VT, Add, Sub); 133 134 SDValue SFAdd = DAG->getNode(ISD::STRICT_FADD, DL, {Float32VT, MVT::Other}, 135 {DAG->getEntryNode(), Op2, Op2}); 136 137 using namespace SDPatternMatch; 138 EXPECT_TRUE(sd_match(Sub, m_BinOp(ISD::SUB, m_Value(), m_Value()))); 139 EXPECT_TRUE(sd_match(Sub, m_Sub(m_Value(), m_Value()))); 140 EXPECT_TRUE(sd_match(Add, m_c_BinOp(ISD::ADD, m_Value(), m_Value()))); 141 EXPECT_TRUE(sd_match(Add, m_Add(m_Value(), m_Value()))); 142 EXPECT_TRUE(sd_match( 143 Mul, m_Mul(m_OneUse(m_Opc(ISD::SUB)), m_NUses<2>(m_Specific(Add))))); 144 EXPECT_TRUE( 145 sd_match(SFAdd, m_ChainedBinOp(ISD::STRICT_FADD, m_SpecificVT(Float32VT), 146 m_SpecificVT(Float32VT)))); 147 SDValue BindVal; 148 EXPECT_TRUE(sd_match(SFAdd, m_ChainedBinOp(ISD::STRICT_FADD, m_Value(BindVal), 149 m_Deferred(BindVal)))); 150 EXPECT_FALSE(sd_match(SFAdd, m_ChainedBinOp(ISD::STRICT_FADD, m_OtherVT(), 151 m_SpecificVT(Float32VT)))); 152 } 153 154 TEST_F(SelectionDAGPatternMatchTest, matchUnaryOp) { 155 SDLoc DL; 156 auto Int32VT = EVT::getIntegerVT(Context, 32); 157 auto Int64VT = EVT::getIntegerVT(Context, 64); 158 159 SDValue Op0 = DAG->getCopyFromReg(DAG->getEntryNode(), DL, 1, Int32VT); 160 SDValue Op1 = DAG->getCopyFromReg(DAG->getEntryNode(), DL, 1, Int64VT); 161 162 SDValue ZExt = DAG->getNode(ISD::ZERO_EXTEND, DL, Int64VT, Op0); 163 SDValue SExt = DAG->getNode(ISD::SIGN_EXTEND, DL, Int64VT, Op0); 164 SDValue Trunc = DAG->getNode(ISD::TRUNCATE, DL, Int32VT, Op1); 165 166 using namespace SDPatternMatch; 167 EXPECT_TRUE(sd_match(ZExt, m_UnaryOp(ISD::ZERO_EXTEND, m_Value()))); 168 EXPECT_TRUE(sd_match(SExt, m_SExt(m_Value()))); 169 EXPECT_TRUE(sd_match(Trunc, m_Trunc(m_Specific(Op1)))); 170 } 171 172 TEST_F(SelectionDAGPatternMatchTest, matchConstants) { 173 SDLoc DL; 174 auto Int32VT = EVT::getIntegerVT(Context, 32); 175 auto VInt32VT = EVT::getVectorVT(Context, Int32VT, 4); 176 177 SDValue Arg0 = DAG->getCopyFromReg(DAG->getEntryNode(), DL, 1, Int32VT); 178 179 SDValue Const3 = DAG->getConstant(3, DL, Int32VT); 180 SDValue Const87 = DAG->getConstant(87, DL, Int32VT); 181 SDValue Splat = DAG->getSplat(VInt32VT, DL, Arg0); 182 SDValue ConstSplat = DAG->getSplat(VInt32VT, DL, Const3); 183 SDValue Zero = DAG->getConstant(0, DL, Int32VT); 184 SDValue One = DAG->getConstant(1, DL, Int32VT); 185 SDValue AllOnes = DAG->getConstant(APInt::getAllOnes(32), DL, Int32VT); 186 187 using namespace SDPatternMatch; 188 EXPECT_TRUE(sd_match(Const87, m_ConstInt())); 189 EXPECT_FALSE(sd_match(Arg0, m_ConstInt())); 190 APInt ConstVal; 191 EXPECT_TRUE(sd_match(ConstSplat, m_ConstInt(ConstVal))); 192 EXPECT_EQ(ConstVal, 3); 193 EXPECT_FALSE(sd_match(Splat, m_ConstInt())); 194 195 EXPECT_TRUE(sd_match(Const87, m_SpecificInt(87))); 196 EXPECT_TRUE(sd_match(Const3, m_SpecificInt(ConstVal))); 197 EXPECT_TRUE(sd_match(AllOnes, m_AllOnes())); 198 199 EXPECT_TRUE(sd_match(Zero, DAG.get(), m_False())); 200 EXPECT_TRUE(sd_match(One, DAG.get(), m_True())); 201 EXPECT_FALSE(sd_match(AllOnes, DAG.get(), m_True())); 202 } 203 204 TEST_F(SelectionDAGPatternMatchTest, patternCombinators) { 205 SDLoc DL; 206 auto Int32VT = EVT::getIntegerVT(Context, 32); 207 208 SDValue Op0 = DAG->getCopyFromReg(DAG->getEntryNode(), DL, 1, Int32VT); 209 SDValue Op1 = DAG->getCopyFromReg(DAG->getEntryNode(), DL, 2, Int32VT); 210 211 SDValue Add = DAG->getNode(ISD::ADD, DL, Int32VT, Op0, Op1); 212 SDValue Sub = DAG->getNode(ISD::SUB, DL, Int32VT, Add, Op0); 213 214 using namespace SDPatternMatch; 215 EXPECT_TRUE(sd_match( 216 Sub, m_AnyOf(m_Opc(ISD::ADD), m_Opc(ISD::SUB), m_Opc(ISD::MUL)))); 217 EXPECT_TRUE(sd_match(Add, m_AllOf(m_Opc(ISD::ADD), m_OneUse()))); 218 } 219 220 TEST_F(SelectionDAGPatternMatchTest, matchNode) { 221 SDLoc DL; 222 auto Int32VT = EVT::getIntegerVT(Context, 32); 223 224 SDValue Op0 = DAG->getCopyFromReg(DAG->getEntryNode(), DL, 1, Int32VT); 225 SDValue Op1 = DAG->getCopyFromReg(DAG->getEntryNode(), DL, 2, Int32VT); 226 227 SDValue Add = DAG->getNode(ISD::ADD, DL, Int32VT, Op0, Op1); 228 229 using namespace SDPatternMatch; 230 EXPECT_TRUE(sd_match(Add, m_Node(ISD::ADD, m_Value(), m_Value()))); 231 EXPECT_FALSE(sd_match(Add, m_Node(ISD::SUB, m_Value(), m_Value()))); 232 EXPECT_FALSE(sd_match(Add, m_Node(ISD::ADD, m_Value()))); 233 EXPECT_FALSE( 234 sd_match(Add, m_Node(ISD::ADD, m_Value(), m_Value(), m_Value()))); 235 EXPECT_FALSE(sd_match(Add, m_Node(ISD::ADD, m_ConstInt(), m_Value()))); 236 } 237 238 namespace { 239 struct VPMatchContext : public SDPatternMatch::BasicMatchContext { 240 using SDPatternMatch::BasicMatchContext::BasicMatchContext; 241 242 bool match(SDValue OpVal, unsigned Opc) const { 243 if (!OpVal->isVPOpcode()) 244 return OpVal->getOpcode() == Opc; 245 246 auto BaseOpc = ISD::getBaseOpcodeForVP(OpVal->getOpcode(), false); 247 return BaseOpc.has_value() && *BaseOpc == Opc; 248 } 249 }; 250 } // anonymous namespace 251 TEST_F(SelectionDAGPatternMatchTest, matchContext) { 252 SDLoc DL; 253 auto BoolVT = EVT::getIntegerVT(Context, 1); 254 auto Int32VT = EVT::getIntegerVT(Context, 32); 255 auto VInt32VT = EVT::getVectorVT(Context, Int32VT, 4); 256 auto MaskVT = EVT::getVectorVT(Context, BoolVT, 4); 257 258 SDValue Scalar0 = DAG->getCopyFromReg(DAG->getEntryNode(), DL, 1, Int32VT); 259 SDValue Vector0 = DAG->getCopyFromReg(DAG->getEntryNode(), DL, 2, VInt32VT); 260 SDValue Mask0 = DAG->getCopyFromReg(DAG->getEntryNode(), DL, 3, MaskVT); 261 262 SDValue VPAdd = DAG->getNode(ISD::VP_ADD, DL, VInt32VT, 263 {Vector0, Vector0, Mask0, Scalar0}); 264 SDValue VPReduceAdd = DAG->getNode(ISD::VP_REDUCE_ADD, DL, Int32VT, 265 {Scalar0, VPAdd, Mask0, Scalar0}); 266 267 using namespace SDPatternMatch; 268 VPMatchContext VPCtx(DAG.get()); 269 EXPECT_TRUE(sd_context_match(VPAdd, VPCtx, m_Opc(ISD::ADD))); 270 // VP_REDUCE_ADD doesn't have a based opcode, so we use a normal 271 // sd_match before switching to VPMatchContext when checking VPAdd. 272 EXPECT_TRUE(sd_match(VPReduceAdd, m_Node(ISD::VP_REDUCE_ADD, m_Value(), 273 m_Context(VPCtx, m_Opc(ISD::ADD)), 274 m_Value(), m_Value()))); 275 } 276 277 TEST_F(SelectionDAGPatternMatchTest, matchAdvancedProperties) { 278 SDLoc DL; 279 auto Int16VT = EVT::getIntegerVT(Context, 16); 280 auto Int64VT = EVT::getIntegerVT(Context, 64); 281 282 SDValue Op0 = DAG->getCopyFromReg(DAG->getEntryNode(), DL, 1, Int64VT); 283 SDValue Op1 = DAG->getCopyFromReg(DAG->getEntryNode(), DL, 2, Int16VT); 284 285 SDValue Add = DAG->getNode(ISD::ADD, DL, Int64VT, Op0, Op0); 286 287 using namespace SDPatternMatch; 288 EXPECT_TRUE(sd_match(Op0, DAG.get(), m_LegalType(m_Value()))); 289 EXPECT_FALSE(sd_match(Op1, DAG.get(), m_LegalType(m_Value()))); 290 EXPECT_TRUE(sd_match(Add, DAG.get(), 291 m_LegalOp(m_IntegerVT(m_Add(m_Value(), m_Value()))))); 292 } 293