1 //===- MachineOperandTest.cpp ---------------------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "llvm/ADT/ilist_node.h" 11 #include "llvm/CodeGen/MachineOperand.h" 12 #include "llvm/Support/raw_ostream.h" 13 #include "gtest/gtest.h" 14 15 using namespace llvm; 16 17 namespace { 18 19 TEST(MachineOperandTest, ChangeToTargetIndexTest) { 20 // Creating a MachineOperand to change it to TargetIndex 21 MachineOperand MO = MachineOperand::CreateImm(50); 22 23 // Checking some precondition on the newly created 24 // MachineOperand. 25 ASSERT_TRUE(MO.isImm()); 26 ASSERT_TRUE(MO.getImm() == 50); 27 ASSERT_FALSE(MO.isTargetIndex()); 28 29 // Changing to TargetIndex with some arbitrary values 30 // for index, offset and flags. 31 MO.ChangeToTargetIndex(74, 57, 12); 32 33 // Checking that the mutation to TargetIndex happened 34 // correctly. 35 ASSERT_TRUE(MO.isTargetIndex()); 36 ASSERT_TRUE(MO.getIndex() == 74); 37 ASSERT_TRUE(MO.getOffset() == 57); 38 ASSERT_TRUE(MO.getTargetFlags() == 12); 39 } 40 41 TEST(MachineOperandTest, PrintRegisterMask) { 42 uint32_t Dummy; 43 MachineOperand MO = MachineOperand::CreateRegMask(&Dummy); 44 45 // Checking some preconditions on the newly created 46 // MachineOperand. 47 ASSERT_TRUE(MO.isRegMask()); 48 ASSERT_TRUE(MO.getRegMask() == &Dummy); 49 50 // Print a MachineOperand containing a RegMask. Here we check that without a 51 // TRI and IntrinsicInfo we still print a less detailed regmask. 52 std::string str; 53 raw_string_ostream OS(str); 54 MO.print(OS, /*TRI=*/nullptr, /*IntrinsicInfo=*/nullptr); 55 ASSERT_TRUE(OS.str() == "<regmask ...>"); 56 } 57 58 TEST(MachineOperandTest, PrintSubReg) { 59 // Create a MachineOperand with RegNum=1 and SubReg=5. 60 MachineOperand MO = MachineOperand::CreateReg( 61 /*Reg=*/1, /*isDef=*/false, /*isImp=*/false, /*isKill=*/false, 62 /*isDead=*/false, /*isUndef=*/false, /*isEarlyClobber=*/false, 63 /*SubReg=*/5, /*isDebug=*/false, /*isInternalRead=*/false); 64 65 // Checking some preconditions on the newly created 66 // MachineOperand. 67 ASSERT_TRUE(MO.isReg()); 68 ASSERT_TRUE(MO.getReg() == 1); 69 ASSERT_TRUE(MO.getSubReg() == 5); 70 71 // Print a MachineOperand containing a SubReg. Here we check that without a 72 // TRI and IntrinsicInfo we can still print the subreg index. 73 std::string str; 74 raw_string_ostream OS(str); 75 MO.print(OS, /*TRI=*/nullptr, /*IntrinsicInfo=*/nullptr); 76 ASSERT_TRUE(OS.str() == "%physreg1.subreg5"); 77 } 78 79 } // end namespace 80