1 //===- MachineInstrTest.cpp -----------------------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "llvm/CodeGen/MachineInstr.h" 10 #include "llvm/ADT/Triple.h" 11 #include "llvm/CodeGen/MachineBasicBlock.h" 12 #include "llvm/CodeGen/MachineFunction.h" 13 #include "llvm/CodeGen/MachineInstrBuilder.h" 14 #include "llvm/CodeGen/MachineMemOperand.h" 15 #include "llvm/CodeGen/MachineModuleInfo.h" 16 #include "llvm/CodeGen/TargetFrameLowering.h" 17 #include "llvm/CodeGen/TargetInstrInfo.h" 18 #include "llvm/CodeGen/TargetLowering.h" 19 #include "llvm/CodeGen/TargetSubtargetInfo.h" 20 #include "llvm/IR/DebugInfoMetadata.h" 21 #include "llvm/IR/IRBuilder.h" 22 #include "llvm/IR/ModuleSlotTracker.h" 23 #include "llvm/MC/MCAsmInfo.h" 24 #include "llvm/MC/MCSymbol.h" 25 #include "llvm/MC/TargetRegistry.h" 26 #include "llvm/Support/TargetSelect.h" 27 #include "llvm/Target/TargetMachine.h" 28 #include "llvm/Target/TargetOptions.h" 29 #include "gmock/gmock.h" 30 #include "gtest/gtest.h" 31 32 using namespace llvm; 33 34 namespace { 35 // Include helper functions to ease the manipulation of MachineFunctions. 36 #include "MFCommon.inc" 37 38 std::unique_ptr<MCContext> createMCContext(MCAsmInfo *AsmInfo) { 39 Triple TheTriple(/*ArchStr=*/"", /*VendorStr=*/"", /*OSStr=*/"", 40 /*EnvironmentStr=*/"elf"); 41 return std::make_unique<MCContext>(TheTriple, AsmInfo, nullptr, nullptr, 42 nullptr, nullptr, false); 43 } 44 45 // This test makes sure that MachineInstr::isIdenticalTo handles Defs correctly 46 // for various combinations of IgnoreDefs, and also that it is symmetrical. 47 TEST(IsIdenticalToTest, DifferentDefs) { 48 LLVMContext Ctx; 49 Module Mod("Module", Ctx); 50 auto MF = createMachineFunction(Ctx, Mod); 51 52 unsigned short NumOps = 2; 53 unsigned char NumDefs = 1; 54 MCOperandInfo OpInfo[] = { 55 {0, 0, MCOI::OPERAND_REGISTER, 0}, 56 {0, 1 << MCOI::OptionalDef, MCOI::OPERAND_REGISTER, 0}}; 57 MCInstrDesc MCID = { 58 0, NumOps, NumDefs, 0, 0, 1ULL << MCID::HasOptionalDef, 59 0, nullptr, nullptr, OpInfo}; 60 61 // Create two MIs with different virtual reg defs and the same uses. 62 unsigned VirtualDef1 = -42; // The value doesn't matter, but the sign does. 63 unsigned VirtualDef2 = -43; 64 unsigned VirtualUse = -44; 65 66 auto MI1 = MF->CreateMachineInstr(MCID, DebugLoc()); 67 MI1->addOperand(*MF, MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true)); 68 MI1->addOperand(*MF, MachineOperand::CreateReg(VirtualUse, /*isDef*/ false)); 69 70 auto MI2 = MF->CreateMachineInstr(MCID, DebugLoc()); 71 MI2->addOperand(*MF, MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true)); 72 MI2->addOperand(*MF, MachineOperand::CreateReg(VirtualUse, /*isDef*/ false)); 73 74 // Check that they are identical when we ignore virtual register defs, but not 75 // when we check defs. 76 ASSERT_FALSE(MI1->isIdenticalTo(*MI2, MachineInstr::CheckDefs)); 77 ASSERT_FALSE(MI2->isIdenticalTo(*MI1, MachineInstr::CheckDefs)); 78 79 ASSERT_TRUE(MI1->isIdenticalTo(*MI2, MachineInstr::IgnoreVRegDefs)); 80 ASSERT_TRUE(MI2->isIdenticalTo(*MI1, MachineInstr::IgnoreVRegDefs)); 81 82 // Create two MIs with different virtual reg defs, and a def or use of a 83 // sentinel register. 84 unsigned SentinelReg = 0; 85 86 auto MI3 = MF->CreateMachineInstr(MCID, DebugLoc()); 87 MI3->addOperand(*MF, MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true)); 88 MI3->addOperand(*MF, MachineOperand::CreateReg(SentinelReg, /*isDef*/ true)); 89 90 auto MI4 = MF->CreateMachineInstr(MCID, DebugLoc()); 91 MI4->addOperand(*MF, MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true)); 92 MI4->addOperand(*MF, MachineOperand::CreateReg(SentinelReg, /*isDef*/ false)); 93 94 // Check that they are never identical. 95 ASSERT_FALSE(MI3->isIdenticalTo(*MI4, MachineInstr::CheckDefs)); 96 ASSERT_FALSE(MI4->isIdenticalTo(*MI3, MachineInstr::CheckDefs)); 97 98 ASSERT_FALSE(MI3->isIdenticalTo(*MI4, MachineInstr::IgnoreVRegDefs)); 99 ASSERT_FALSE(MI4->isIdenticalTo(*MI3, MachineInstr::IgnoreVRegDefs)); 100 } 101 102 // Check that MachineInstrExpressionTrait::isEqual is symmetric and in sync with 103 // MachineInstrExpressionTrait::getHashValue 104 void checkHashAndIsEqualMatch(MachineInstr *MI1, MachineInstr *MI2) { 105 bool IsEqual1 = MachineInstrExpressionTrait::isEqual(MI1, MI2); 106 bool IsEqual2 = MachineInstrExpressionTrait::isEqual(MI2, MI1); 107 108 ASSERT_EQ(IsEqual1, IsEqual2); 109 110 auto Hash1 = MachineInstrExpressionTrait::getHashValue(MI1); 111 auto Hash2 = MachineInstrExpressionTrait::getHashValue(MI2); 112 113 ASSERT_EQ(IsEqual1, Hash1 == Hash2); 114 } 115 116 // This test makes sure that MachineInstrExpressionTraits::isEqual is in sync 117 // with MachineInstrExpressionTraits::getHashValue. 118 TEST(MachineInstrExpressionTraitTest, IsEqualAgreesWithGetHashValue) { 119 LLVMContext Ctx; 120 Module Mod("Module", Ctx); 121 auto MF = createMachineFunction(Ctx, Mod); 122 123 unsigned short NumOps = 2; 124 unsigned char NumDefs = 1; 125 MCOperandInfo OpInfo[] = { 126 {0, 0, MCOI::OPERAND_REGISTER, 0}, 127 {0, 1 << MCOI::OptionalDef, MCOI::OPERAND_REGISTER, 0}}; 128 MCInstrDesc MCID = { 129 0, NumOps, NumDefs, 0, 0, 1ULL << MCID::HasOptionalDef, 130 0, nullptr, nullptr, OpInfo}; 131 132 // Define a series of instructions with different kinds of operands and make 133 // sure that the hash function is consistent with isEqual for various 134 // combinations of them. 135 unsigned VirtualDef1 = -42; 136 unsigned VirtualDef2 = -43; 137 unsigned VirtualReg = -44; 138 unsigned SentinelReg = 0; 139 unsigned PhysicalReg = 45; 140 141 auto VD1VU = MF->CreateMachineInstr(MCID, DebugLoc()); 142 VD1VU->addOperand(*MF, 143 MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true)); 144 VD1VU->addOperand(*MF, 145 MachineOperand::CreateReg(VirtualReg, /*isDef*/ false)); 146 147 auto VD2VU = MF->CreateMachineInstr(MCID, DebugLoc()); 148 VD2VU->addOperand(*MF, 149 MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true)); 150 VD2VU->addOperand(*MF, 151 MachineOperand::CreateReg(VirtualReg, /*isDef*/ false)); 152 153 auto VD1SU = MF->CreateMachineInstr(MCID, DebugLoc()); 154 VD1SU->addOperand(*MF, 155 MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true)); 156 VD1SU->addOperand(*MF, 157 MachineOperand::CreateReg(SentinelReg, /*isDef*/ false)); 158 159 auto VD1SD = MF->CreateMachineInstr(MCID, DebugLoc()); 160 VD1SD->addOperand(*MF, 161 MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true)); 162 VD1SD->addOperand(*MF, 163 MachineOperand::CreateReg(SentinelReg, /*isDef*/ true)); 164 165 auto VD2PU = MF->CreateMachineInstr(MCID, DebugLoc()); 166 VD2PU->addOperand(*MF, 167 MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true)); 168 VD2PU->addOperand(*MF, 169 MachineOperand::CreateReg(PhysicalReg, /*isDef*/ false)); 170 171 auto VD2PD = MF->CreateMachineInstr(MCID, DebugLoc()); 172 VD2PD->addOperand(*MF, 173 MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true)); 174 VD2PD->addOperand(*MF, 175 MachineOperand::CreateReg(PhysicalReg, /*isDef*/ true)); 176 177 checkHashAndIsEqualMatch(VD1VU, VD2VU); 178 checkHashAndIsEqualMatch(VD1VU, VD1SU); 179 checkHashAndIsEqualMatch(VD1VU, VD1SD); 180 checkHashAndIsEqualMatch(VD1VU, VD2PU); 181 checkHashAndIsEqualMatch(VD1VU, VD2PD); 182 183 checkHashAndIsEqualMatch(VD2VU, VD1SU); 184 checkHashAndIsEqualMatch(VD2VU, VD1SD); 185 checkHashAndIsEqualMatch(VD2VU, VD2PU); 186 checkHashAndIsEqualMatch(VD2VU, VD2PD); 187 188 checkHashAndIsEqualMatch(VD1SU, VD1SD); 189 checkHashAndIsEqualMatch(VD1SU, VD2PU); 190 checkHashAndIsEqualMatch(VD1SU, VD2PD); 191 192 checkHashAndIsEqualMatch(VD1SD, VD2PU); 193 checkHashAndIsEqualMatch(VD1SD, VD2PD); 194 195 checkHashAndIsEqualMatch(VD2PU, VD2PD); 196 } 197 198 TEST(MachineInstrPrintingTest, DebugLocPrinting) { 199 LLVMContext Ctx; 200 Module Mod("Module", Ctx); 201 auto MF = createMachineFunction(Ctx, Mod); 202 203 MCOperandInfo OpInfo{0, 0, MCOI::OPERAND_REGISTER, 0}; 204 MCInstrDesc MCID = {0, 1, 1, 0, 0, 0, 0, nullptr, nullptr, &OpInfo}; 205 206 DIFile *DIF = DIFile::getDistinct(Ctx, "filename", ""); 207 DISubprogram *DIS = DISubprogram::getDistinct( 208 Ctx, nullptr, "", "", DIF, 0, nullptr, 0, nullptr, 0, 0, DINode::FlagZero, 209 DISubprogram::SPFlagZero, nullptr); 210 DILocation *DIL = DILocation::get(Ctx, 1, 5, DIS); 211 DebugLoc DL(DIL); 212 MachineInstr *MI = MF->CreateMachineInstr(MCID, DL); 213 MI->addOperand(*MF, MachineOperand::CreateReg(0, /*isDef*/ true)); 214 215 std::string str; 216 raw_string_ostream OS(str); 217 MI->print(OS, /*IsStandalone*/true, /*SkipOpers*/false, /*SkipDebugLoc*/false, 218 /*AddNewLine*/false); 219 ASSERT_TRUE( 220 StringRef(OS.str()).startswith("$noreg = UNKNOWN debug-location ")); 221 ASSERT_TRUE( 222 StringRef(OS.str()).endswith("filename:1:5")); 223 } 224 225 TEST(MachineInstrSpan, DistanceBegin) { 226 LLVMContext Ctx; 227 Module Mod("Module", Ctx); 228 auto MF = createMachineFunction(Ctx, Mod); 229 auto MBB = MF->CreateMachineBasicBlock(); 230 231 MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, nullptr, nullptr, nullptr}; 232 233 auto MII = MBB->begin(); 234 MachineInstrSpan MIS(MII, MBB); 235 ASSERT_TRUE(MIS.empty()); 236 237 auto MI = MF->CreateMachineInstr(MCID, DebugLoc()); 238 MBB->insert(MII, MI); 239 ASSERT_TRUE(std::distance(MIS.begin(), MII) == 1); 240 } 241 242 TEST(MachineInstrSpan, DistanceEnd) { 243 LLVMContext Ctx; 244 Module Mod("Module", Ctx); 245 auto MF = createMachineFunction(Ctx, Mod); 246 auto MBB = MF->CreateMachineBasicBlock(); 247 248 MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, nullptr, nullptr, nullptr}; 249 250 auto MII = MBB->end(); 251 MachineInstrSpan MIS(MII, MBB); 252 ASSERT_TRUE(MIS.empty()); 253 254 auto MI = MF->CreateMachineInstr(MCID, DebugLoc()); 255 MBB->insert(MII, MI); 256 ASSERT_TRUE(std::distance(MIS.begin(), MII) == 1); 257 } 258 259 TEST(MachineInstrExtraInfo, AddExtraInfo) { 260 LLVMContext Ctx; 261 Module Mod("Module", Ctx); 262 auto MF = createMachineFunction(Ctx, Mod); 263 MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, nullptr, nullptr, nullptr}; 264 265 auto MI = MF->CreateMachineInstr(MCID, DebugLoc()); 266 auto MAI = MCAsmInfo(); 267 auto MC = createMCContext(&MAI); 268 auto MMO = MF->getMachineMemOperand(MachinePointerInfo(), 269 MachineMemOperand::MOLoad, 8, Align(8)); 270 SmallVector<MachineMemOperand *, 2> MMOs; 271 MMOs.push_back(MMO); 272 MCSymbol *Sym1 = MC->createTempSymbol("pre_label", false); 273 MCSymbol *Sym2 = MC->createTempSymbol("post_label", false); 274 MDNode *HAM = MDNode::getDistinct(Ctx, None); 275 MDNode *PCS = MDNode::getDistinct(Ctx, None); 276 277 ASSERT_TRUE(MI->memoperands_empty()); 278 ASSERT_FALSE(MI->getPreInstrSymbol()); 279 ASSERT_FALSE(MI->getPostInstrSymbol()); 280 ASSERT_FALSE(MI->getHeapAllocMarker()); 281 ASSERT_FALSE(MI->getPCSections()); 282 283 MI->setMemRefs(*MF, MMOs); 284 ASSERT_TRUE(MI->memoperands().size() == 1); 285 ASSERT_FALSE(MI->getPreInstrSymbol()); 286 ASSERT_FALSE(MI->getPostInstrSymbol()); 287 ASSERT_FALSE(MI->getHeapAllocMarker()); 288 ASSERT_FALSE(MI->getPCSections()); 289 290 MI->setPreInstrSymbol(*MF, Sym1); 291 ASSERT_TRUE(MI->memoperands().size() == 1); 292 ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1); 293 ASSERT_FALSE(MI->getPostInstrSymbol()); 294 ASSERT_FALSE(MI->getHeapAllocMarker()); 295 ASSERT_FALSE(MI->getPCSections()); 296 297 MI->setPostInstrSymbol(*MF, Sym2); 298 ASSERT_TRUE(MI->memoperands().size() == 1); 299 ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1); 300 ASSERT_TRUE(MI->getPostInstrSymbol() == Sym2); 301 ASSERT_FALSE(MI->getHeapAllocMarker()); 302 ASSERT_FALSE(MI->getPCSections()); 303 304 MI->setHeapAllocMarker(*MF, HAM); 305 ASSERT_TRUE(MI->memoperands().size() == 1); 306 ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1); 307 ASSERT_TRUE(MI->getPostInstrSymbol() == Sym2); 308 ASSERT_TRUE(MI->getHeapAllocMarker() == HAM); 309 ASSERT_FALSE(MI->getPCSections()); 310 311 MI->setPCSections(*MF, PCS); 312 ASSERT_TRUE(MI->memoperands().size() == 1); 313 ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1); 314 ASSERT_TRUE(MI->getPostInstrSymbol() == Sym2); 315 ASSERT_TRUE(MI->getHeapAllocMarker() == HAM); 316 ASSERT_TRUE(MI->getPCSections() == PCS); 317 } 318 319 TEST(MachineInstrExtraInfo, ChangeExtraInfo) { 320 LLVMContext Ctx; 321 Module Mod("Module", Ctx); 322 auto MF = createMachineFunction(Ctx, Mod); 323 MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, nullptr, nullptr, nullptr}; 324 325 auto MI = MF->CreateMachineInstr(MCID, DebugLoc()); 326 auto MAI = MCAsmInfo(); 327 auto MC = createMCContext(&MAI); 328 auto MMO = MF->getMachineMemOperand(MachinePointerInfo(), 329 MachineMemOperand::MOLoad, 8, Align(8)); 330 SmallVector<MachineMemOperand *, 2> MMOs; 331 MMOs.push_back(MMO); 332 MCSymbol *Sym1 = MC->createTempSymbol("pre_label", false); 333 MCSymbol *Sym2 = MC->createTempSymbol("post_label", false); 334 MDNode *HAM = MDNode::getDistinct(Ctx, None); 335 MDNode *PCS = MDNode::getDistinct(Ctx, None); 336 337 MI->setMemRefs(*MF, MMOs); 338 MI->setPreInstrSymbol(*MF, Sym1); 339 MI->setPostInstrSymbol(*MF, Sym2); 340 MI->setHeapAllocMarker(*MF, HAM); 341 MI->setPCSections(*MF, PCS); 342 343 MMOs.push_back(MMO); 344 345 MI->setMemRefs(*MF, MMOs); 346 ASSERT_TRUE(MI->memoperands().size() == 2); 347 ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1); 348 ASSERT_TRUE(MI->getPostInstrSymbol() == Sym2); 349 ASSERT_TRUE(MI->getHeapAllocMarker() == HAM); 350 ASSERT_TRUE(MI->getPCSections() == PCS); 351 352 MI->setPostInstrSymbol(*MF, Sym1); 353 ASSERT_TRUE(MI->memoperands().size() == 2); 354 ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1); 355 ASSERT_TRUE(MI->getPostInstrSymbol() == Sym1); 356 ASSERT_TRUE(MI->getHeapAllocMarker() == HAM); 357 ASSERT_TRUE(MI->getPCSections() == PCS); 358 } 359 360 TEST(MachineInstrExtraInfo, RemoveExtraInfo) { 361 LLVMContext Ctx; 362 Module Mod("Module", Ctx); 363 auto MF = createMachineFunction(Ctx, Mod); 364 MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, nullptr, nullptr, nullptr}; 365 366 auto MI = MF->CreateMachineInstr(MCID, DebugLoc()); 367 auto MAI = MCAsmInfo(); 368 auto MC = createMCContext(&MAI); 369 auto MMO = MF->getMachineMemOperand(MachinePointerInfo(), 370 MachineMemOperand::MOLoad, 8, Align(8)); 371 SmallVector<MachineMemOperand *, 2> MMOs; 372 MMOs.push_back(MMO); 373 MMOs.push_back(MMO); 374 MCSymbol *Sym1 = MC->createTempSymbol("pre_label", false); 375 MCSymbol *Sym2 = MC->createTempSymbol("post_label", false); 376 MDNode *HAM = MDNode::getDistinct(Ctx, None); 377 MDNode *PCS = MDNode::getDistinct(Ctx, None); 378 379 MI->setMemRefs(*MF, MMOs); 380 MI->setPreInstrSymbol(*MF, Sym1); 381 MI->setPostInstrSymbol(*MF, Sym2); 382 MI->setHeapAllocMarker(*MF, HAM); 383 MI->setPCSections(*MF, PCS); 384 385 MI->setPostInstrSymbol(*MF, nullptr); 386 ASSERT_TRUE(MI->memoperands().size() == 2); 387 ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1); 388 ASSERT_FALSE(MI->getPostInstrSymbol()); 389 ASSERT_TRUE(MI->getHeapAllocMarker() == HAM); 390 ASSERT_TRUE(MI->getPCSections() == PCS); 391 392 MI->setHeapAllocMarker(*MF, nullptr); 393 ASSERT_TRUE(MI->memoperands().size() == 2); 394 ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1); 395 ASSERT_FALSE(MI->getPostInstrSymbol()); 396 ASSERT_FALSE(MI->getHeapAllocMarker()); 397 ASSERT_TRUE(MI->getPCSections() == PCS); 398 399 MI->setPCSections(*MF, nullptr); 400 ASSERT_TRUE(MI->memoperands().size() == 2); 401 ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1); 402 ASSERT_FALSE(MI->getPostInstrSymbol()); 403 ASSERT_FALSE(MI->getHeapAllocMarker()); 404 ASSERT_FALSE(MI->getPCSections()); 405 406 MI->setPreInstrSymbol(*MF, nullptr); 407 ASSERT_TRUE(MI->memoperands().size() == 2); 408 ASSERT_FALSE(MI->getPreInstrSymbol()); 409 ASSERT_FALSE(MI->getPostInstrSymbol()); 410 ASSERT_FALSE(MI->getHeapAllocMarker()); 411 ASSERT_FALSE(MI->getPCSections()); 412 413 MI->setMemRefs(*MF, {}); 414 ASSERT_TRUE(MI->memoperands_empty()); 415 ASSERT_FALSE(MI->getPreInstrSymbol()); 416 ASSERT_FALSE(MI->getPostInstrSymbol()); 417 ASSERT_FALSE(MI->getHeapAllocMarker()); 418 ASSERT_FALSE(MI->getPCSections()); 419 } 420 421 TEST(MachineInstrDebugValue, AddDebugValueOperand) { 422 LLVMContext Ctx; 423 Module Mod("Module", Ctx); 424 auto MF = createMachineFunction(Ctx, Mod); 425 426 for (const unsigned short Opcode : 427 {TargetOpcode::DBG_VALUE, TargetOpcode::DBG_VALUE_LIST, 428 TargetOpcode::DBG_INSTR_REF, TargetOpcode::DBG_PHI, 429 TargetOpcode::DBG_LABEL}) { 430 const MCInstrDesc MCID = { 431 Opcode, 0, 0, 432 0, 0, (1ULL << MCID::Pseudo) | (1ULL << MCID::Variadic), 433 0, nullptr, nullptr, 434 nullptr}; 435 436 auto *MI = MF->CreateMachineInstr(MCID, DebugLoc()); 437 MI->addOperand(*MF, MachineOperand::CreateReg(0, /*isDef*/ false)); 438 439 MI->addOperand(*MF, MachineOperand::CreateImm(0)); 440 MI->getOperand(1).ChangeToRegister(0, false); 441 442 ASSERT_TRUE(MI->getOperand(0).isDebug()); 443 ASSERT_TRUE(MI->getOperand(1).isDebug()); 444 } 445 } 446 447 MATCHER_P(HasMIMetadata, MIMD, "") { 448 return arg->getDebugLoc() == MIMD.getDL() && 449 arg->getPCSections() == MIMD.getPCSections(); 450 } 451 452 TEST(MachineInstrBuilder, BuildMI) { 453 LLVMContext Ctx; 454 MDNode *PCS = MDNode::getDistinct(Ctx, None); 455 MDNode *DI = MDNode::getDistinct(Ctx, None); 456 DebugLoc DL(DI); 457 MIMetadata MIMD(DL, PCS); 458 EXPECT_EQ(MIMD.getDL(), DL); 459 EXPECT_EQ(MIMD.getPCSections(), PCS); 460 // Check common BuildMI() overloads propagate MIMetadata. 461 Module Mod("Module", Ctx); 462 auto MF = createMachineFunction(Ctx, Mod); 463 auto MBB = MF->CreateMachineBasicBlock(); 464 MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 0, nullptr, nullptr, nullptr}; 465 EXPECT_THAT(BuildMI(*MF, MIMD, MCID), HasMIMetadata(MIMD)); 466 EXPECT_THAT(BuildMI(*MF, MIMD, MCID), HasMIMetadata(MIMD)); 467 EXPECT_THAT(BuildMI(*MBB, MBB->end(), MIMD, MCID), HasMIMetadata(MIMD)); 468 EXPECT_THAT(BuildMI(*MBB, MBB->end(), MIMD, MCID), HasMIMetadata(MIMD)); 469 EXPECT_THAT(BuildMI(*MBB, MBB->instr_end(), MIMD, MCID), HasMIMetadata(MIMD)); 470 EXPECT_THAT(BuildMI(*MBB, *MBB->begin(), MIMD, MCID), HasMIMetadata(MIMD)); 471 EXPECT_THAT(BuildMI(*MBB, &*MBB->begin(), MIMD, MCID), HasMIMetadata(MIMD)); 472 EXPECT_THAT(BuildMI(MBB, MIMD, MCID), HasMIMetadata(MIMD)); 473 } 474 475 static_assert(std::is_trivially_copyable<MCOperand>::value, 476 "trivially copyable"); 477 478 } // end namespace 479