1 //===- MachineInstrTest.cpp -----------------------------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "llvm/CodeGen/MachineBasicBlock.h" 10 #include "llvm/CodeGen/MachineInstr.h" 11 #include "llvm/CodeGen/MachineFunction.h" 12 #include "llvm/CodeGen/MachineMemOperand.h" 13 #include "llvm/CodeGen/MachineModuleInfo.h" 14 #include "llvm/CodeGen/TargetFrameLowering.h" 15 #include "llvm/CodeGen/TargetInstrInfo.h" 16 #include "llvm/CodeGen/TargetLowering.h" 17 #include "llvm/CodeGen/TargetSubtargetInfo.h" 18 #include "llvm/IR/DebugInfoMetadata.h" 19 #include "llvm/IR/ModuleSlotTracker.h" 20 #include "llvm/MC/MCAsmInfo.h" 21 #include "llvm/MC/MCSymbol.h" 22 #include "llvm/Support/TargetRegistry.h" 23 #include "llvm/Support/TargetSelect.h" 24 #include "llvm/Target/TargetMachine.h" 25 #include "llvm/Target/TargetOptions.h" 26 #include "gtest/gtest.h" 27 28 using namespace llvm; 29 30 namespace { 31 // Add a few Bogus backend classes so we can create MachineInstrs without 32 // depending on a real target. 33 class BogusTargetLowering : public TargetLowering { 34 public: 35 BogusTargetLowering(TargetMachine &TM) : TargetLowering(TM) {} 36 }; 37 38 class BogusFrameLowering : public TargetFrameLowering { 39 public: 40 BogusFrameLowering() 41 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, Align(4), 4) {} 42 43 void emitPrologue(MachineFunction &MF, 44 MachineBasicBlock &MBB) const override {} 45 void emitEpilogue(MachineFunction &MF, 46 MachineBasicBlock &MBB) const override {} 47 bool hasFP(const MachineFunction &MF) const override { return false; } 48 }; 49 50 static TargetRegisterClass *const BogusRegisterClasses[] = {nullptr}; 51 52 class BogusRegisterInfo : public TargetRegisterInfo { 53 public: 54 BogusRegisterInfo() 55 : TargetRegisterInfo(nullptr, BogusRegisterClasses, BogusRegisterClasses, 56 nullptr, nullptr, LaneBitmask(~0u), nullptr) { 57 InitMCRegisterInfo(nullptr, 0, 0, 0, nullptr, 0, nullptr, 0, nullptr, 58 nullptr, nullptr, nullptr, nullptr, 0, nullptr, nullptr); 59 } 60 61 const MCPhysReg * 62 getCalleeSavedRegs(const MachineFunction *MF) const override { 63 return nullptr; 64 } 65 ArrayRef<const uint32_t *> getRegMasks() const override { return None; } 66 ArrayRef<const char *> getRegMaskNames() const override { return None; } 67 BitVector getReservedRegs(const MachineFunction &MF) const override { 68 return BitVector(); 69 } 70 const RegClassWeight & 71 getRegClassWeight(const TargetRegisterClass *RC) const override { 72 static RegClassWeight Bogus{1, 16}; 73 return Bogus; 74 } 75 unsigned getRegUnitWeight(unsigned RegUnit) const override { return 1; } 76 unsigned getNumRegPressureSets() const override { return 0; } 77 const char *getRegPressureSetName(unsigned Idx) const override { 78 return "bogus"; 79 } 80 unsigned getRegPressureSetLimit(const MachineFunction &MF, 81 unsigned Idx) const override { 82 return 0; 83 } 84 const int * 85 getRegClassPressureSets(const TargetRegisterClass *RC) const override { 86 static const int Bogus[] = {0, -1}; 87 return &Bogus[0]; 88 } 89 const int *getRegUnitPressureSets(unsigned RegUnit) const override { 90 static const int Bogus[] = {0, -1}; 91 return &Bogus[0]; 92 } 93 94 Register getFrameRegister(const MachineFunction &MF) const override { 95 return 0; 96 } 97 void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, 98 unsigned FIOperandNum, 99 RegScavenger *RS = nullptr) const override {} 100 }; 101 102 class BogusSubtarget : public TargetSubtargetInfo { 103 public: 104 BogusSubtarget(TargetMachine &TM) 105 : TargetSubtargetInfo(Triple(""), "", "", {}, {}, nullptr, nullptr, 106 nullptr, nullptr, nullptr, nullptr), 107 FL(), TL(TM) {} 108 ~BogusSubtarget() override {} 109 110 const TargetFrameLowering *getFrameLowering() const override { return &FL; } 111 112 const TargetLowering *getTargetLowering() const override { return &TL; } 113 114 const TargetInstrInfo *getInstrInfo() const override { return &TII; } 115 116 const TargetRegisterInfo *getRegisterInfo() const override { return &TRI; } 117 118 private: 119 BogusFrameLowering FL; 120 BogusRegisterInfo TRI; 121 BogusTargetLowering TL; 122 TargetInstrInfo TII; 123 }; 124 125 class BogusTargetMachine : public LLVMTargetMachine { 126 public: 127 BogusTargetMachine() 128 : LLVMTargetMachine(Target(), "", Triple(""), "", "", TargetOptions(), 129 Reloc::Static, CodeModel::Small, CodeGenOpt::Default), 130 ST(*this) {} 131 132 ~BogusTargetMachine() override {} 133 134 const TargetSubtargetInfo *getSubtargetImpl(const Function &) const override { 135 return &ST; 136 } 137 138 private: 139 BogusSubtarget ST; 140 }; 141 142 class BogusMCContext : public MCContext { 143 public: 144 BogusMCContext(MCAsmInfo *mai) 145 : MCContext(mai, nullptr, nullptr, nullptr, nullptr, false) {} 146 }; 147 148 std::unique_ptr<BogusMCContext> createMCContext() { 149 MCAsmInfo mai = MCAsmInfo(); 150 return std::make_unique<BogusMCContext>(&mai); 151 } 152 153 std::unique_ptr<BogusTargetMachine> createTargetMachine() { 154 return std::make_unique<BogusTargetMachine>(); 155 } 156 157 std::unique_ptr<MachineFunction> createMachineFunction() { 158 LLVMContext Ctx; 159 Module M("Module", Ctx); 160 auto Type = FunctionType::get(Type::getVoidTy(Ctx), false); 161 auto F = Function::Create(Type, GlobalValue::ExternalLinkage, "Test", &M); 162 163 auto TM = createTargetMachine(); 164 unsigned FunctionNum = 42; 165 MachineModuleInfo MMI(TM.get()); 166 const TargetSubtargetInfo &STI = *TM->getSubtargetImpl(*F); 167 168 return std::make_unique<MachineFunction>(*F, *TM, STI, FunctionNum, MMI); 169 } 170 171 // This test makes sure that MachineInstr::isIdenticalTo handles Defs correctly 172 // for various combinations of IgnoreDefs, and also that it is symmetrical. 173 TEST(IsIdenticalToTest, DifferentDefs) { 174 auto MF = createMachineFunction(); 175 176 unsigned short NumOps = 2; 177 unsigned char NumDefs = 1; 178 MCOperandInfo OpInfo[] = { 179 {0, 0, MCOI::OPERAND_REGISTER, 0}, 180 {0, 1 << MCOI::OptionalDef, MCOI::OPERAND_REGISTER, 0}}; 181 MCInstrDesc MCID = { 182 0, NumOps, NumDefs, 0, 0, 1ULL << MCID::HasOptionalDef, 183 0, nullptr, nullptr, OpInfo, 0, nullptr}; 184 185 // Create two MIs with different virtual reg defs and the same uses. 186 unsigned VirtualDef1 = -42; // The value doesn't matter, but the sign does. 187 unsigned VirtualDef2 = -43; 188 unsigned VirtualUse = -44; 189 190 auto MI1 = MF->CreateMachineInstr(MCID, DebugLoc()); 191 MI1->addOperand(*MF, MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true)); 192 MI1->addOperand(*MF, MachineOperand::CreateReg(VirtualUse, /*isDef*/ false)); 193 194 auto MI2 = MF->CreateMachineInstr(MCID, DebugLoc()); 195 MI2->addOperand(*MF, MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true)); 196 MI2->addOperand(*MF, MachineOperand::CreateReg(VirtualUse, /*isDef*/ false)); 197 198 // Check that they are identical when we ignore virtual register defs, but not 199 // when we check defs. 200 ASSERT_FALSE(MI1->isIdenticalTo(*MI2, MachineInstr::CheckDefs)); 201 ASSERT_FALSE(MI2->isIdenticalTo(*MI1, MachineInstr::CheckDefs)); 202 203 ASSERT_TRUE(MI1->isIdenticalTo(*MI2, MachineInstr::IgnoreVRegDefs)); 204 ASSERT_TRUE(MI2->isIdenticalTo(*MI1, MachineInstr::IgnoreVRegDefs)); 205 206 // Create two MIs with different virtual reg defs, and a def or use of a 207 // sentinel register. 208 unsigned SentinelReg = 0; 209 210 auto MI3 = MF->CreateMachineInstr(MCID, DebugLoc()); 211 MI3->addOperand(*MF, MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true)); 212 MI3->addOperand(*MF, MachineOperand::CreateReg(SentinelReg, /*isDef*/ true)); 213 214 auto MI4 = MF->CreateMachineInstr(MCID, DebugLoc()); 215 MI4->addOperand(*MF, MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true)); 216 MI4->addOperand(*MF, MachineOperand::CreateReg(SentinelReg, /*isDef*/ false)); 217 218 // Check that they are never identical. 219 ASSERT_FALSE(MI3->isIdenticalTo(*MI4, MachineInstr::CheckDefs)); 220 ASSERT_FALSE(MI4->isIdenticalTo(*MI3, MachineInstr::CheckDefs)); 221 222 ASSERT_FALSE(MI3->isIdenticalTo(*MI4, MachineInstr::IgnoreVRegDefs)); 223 ASSERT_FALSE(MI4->isIdenticalTo(*MI3, MachineInstr::IgnoreVRegDefs)); 224 } 225 226 // Check that MachineInstrExpressionTrait::isEqual is symmetric and in sync with 227 // MachineInstrExpressionTrait::getHashValue 228 void checkHashAndIsEqualMatch(MachineInstr *MI1, MachineInstr *MI2) { 229 bool IsEqual1 = MachineInstrExpressionTrait::isEqual(MI1, MI2); 230 bool IsEqual2 = MachineInstrExpressionTrait::isEqual(MI2, MI1); 231 232 ASSERT_EQ(IsEqual1, IsEqual2); 233 234 auto Hash1 = MachineInstrExpressionTrait::getHashValue(MI1); 235 auto Hash2 = MachineInstrExpressionTrait::getHashValue(MI2); 236 237 ASSERT_EQ(IsEqual1, Hash1 == Hash2); 238 } 239 240 // This test makes sure that MachineInstrExpressionTraits::isEqual is in sync 241 // with MachineInstrExpressionTraits::getHashValue. 242 TEST(MachineInstrExpressionTraitTest, IsEqualAgreesWithGetHashValue) { 243 auto MF = createMachineFunction(); 244 245 unsigned short NumOps = 2; 246 unsigned char NumDefs = 1; 247 MCOperandInfo OpInfo[] = { 248 {0, 0, MCOI::OPERAND_REGISTER, 0}, 249 {0, 1 << MCOI::OptionalDef, MCOI::OPERAND_REGISTER, 0}}; 250 MCInstrDesc MCID = { 251 0, NumOps, NumDefs, 0, 0, 1ULL << MCID::HasOptionalDef, 252 0, nullptr, nullptr, OpInfo, 0, nullptr}; 253 254 // Define a series of instructions with different kinds of operands and make 255 // sure that the hash function is consistent with isEqual for various 256 // combinations of them. 257 unsigned VirtualDef1 = -42; 258 unsigned VirtualDef2 = -43; 259 unsigned VirtualReg = -44; 260 unsigned SentinelReg = 0; 261 unsigned PhysicalReg = 45; 262 263 auto VD1VU = MF->CreateMachineInstr(MCID, DebugLoc()); 264 VD1VU->addOperand(*MF, 265 MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true)); 266 VD1VU->addOperand(*MF, 267 MachineOperand::CreateReg(VirtualReg, /*isDef*/ false)); 268 269 auto VD2VU = MF->CreateMachineInstr(MCID, DebugLoc()); 270 VD2VU->addOperand(*MF, 271 MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true)); 272 VD2VU->addOperand(*MF, 273 MachineOperand::CreateReg(VirtualReg, /*isDef*/ false)); 274 275 auto VD1SU = MF->CreateMachineInstr(MCID, DebugLoc()); 276 VD1SU->addOperand(*MF, 277 MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true)); 278 VD1SU->addOperand(*MF, 279 MachineOperand::CreateReg(SentinelReg, /*isDef*/ false)); 280 281 auto VD1SD = MF->CreateMachineInstr(MCID, DebugLoc()); 282 VD1SD->addOperand(*MF, 283 MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true)); 284 VD1SD->addOperand(*MF, 285 MachineOperand::CreateReg(SentinelReg, /*isDef*/ true)); 286 287 auto VD2PU = MF->CreateMachineInstr(MCID, DebugLoc()); 288 VD2PU->addOperand(*MF, 289 MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true)); 290 VD2PU->addOperand(*MF, 291 MachineOperand::CreateReg(PhysicalReg, /*isDef*/ false)); 292 293 auto VD2PD = MF->CreateMachineInstr(MCID, DebugLoc()); 294 VD2PD->addOperand(*MF, 295 MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true)); 296 VD2PD->addOperand(*MF, 297 MachineOperand::CreateReg(PhysicalReg, /*isDef*/ true)); 298 299 checkHashAndIsEqualMatch(VD1VU, VD2VU); 300 checkHashAndIsEqualMatch(VD1VU, VD1SU); 301 checkHashAndIsEqualMatch(VD1VU, VD1SD); 302 checkHashAndIsEqualMatch(VD1VU, VD2PU); 303 checkHashAndIsEqualMatch(VD1VU, VD2PD); 304 305 checkHashAndIsEqualMatch(VD2VU, VD1SU); 306 checkHashAndIsEqualMatch(VD2VU, VD1SD); 307 checkHashAndIsEqualMatch(VD2VU, VD2PU); 308 checkHashAndIsEqualMatch(VD2VU, VD2PD); 309 310 checkHashAndIsEqualMatch(VD1SU, VD1SD); 311 checkHashAndIsEqualMatch(VD1SU, VD2PU); 312 checkHashAndIsEqualMatch(VD1SU, VD2PD); 313 314 checkHashAndIsEqualMatch(VD1SD, VD2PU); 315 checkHashAndIsEqualMatch(VD1SD, VD2PD); 316 317 checkHashAndIsEqualMatch(VD2PU, VD2PD); 318 } 319 320 TEST(MachineInstrPrintingTest, DebugLocPrinting) { 321 auto MF = createMachineFunction(); 322 323 MCOperandInfo OpInfo{0, 0, MCOI::OPERAND_REGISTER, 0}; 324 MCInstrDesc MCID = {0, 1, 1, 0, 0, 0, 325 0, nullptr, nullptr, &OpInfo, 0, nullptr}; 326 327 LLVMContext Ctx; 328 DIFile *DIF = DIFile::getDistinct(Ctx, "filename", ""); 329 DISubprogram *DIS = DISubprogram::getDistinct( 330 Ctx, nullptr, "", "", DIF, 0, nullptr, 0, nullptr, 0, 0, DINode::FlagZero, 331 DISubprogram::SPFlagZero, nullptr); 332 DILocation *DIL = DILocation::get(Ctx, 1, 5, DIS); 333 DebugLoc DL(DIL); 334 MachineInstr *MI = MF->CreateMachineInstr(MCID, DL); 335 MI->addOperand(*MF, MachineOperand::CreateReg(0, /*isDef*/ true)); 336 337 std::string str; 338 raw_string_ostream OS(str); 339 MI->print(OS, /*IsStandalone*/true, /*SkipOpers*/false, /*SkipDebugLoc*/false, 340 /*AddNewLine*/false); 341 ASSERT_TRUE( 342 StringRef(OS.str()).startswith("$noreg = UNKNOWN debug-location ")); 343 ASSERT_TRUE( 344 StringRef(OS.str()).endswith("filename:1:5")); 345 } 346 347 TEST(MachineInstrSpan, DistanceBegin) { 348 auto MF = createMachineFunction(); 349 auto MBB = MF->CreateMachineBasicBlock(); 350 351 MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 352 0, nullptr, nullptr, nullptr, 0, nullptr}; 353 354 auto MII = MBB->begin(); 355 MachineInstrSpan MIS(MII, MBB); 356 ASSERT_TRUE(MIS.empty()); 357 358 auto MI = MF->CreateMachineInstr(MCID, DebugLoc()); 359 MBB->insert(MII, MI); 360 ASSERT_TRUE(std::distance(MIS.begin(), MII) == 1); 361 } 362 363 TEST(MachineInstrSpan, DistanceEnd) { 364 auto MF = createMachineFunction(); 365 auto MBB = MF->CreateMachineBasicBlock(); 366 367 MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 368 0, nullptr, nullptr, nullptr, 0, nullptr}; 369 370 auto MII = MBB->end(); 371 MachineInstrSpan MIS(MII, MBB); 372 ASSERT_TRUE(MIS.empty()); 373 374 auto MI = MF->CreateMachineInstr(MCID, DebugLoc()); 375 MBB->insert(MII, MI); 376 ASSERT_TRUE(std::distance(MIS.begin(), MII) == 1); 377 } 378 379 TEST(MachineInstrExtraInfo, AddExtraInfo) { 380 auto MF = createMachineFunction(); 381 MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 382 0, nullptr, nullptr, nullptr, 0, nullptr}; 383 384 auto MI = MF->CreateMachineInstr(MCID, DebugLoc()); 385 auto MC = createMCContext(); 386 auto MMO = MF->getMachineMemOperand(MachinePointerInfo(), 387 MachineMemOperand::MOLoad, 8, 8); 388 SmallVector<MachineMemOperand *, 2> MMOs; 389 MMOs.push_back(MMO); 390 MCSymbol *Sym1 = MC->createTempSymbol("pre_label", false); 391 MCSymbol *Sym2 = MC->createTempSymbol("post_label", false); 392 LLVMContext Ctx; 393 MDNode *MDN = MDNode::getDistinct(Ctx, None); 394 395 ASSERT_TRUE(MI->memoperands_empty()); 396 ASSERT_FALSE(MI->getPreInstrSymbol()); 397 ASSERT_FALSE(MI->getPostInstrSymbol()); 398 ASSERT_FALSE(MI->getHeapAllocMarker()); 399 400 MI->setMemRefs(*MF, MMOs); 401 ASSERT_TRUE(MI->memoperands().size() == 1); 402 ASSERT_FALSE(MI->getPreInstrSymbol()); 403 ASSERT_FALSE(MI->getPostInstrSymbol()); 404 ASSERT_FALSE(MI->getHeapAllocMarker()); 405 406 MI->setPreInstrSymbol(*MF, Sym1); 407 ASSERT_TRUE(MI->memoperands().size() == 1); 408 ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1); 409 ASSERT_FALSE(MI->getPostInstrSymbol()); 410 ASSERT_FALSE(MI->getHeapAllocMarker()); 411 412 MI->setPostInstrSymbol(*MF, Sym2); 413 ASSERT_TRUE(MI->memoperands().size() == 1); 414 ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1); 415 ASSERT_TRUE(MI->getPostInstrSymbol() == Sym2); 416 ASSERT_FALSE(MI->getHeapAllocMarker()); 417 418 MI->setHeapAllocMarker(*MF, MDN); 419 ASSERT_TRUE(MI->memoperands().size() == 1); 420 ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1); 421 ASSERT_TRUE(MI->getPostInstrSymbol() == Sym2); 422 ASSERT_TRUE(MI->getHeapAllocMarker() == MDN); 423 } 424 425 TEST(MachineInstrExtraInfo, ChangeExtraInfo) { 426 auto MF = createMachineFunction(); 427 MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 428 0, nullptr, nullptr, nullptr, 0, nullptr}; 429 430 auto MI = MF->CreateMachineInstr(MCID, DebugLoc()); 431 auto MC = createMCContext(); 432 auto MMO = MF->getMachineMemOperand(MachinePointerInfo(), 433 MachineMemOperand::MOLoad, 8, 8); 434 SmallVector<MachineMemOperand *, 2> MMOs; 435 MMOs.push_back(MMO); 436 MCSymbol *Sym1 = MC->createTempSymbol("pre_label", false); 437 MCSymbol *Sym2 = MC->createTempSymbol("post_label", false); 438 LLVMContext Ctx; 439 MDNode *MDN = MDNode::getDistinct(Ctx, None); 440 441 MI->setMemRefs(*MF, MMOs); 442 MI->setPreInstrSymbol(*MF, Sym1); 443 MI->setPostInstrSymbol(*MF, Sym2); 444 MI->setHeapAllocMarker(*MF, MDN); 445 446 MMOs.push_back(MMO); 447 448 MI->setMemRefs(*MF, MMOs); 449 ASSERT_TRUE(MI->memoperands().size() == 2); 450 ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1); 451 ASSERT_TRUE(MI->getPostInstrSymbol() == Sym2); 452 ASSERT_TRUE(MI->getHeapAllocMarker() == MDN); 453 454 MI->setPostInstrSymbol(*MF, Sym1); 455 ASSERT_TRUE(MI->memoperands().size() == 2); 456 ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1); 457 ASSERT_TRUE(MI->getPostInstrSymbol() == Sym1); 458 ASSERT_TRUE(MI->getHeapAllocMarker() == MDN); 459 } 460 461 TEST(MachineInstrExtraInfo, RemoveExtraInfo) { 462 auto MF = createMachineFunction(); 463 MCInstrDesc MCID = {0, 0, 0, 0, 0, 0, 464 0, nullptr, nullptr, nullptr, 0, nullptr}; 465 466 auto MI = MF->CreateMachineInstr(MCID, DebugLoc()); 467 auto MC = createMCContext(); 468 auto MMO = MF->getMachineMemOperand(MachinePointerInfo(), 469 MachineMemOperand::MOLoad, 8, 8); 470 SmallVector<MachineMemOperand *, 2> MMOs; 471 MMOs.push_back(MMO); 472 MMOs.push_back(MMO); 473 MCSymbol *Sym1 = MC->createTempSymbol("pre_label", false); 474 MCSymbol *Sym2 = MC->createTempSymbol("post_label", false); 475 LLVMContext Ctx; 476 MDNode *MDN = MDNode::getDistinct(Ctx, None); 477 478 MI->setMemRefs(*MF, MMOs); 479 MI->setPreInstrSymbol(*MF, Sym1); 480 MI->setPostInstrSymbol(*MF, Sym2); 481 MI->setHeapAllocMarker(*MF, MDN); 482 483 MI->setPostInstrSymbol(*MF, nullptr); 484 ASSERT_TRUE(MI->memoperands().size() == 2); 485 ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1); 486 ASSERT_FALSE(MI->getPostInstrSymbol()); 487 ASSERT_TRUE(MI->getHeapAllocMarker() == MDN); 488 489 MI->setHeapAllocMarker(*MF, nullptr); 490 ASSERT_TRUE(MI->memoperands().size() == 2); 491 ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1); 492 ASSERT_FALSE(MI->getPostInstrSymbol()); 493 ASSERT_FALSE(MI->getHeapAllocMarker()); 494 495 MI->setPreInstrSymbol(*MF, nullptr); 496 ASSERT_TRUE(MI->memoperands().size() == 2); 497 ASSERT_FALSE(MI->getPreInstrSymbol()); 498 ASSERT_FALSE(MI->getPostInstrSymbol()); 499 ASSERT_FALSE(MI->getHeapAllocMarker()); 500 501 MI->setMemRefs(*MF, {}); 502 ASSERT_TRUE(MI->memoperands_empty()); 503 ASSERT_FALSE(MI->getPreInstrSymbol()); 504 ASSERT_FALSE(MI->getPostInstrSymbol()); 505 ASSERT_FALSE(MI->getHeapAllocMarker()); 506 } 507 508 static_assert(is_trivially_copyable<MCOperand>::value, "trivially copyable"); 509 510 } // end namespace 511