xref: /llvm-project/llvm/unittests/CodeGen/MachineInstrTest.cpp (revision 329c03204069f3dc02cd2a968b9519457aad507b) 
1 //===- MachineInstrTest.cpp -----------------------------------------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "llvm/CodeGen/MachineBasicBlock.h"
10 #include "llvm/CodeGen/MachineInstr.h"
11 #include "llvm/CodeGen/MachineFunction.h"
12 #include "llvm/CodeGen/MachineModuleInfo.h"
13 #include "llvm/CodeGen/TargetFrameLowering.h"
14 #include "llvm/CodeGen/TargetInstrInfo.h"
15 #include "llvm/CodeGen/TargetLowering.h"
16 #include "llvm/CodeGen/TargetSubtargetInfo.h"
17 #include "llvm/IR/DebugInfoMetadata.h"
18 #include "llvm/IR/ModuleSlotTracker.h"
19 #include "llvm/Support/TargetRegistry.h"
20 #include "llvm/Support/TargetSelect.h"
21 #include "llvm/Target/TargetMachine.h"
22 #include "llvm/Target/TargetOptions.h"
23 #include "gtest/gtest.h"
24 
25 using namespace llvm;
26 
27 namespace {
28 // Add a few Bogus backend classes so we can create MachineInstrs without
29 // depending on a real target.
30 class BogusTargetLowering : public TargetLowering {
31 public:
32   BogusTargetLowering(TargetMachine &TM) : TargetLowering(TM) {}
33 };
34 
35 class BogusFrameLowering : public TargetFrameLowering {
36 public:
37   BogusFrameLowering()
38       : TargetFrameLowering(TargetFrameLowering::StackGrowsDown, 4, 4) {}
39 
40   void emitPrologue(MachineFunction &MF,
41                     MachineBasicBlock &MBB) const override {}
42   void emitEpilogue(MachineFunction &MF,
43                     MachineBasicBlock &MBB) const override {}
44   bool hasFP(const MachineFunction &MF) const override { return false; }
45 };
46 
47 static TargetRegisterClass *const BogusRegisterClasses[] = {nullptr};
48 
49 class BogusRegisterInfo : public TargetRegisterInfo {
50 public:
51   BogusRegisterInfo()
52       : TargetRegisterInfo(nullptr, BogusRegisterClasses, BogusRegisterClasses,
53                            nullptr, nullptr, LaneBitmask(~0u), nullptr) {}
54 
55   const MCPhysReg *
56   getCalleeSavedRegs(const MachineFunction *MF) const override {
57     return nullptr;
58   }
59   ArrayRef<const uint32_t *> getRegMasks() const override { return None; }
60   ArrayRef<const char *> getRegMaskNames() const override { return None; }
61   BitVector getReservedRegs(const MachineFunction &MF) const override {
62     return BitVector();
63   }
64   const RegClassWeight &
65   getRegClassWeight(const TargetRegisterClass *RC) const override {
66     static RegClassWeight Bogus{1, 16};
67     return Bogus;
68   }
69   unsigned getRegUnitWeight(unsigned RegUnit) const override { return 1; }
70   unsigned getNumRegPressureSets() const override { return 0; }
71   const char *getRegPressureSetName(unsigned Idx) const override {
72     return "bogus";
73   }
74   unsigned getRegPressureSetLimit(const MachineFunction &MF,
75                                   unsigned Idx) const override {
76     return 0;
77   }
78   const int *
79   getRegClassPressureSets(const TargetRegisterClass *RC) const override {
80     static const int Bogus[] = {0, -1};
81     return &Bogus[0];
82   }
83   const int *getRegUnitPressureSets(unsigned RegUnit) const override {
84     static const int Bogus[] = {0, -1};
85     return &Bogus[0];
86   }
87 
88   Register getFrameRegister(const MachineFunction &MF) const override {
89     return 0;
90   }
91   void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
92                            unsigned FIOperandNum,
93                            RegScavenger *RS = nullptr) const override {}
94 };
95 
96 class BogusSubtarget : public TargetSubtargetInfo {
97 public:
98   BogusSubtarget(TargetMachine &TM)
99       : TargetSubtargetInfo(Triple(""), "", "", {}, {}, nullptr, nullptr,
100                             nullptr, nullptr, nullptr, nullptr),
101         FL(), TL(TM) {}
102   ~BogusSubtarget() override {}
103 
104   const TargetFrameLowering *getFrameLowering() const override { return &FL; }
105 
106   const TargetLowering *getTargetLowering() const override { return &TL; }
107 
108   const TargetInstrInfo *getInstrInfo() const override { return &TII; }
109 
110   const TargetRegisterInfo *getRegisterInfo() const override { return &TRI; }
111 
112 private:
113   BogusFrameLowering FL;
114   BogusRegisterInfo TRI;
115   BogusTargetLowering TL;
116   TargetInstrInfo TII;
117 };
118 
119 class BogusTargetMachine : public LLVMTargetMachine {
120 public:
121   BogusTargetMachine()
122       : LLVMTargetMachine(Target(), "", Triple(""), "", "", TargetOptions(),
123                           Reloc::Static, CodeModel::Small, CodeGenOpt::Default),
124         ST(*this) {}
125   ~BogusTargetMachine() override {}
126 
127   const TargetSubtargetInfo *getSubtargetImpl(const Function &) const override {
128     return &ST;
129   }
130 
131 private:
132   BogusSubtarget ST;
133 };
134 
135 std::unique_ptr<BogusTargetMachine> createTargetMachine() {
136   return llvm::make_unique<BogusTargetMachine>();
137 }
138 
139 std::unique_ptr<MachineFunction> createMachineFunction() {
140   LLVMContext Ctx;
141   Module M("Module", Ctx);
142   auto Type = FunctionType::get(Type::getVoidTy(Ctx), false);
143   auto F = Function::Create(Type, GlobalValue::ExternalLinkage, "Test", &M);
144 
145   auto TM = createTargetMachine();
146   unsigned FunctionNum = 42;
147   MachineModuleInfo MMI(TM.get());
148   const TargetSubtargetInfo &STI = *TM->getSubtargetImpl(*F);
149 
150   return llvm::make_unique<MachineFunction>(*F, *TM, STI, FunctionNum, MMI);
151 }
152 
153 // This test makes sure that MachineInstr::isIdenticalTo handles Defs correctly
154 // for various combinations of IgnoreDefs, and also that it is symmetrical.
155 TEST(IsIdenticalToTest, DifferentDefs) {
156   auto MF = createMachineFunction();
157 
158   unsigned short NumOps = 2;
159   unsigned char NumDefs = 1;
160   MCOperandInfo OpInfo[] = {
161       {0, 0, MCOI::OPERAND_REGISTER, 0},
162       {0, 1 << MCOI::OptionalDef, MCOI::OPERAND_REGISTER, 0}};
163   MCInstrDesc MCID = {
164       0, NumOps,  NumDefs, 0,      0, 1ULL << MCID::HasOptionalDef,
165       0, nullptr, nullptr, OpInfo, 0, nullptr};
166 
167   // Create two MIs with different virtual reg defs and the same uses.
168   unsigned VirtualDef1 = -42; // The value doesn't matter, but the sign does.
169   unsigned VirtualDef2 = -43;
170   unsigned VirtualUse = -44;
171 
172   auto MI1 = MF->CreateMachineInstr(MCID, DebugLoc());
173   MI1->addOperand(*MF, MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
174   MI1->addOperand(*MF, MachineOperand::CreateReg(VirtualUse, /*isDef*/ false));
175 
176   auto MI2 = MF->CreateMachineInstr(MCID, DebugLoc());
177   MI2->addOperand(*MF, MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
178   MI2->addOperand(*MF, MachineOperand::CreateReg(VirtualUse, /*isDef*/ false));
179 
180   // Check that they are identical when we ignore virtual register defs, but not
181   // when we check defs.
182   ASSERT_FALSE(MI1->isIdenticalTo(*MI2, MachineInstr::CheckDefs));
183   ASSERT_FALSE(MI2->isIdenticalTo(*MI1, MachineInstr::CheckDefs));
184 
185   ASSERT_TRUE(MI1->isIdenticalTo(*MI2, MachineInstr::IgnoreVRegDefs));
186   ASSERT_TRUE(MI2->isIdenticalTo(*MI1, MachineInstr::IgnoreVRegDefs));
187 
188   // Create two MIs with different virtual reg defs, and a def or use of a
189   // sentinel register.
190   unsigned SentinelReg = 0;
191 
192   auto MI3 = MF->CreateMachineInstr(MCID, DebugLoc());
193   MI3->addOperand(*MF, MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
194   MI3->addOperand(*MF, MachineOperand::CreateReg(SentinelReg, /*isDef*/ true));
195 
196   auto MI4 = MF->CreateMachineInstr(MCID, DebugLoc());
197   MI4->addOperand(*MF, MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
198   MI4->addOperand(*MF, MachineOperand::CreateReg(SentinelReg, /*isDef*/ false));
199 
200   // Check that they are never identical.
201   ASSERT_FALSE(MI3->isIdenticalTo(*MI4, MachineInstr::CheckDefs));
202   ASSERT_FALSE(MI4->isIdenticalTo(*MI3, MachineInstr::CheckDefs));
203 
204   ASSERT_FALSE(MI3->isIdenticalTo(*MI4, MachineInstr::IgnoreVRegDefs));
205   ASSERT_FALSE(MI4->isIdenticalTo(*MI3, MachineInstr::IgnoreVRegDefs));
206 }
207 
208 // Check that MachineInstrExpressionTrait::isEqual is symmetric and in sync with
209 // MachineInstrExpressionTrait::getHashValue
210 void checkHashAndIsEqualMatch(MachineInstr *MI1, MachineInstr *MI2) {
211   bool IsEqual1 = MachineInstrExpressionTrait::isEqual(MI1, MI2);
212   bool IsEqual2 = MachineInstrExpressionTrait::isEqual(MI2, MI1);
213 
214   ASSERT_EQ(IsEqual1, IsEqual2);
215 
216   auto Hash1 = MachineInstrExpressionTrait::getHashValue(MI1);
217   auto Hash2 = MachineInstrExpressionTrait::getHashValue(MI2);
218 
219   ASSERT_EQ(IsEqual1, Hash1 == Hash2);
220 }
221 
222 // This test makes sure that MachineInstrExpressionTraits::isEqual is in sync
223 // with MachineInstrExpressionTraits::getHashValue.
224 TEST(MachineInstrExpressionTraitTest, IsEqualAgreesWithGetHashValue) {
225   auto MF = createMachineFunction();
226 
227   unsigned short NumOps = 2;
228   unsigned char NumDefs = 1;
229   MCOperandInfo OpInfo[] = {
230       {0, 0, MCOI::OPERAND_REGISTER, 0},
231       {0, 1 << MCOI::OptionalDef, MCOI::OPERAND_REGISTER, 0}};
232   MCInstrDesc MCID = {
233       0, NumOps,  NumDefs, 0,      0, 1ULL << MCID::HasOptionalDef,
234       0, nullptr, nullptr, OpInfo, 0, nullptr};
235 
236   // Define a series of instructions with different kinds of operands and make
237   // sure that the hash function is consistent with isEqual for various
238   // combinations of them.
239   unsigned VirtualDef1 = -42;
240   unsigned VirtualDef2 = -43;
241   unsigned VirtualReg = -44;
242   unsigned SentinelReg = 0;
243   unsigned PhysicalReg = 45;
244 
245   auto VD1VU = MF->CreateMachineInstr(MCID, DebugLoc());
246   VD1VU->addOperand(*MF,
247                     MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
248   VD1VU->addOperand(*MF,
249                     MachineOperand::CreateReg(VirtualReg, /*isDef*/ false));
250 
251   auto VD2VU = MF->CreateMachineInstr(MCID, DebugLoc());
252   VD2VU->addOperand(*MF,
253                     MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
254   VD2VU->addOperand(*MF,
255                     MachineOperand::CreateReg(VirtualReg, /*isDef*/ false));
256 
257   auto VD1SU = MF->CreateMachineInstr(MCID, DebugLoc());
258   VD1SU->addOperand(*MF,
259                     MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
260   VD1SU->addOperand(*MF,
261                     MachineOperand::CreateReg(SentinelReg, /*isDef*/ false));
262 
263   auto VD1SD = MF->CreateMachineInstr(MCID, DebugLoc());
264   VD1SD->addOperand(*MF,
265                     MachineOperand::CreateReg(VirtualDef1, /*isDef*/ true));
266   VD1SD->addOperand(*MF,
267                     MachineOperand::CreateReg(SentinelReg, /*isDef*/ true));
268 
269   auto VD2PU = MF->CreateMachineInstr(MCID, DebugLoc());
270   VD2PU->addOperand(*MF,
271                     MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
272   VD2PU->addOperand(*MF,
273                     MachineOperand::CreateReg(PhysicalReg, /*isDef*/ false));
274 
275   auto VD2PD = MF->CreateMachineInstr(MCID, DebugLoc());
276   VD2PD->addOperand(*MF,
277                     MachineOperand::CreateReg(VirtualDef2, /*isDef*/ true));
278   VD2PD->addOperand(*MF,
279                     MachineOperand::CreateReg(PhysicalReg, /*isDef*/ true));
280 
281   checkHashAndIsEqualMatch(VD1VU, VD2VU);
282   checkHashAndIsEqualMatch(VD1VU, VD1SU);
283   checkHashAndIsEqualMatch(VD1VU, VD1SD);
284   checkHashAndIsEqualMatch(VD1VU, VD2PU);
285   checkHashAndIsEqualMatch(VD1VU, VD2PD);
286 
287   checkHashAndIsEqualMatch(VD2VU, VD1SU);
288   checkHashAndIsEqualMatch(VD2VU, VD1SD);
289   checkHashAndIsEqualMatch(VD2VU, VD2PU);
290   checkHashAndIsEqualMatch(VD2VU, VD2PD);
291 
292   checkHashAndIsEqualMatch(VD1SU, VD1SD);
293   checkHashAndIsEqualMatch(VD1SU, VD2PU);
294   checkHashAndIsEqualMatch(VD1SU, VD2PD);
295 
296   checkHashAndIsEqualMatch(VD1SD, VD2PU);
297   checkHashAndIsEqualMatch(VD1SD, VD2PD);
298 
299   checkHashAndIsEqualMatch(VD2PU, VD2PD);
300 }
301 
302 TEST(MachineInstrPrintingTest, DebugLocPrinting) {
303   auto MF = createMachineFunction();
304 
305   MCOperandInfo OpInfo{0, 0, MCOI::OPERAND_REGISTER, 0};
306   MCInstrDesc MCID = {0, 1,       1,       0,       0, 0,
307                       0, nullptr, nullptr, &OpInfo, 0, nullptr};
308 
309   LLVMContext Ctx;
310   DIFile *DIF = DIFile::getDistinct(Ctx, "filename", "");
311   DISubprogram *DIS = DISubprogram::getDistinct(
312       Ctx, nullptr, "", "", DIF, 0, nullptr, 0, nullptr, 0, 0, DINode::FlagZero,
313       DISubprogram::SPFlagZero, nullptr);
314   DILocation *DIL = DILocation::get(Ctx, 1, 5, DIS);
315   DebugLoc DL(DIL);
316   MachineInstr *MI = MF->CreateMachineInstr(MCID, DL);
317   MI->addOperand(*MF, MachineOperand::CreateReg(0, /*isDef*/ true));
318 
319   std::string str;
320   raw_string_ostream OS(str);
321   MI->print(OS, /*IsStandalone*/true, /*SkipOpers*/false, /*SkipDebugLoc*/false,
322             /*AddNewLine*/false);
323   ASSERT_TRUE(
324       StringRef(OS.str()).startswith("$noreg = UNKNOWN debug-location "));
325   ASSERT_TRUE(
326       StringRef(OS.str()).endswith("filename:1:5"));
327 }
328 
329 TEST(MachineInstrSpan, DistanceBegin) {
330   auto MF = createMachineFunction();
331   auto MBB = MF->CreateMachineBasicBlock();
332 
333   MCInstrDesc MCID = {0, 0,       0,       0,       0, 0,
334                       0, nullptr, nullptr, nullptr, 0, nullptr};
335 
336   auto MII = MBB->begin();
337   MachineInstrSpan MIS(MII, MBB);
338   ASSERT_TRUE(MIS.empty());
339 
340   auto MI = MF->CreateMachineInstr(MCID, DebugLoc());
341   MBB->insert(MII, MI);
342   ASSERT_TRUE(std::distance(MIS.begin(), MII) == 1);
343 }
344 
345 TEST(MachineInstrSpan, DistanceEnd) {
346   auto MF = createMachineFunction();
347   auto MBB = MF->CreateMachineBasicBlock();
348 
349   MCInstrDesc MCID = {0, 0,       0,       0,       0, 0,
350                       0, nullptr, nullptr, nullptr, 0, nullptr};
351 
352   auto MII = MBB->end();
353   MachineInstrSpan MIS(MII, MBB);
354   ASSERT_TRUE(MIS.empty());
355 
356   auto MI = MF->CreateMachineInstr(MCID, DebugLoc());
357   MBB->insert(MII, MI);
358   ASSERT_TRUE(std::distance(MIS.begin(), MII) == 1);
359 }
360 
361 static_assert(is_trivially_copyable<MCOperand>::value, "trivially copyable");
362 
363 } // end namespace
364