1 //===------------- llvm/unittest/CodeGen/InstrRefLDVTest.cpp --------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "llvm/CodeGen/MIRParser/MIRParser.h" 10 #include "llvm/CodeGen/MachineDominators.h" 11 #include "llvm/CodeGen/MachineModuleInfo.h" 12 #include "llvm/CodeGen/TargetFrameLowering.h" 13 #include "llvm/CodeGen/TargetInstrInfo.h" 14 #include "llvm/CodeGen/TargetLowering.h" 15 #include "llvm/CodeGen/TargetRegisterInfo.h" 16 #include "llvm/CodeGen/TargetSubtargetInfo.h" 17 #include "llvm/IR/DIBuilder.h" 18 #include "llvm/IR/DebugInfoMetadata.h" 19 #include "llvm/IR/IRBuilder.h" 20 #include "llvm/MC/TargetRegistry.h" 21 #include "llvm/Support/MemoryBuffer.h" 22 #include "llvm/Support/TargetSelect.h" 23 #include "llvm/Target/TargetMachine.h" 24 #include "llvm/Target/TargetOptions.h" 25 26 #include "../lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.h" 27 28 #include "gtest/gtest.h" 29 30 using namespace llvm; 31 using namespace LiveDebugValues; 32 33 // Include helper functions to ease the manipulation of MachineFunctions 34 #include "MFCommon.inc" 35 36 class InstrRefLDVTest : public testing::Test { 37 public: 38 friend class InstrRefBasedLDV; 39 using MLocTransferMap = InstrRefBasedLDV::MLocTransferMap; 40 41 LLVMContext Ctx; 42 std::unique_ptr<Module> Mod; 43 std::unique_ptr<TargetMachine> Machine; 44 std::unique_ptr<MachineFunction> MF; 45 std::unique_ptr<MachineDominatorTree> DomTree; 46 std::unique_ptr<MachineModuleInfo> MMI; 47 DICompileUnit *OurCU; 48 DIFile *OurFile; 49 DISubprogram *OurFunc; 50 DILexicalBlock *OurBlock, *AnotherBlock; 51 DISubprogram *ToInlineFunc; 52 DILexicalBlock *ToInlineBlock; 53 DILocalVariable *FuncVariable; 54 DIBasicType *LongInt; 55 DIExpression *EmptyExpr; 56 LiveDebugValues::OverlapMap Overlaps; 57 58 DebugLoc OutermostLoc, InBlockLoc, NotNestedBlockLoc, InlinedLoc; 59 60 MachineBasicBlock *MBB0, *MBB1, *MBB2, *MBB3, *MBB4; 61 62 std::unique_ptr<InstrRefBasedLDV> LDV; 63 std::unique_ptr<MLocTracker> MTracker; 64 std::unique_ptr<VLocTracker> VTracker; 65 66 SmallString<256> MIRStr; 67 68 InstrRefLDVTest() : Ctx(), Mod(std::make_unique<Module>("beehives", Ctx)) {} 69 70 void SetUp() { 71 // Boilerplate that creates a MachineFunction and associated blocks. 72 73 Mod->setDataLayout("e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-" 74 "n8:16:32:64-S128"); 75 Triple TargetTriple("x86_64--"); 76 std::string Error; 77 const Target *T = TargetRegistry::lookupTarget("", TargetTriple, Error); 78 if (!T) 79 GTEST_SKIP(); 80 81 TargetOptions Options; 82 Machine = std::unique_ptr<TargetMachine>( 83 T->createTargetMachine(Triple::normalize("x86_64--"), "", "", Options, 84 None, None, CodeGenOpt::Aggressive)); 85 86 auto Type = FunctionType::get(Type::getVoidTy(Ctx), false); 87 auto F = 88 Function::Create(Type, GlobalValue::ExternalLinkage, "Test", &*Mod); 89 90 unsigned FunctionNum = 42; 91 MMI = std::make_unique<MachineModuleInfo>((LLVMTargetMachine *)&*Machine); 92 const TargetSubtargetInfo &STI = *Machine->getSubtargetImpl(*F); 93 94 MF = std::make_unique<MachineFunction>(*F, (LLVMTargetMachine &)*Machine, 95 STI, FunctionNum, *MMI); 96 97 // Create metadata: CU, subprogram, some blocks and an inline function 98 // scope. 99 DIBuilder DIB(*Mod); 100 OurFile = DIB.createFile("xyzzy.c", "/cave"); 101 OurCU = 102 DIB.createCompileUnit(dwarf::DW_LANG_C99, OurFile, "nou", false, "", 0); 103 auto OurSubT = DIB.createSubroutineType(DIB.getOrCreateTypeArray(None)); 104 OurFunc = 105 DIB.createFunction(OurCU, "bees", "", OurFile, 1, OurSubT, 1, 106 DINode::FlagZero, DISubprogram::SPFlagDefinition); 107 F->setSubprogram(OurFunc); 108 OurBlock = DIB.createLexicalBlock(OurFunc, OurFile, 2, 3); 109 AnotherBlock = DIB.createLexicalBlock(OurFunc, OurFile, 2, 6); 110 ToInlineFunc = 111 DIB.createFunction(OurFile, "shoes", "", OurFile, 10, OurSubT, 10, 112 DINode::FlagZero, DISubprogram::SPFlagDefinition); 113 114 // Make some nested scopes. 115 OutermostLoc = DILocation::get(Ctx, 3, 1, OurFunc); 116 InBlockLoc = DILocation::get(Ctx, 4, 1, OurBlock); 117 InlinedLoc = DILocation::get(Ctx, 10, 1, ToInlineFunc, InBlockLoc.get()); 118 119 // Make a scope that isn't nested within the others. 120 NotNestedBlockLoc = DILocation::get(Ctx, 4, 1, AnotherBlock); 121 122 LongInt = DIB.createBasicType("long", 64, llvm::dwarf::DW_ATE_unsigned); 123 FuncVariable = DIB.createAutoVariable(OurFunc, "lala", OurFile, 1, LongInt); 124 EmptyExpr = DIExpression::get(Ctx, {}); 125 126 DIB.finalize(); 127 } 128 129 Register getRegByName(const char *WantedName) { 130 auto *TRI = MF->getRegInfo().getTargetRegisterInfo(); 131 // Slow, but works. 132 for (unsigned int I = 1; I < TRI->getNumRegs(); ++I) { 133 const char *Name = TRI->getName(I); 134 if (strcmp(WantedName, Name) == 0) 135 return I; 136 } 137 138 // If this ever fails, something is very wrong with this unit test. 139 llvm_unreachable("Can't find register by name"); 140 } 141 142 InstrRefBasedLDV *setupLDVObj(MachineFunction *MF) { 143 // Create a new LDV object, and plug some relevant object ptrs into it. 144 LDV = std::make_unique<InstrRefBasedLDV>(); 145 const TargetSubtargetInfo &STI = MF->getSubtarget(); 146 LDV->TII = STI.getInstrInfo(); 147 LDV->TRI = STI.getRegisterInfo(); 148 LDV->TFI = STI.getFrameLowering(); 149 LDV->MFI = &MF->getFrameInfo(); 150 LDV->MRI = &MF->getRegInfo(); 151 152 DomTree = std::make_unique<MachineDominatorTree>(*MF); 153 LDV->DomTree = &*DomTree; 154 155 // Future work: unit tests for mtracker / vtracker / ttracker. 156 157 // Setup things like the artifical block map, and BlockNo <=> RPO Order 158 // mappings. 159 LDV->initialSetup(*MF); 160 LDV->LS.initialize(*MF); 161 addMTracker(MF); 162 return &*LDV; 163 } 164 165 void addMTracker(MachineFunction *MF) { 166 ASSERT_TRUE(LDV); 167 // Add a machine-location-tracking object to LDV. Don't initialize any 168 // register locations within it though. 169 const TargetSubtargetInfo &STI = MF->getSubtarget(); 170 MTracker = std::make_unique<MLocTracker>( 171 *MF, *LDV->TII, *LDV->TRI, *STI.getTargetLowering()); 172 LDV->MTracker = &*MTracker; 173 } 174 175 void addVTracker() { 176 ASSERT_TRUE(LDV); 177 VTracker = std::make_unique<VLocTracker>(Overlaps, EmptyExpr); 178 LDV->VTracker = &*VTracker; 179 } 180 181 // Some routines for bouncing into LDV, 182 void buildMLocValueMap(FuncValueTable &MInLocs, FuncValueTable &MOutLocs, 183 SmallVectorImpl<MLocTransferMap> &MLocTransfer) { 184 LDV->buildMLocValueMap(*MF, MInLocs, MOutLocs, MLocTransfer); 185 } 186 187 void placeMLocPHIs(MachineFunction &MF, 188 SmallPtrSetImpl<MachineBasicBlock *> &AllBlocks, 189 FuncValueTable &MInLocs, 190 SmallVectorImpl<MLocTransferMap> &MLocTransfer) { 191 LDV->placeMLocPHIs(MF, AllBlocks, MInLocs, MLocTransfer); 192 } 193 194 Optional<ValueIDNum> 195 pickVPHILoc(const MachineBasicBlock &MBB, const DebugVariable &Var, 196 const InstrRefBasedLDV::LiveIdxT &LiveOuts, FuncValueTable &MOutLocs, 197 const SmallVectorImpl<const MachineBasicBlock *> &BlockOrders) { 198 return LDV->pickVPHILoc(MBB, Var, LiveOuts, MOutLocs, BlockOrders); 199 } 200 201 bool vlocJoin(MachineBasicBlock &MBB, InstrRefBasedLDV::LiveIdxT &VLOCOutLocs, 202 SmallPtrSet<const MachineBasicBlock *, 8> &BlocksToExplore, 203 DbgValue &InLoc) { 204 return LDV->vlocJoin(MBB, VLOCOutLocs, BlocksToExplore, InLoc); 205 } 206 207 void buildVLocValueMap(const DILocation *DILoc, 208 const SmallSet<DebugVariable, 4> &VarsWeCareAbout, 209 SmallPtrSetImpl<MachineBasicBlock *> &AssignBlocks, 210 InstrRefBasedLDV::LiveInsT &Output, FuncValueTable &MOutLocs, 211 FuncValueTable &MInLocs, 212 SmallVectorImpl<VLocTracker> &AllTheVLocs) { 213 LDV->buildVLocValueMap(DILoc, VarsWeCareAbout, AssignBlocks, Output, 214 MOutLocs, MInLocs, AllTheVLocs); 215 } 216 217 void initValueArray(FuncValueTable &Nums, unsigned Blks, unsigned Locs) { 218 for (unsigned int I = 0; I < Blks; ++I) 219 for (unsigned int J = 0; J < Locs; ++J) 220 Nums[I][J] = ValueIDNum::EmptyValue; 221 } 222 223 void setupSingleBlock() { 224 // Add an entry block with nothing but 'ret void' in it. 225 Function &F = const_cast<llvm::Function &>(MF->getFunction()); 226 auto *BB0 = BasicBlock::Create(Ctx, "entry", &F); 227 IRBuilder<> IRB(BB0); 228 IRB.CreateRetVoid(); 229 MBB0 = MF->CreateMachineBasicBlock(BB0); 230 MF->insert(MF->end(), MBB0); 231 MF->RenumberBlocks(); 232 233 setupLDVObj(&*MF); 234 } 235 236 void setupDiamondBlocks() { 237 // entry 238 // / \ 239 // br1 br2 240 // \ / 241 // ret 242 llvm::Function &F = const_cast<llvm::Function &>(MF->getFunction()); 243 auto *BB0 = BasicBlock::Create(Ctx, "a", &F); 244 auto *BB1 = BasicBlock::Create(Ctx, "b", &F); 245 auto *BB2 = BasicBlock::Create(Ctx, "c", &F); 246 auto *BB3 = BasicBlock::Create(Ctx, "d", &F); 247 IRBuilder<> IRB0(BB0), IRB1(BB1), IRB2(BB2), IRB3(BB3); 248 IRB0.CreateBr(BB1); 249 IRB1.CreateBr(BB2); 250 IRB2.CreateBr(BB3); 251 IRB3.CreateRetVoid(); 252 MBB0 = MF->CreateMachineBasicBlock(BB0); 253 MF->insert(MF->end(), MBB0); 254 MBB1 = MF->CreateMachineBasicBlock(BB1); 255 MF->insert(MF->end(), MBB1); 256 MBB2 = MF->CreateMachineBasicBlock(BB2); 257 MF->insert(MF->end(), MBB2); 258 MBB3 = MF->CreateMachineBasicBlock(BB3); 259 MF->insert(MF->end(), MBB3); 260 MBB0->addSuccessor(MBB1); 261 MBB0->addSuccessor(MBB2); 262 MBB1->addSuccessor(MBB3); 263 MBB2->addSuccessor(MBB3); 264 MF->RenumberBlocks(); 265 266 setupLDVObj(&*MF); 267 } 268 269 void setupSimpleLoop() { 270 // entry 271 // | 272 // |/-----\ 273 // loopblk | 274 // |\-----/ 275 // | 276 // ret 277 llvm::Function &F = const_cast<llvm::Function &>(MF->getFunction()); 278 auto *BB0 = BasicBlock::Create(Ctx, "entry", &F); 279 auto *BB1 = BasicBlock::Create(Ctx, "loop", &F); 280 auto *BB2 = BasicBlock::Create(Ctx, "ret", &F); 281 IRBuilder<> IRB0(BB0), IRB1(BB1), IRB2(BB2); 282 IRB0.CreateBr(BB1); 283 IRB1.CreateBr(BB2); 284 IRB2.CreateRetVoid(); 285 MBB0 = MF->CreateMachineBasicBlock(BB0); 286 MF->insert(MF->end(), MBB0); 287 MBB1 = MF->CreateMachineBasicBlock(BB1); 288 MF->insert(MF->end(), MBB1); 289 MBB2 = MF->CreateMachineBasicBlock(BB2); 290 MF->insert(MF->end(), MBB2); 291 MBB0->addSuccessor(MBB1); 292 MBB1->addSuccessor(MBB2); 293 MBB1->addSuccessor(MBB1); 294 MF->RenumberBlocks(); 295 296 setupLDVObj(&*MF); 297 } 298 299 void setupNestedLoops() { 300 // entry 301 // | 302 // loop1 303 // ^\ 304 // | \ /-\ 305 // | loop2 | 306 // | / \-/ 307 // ^ / 308 // join 309 // | 310 // ret 311 llvm::Function &F = const_cast<llvm::Function &>(MF->getFunction()); 312 auto *BB0 = BasicBlock::Create(Ctx, "entry", &F); 313 auto *BB1 = BasicBlock::Create(Ctx, "loop1", &F); 314 auto *BB2 = BasicBlock::Create(Ctx, "loop2", &F); 315 auto *BB3 = BasicBlock::Create(Ctx, "join", &F); 316 auto *BB4 = BasicBlock::Create(Ctx, "ret", &F); 317 IRBuilder<> IRB0(BB0), IRB1(BB1), IRB2(BB2), IRB3(BB3), IRB4(BB4); 318 IRB0.CreateBr(BB1); 319 IRB1.CreateBr(BB2); 320 IRB2.CreateBr(BB3); 321 IRB3.CreateBr(BB4); 322 IRB4.CreateRetVoid(); 323 MBB0 = MF->CreateMachineBasicBlock(BB0); 324 MF->insert(MF->end(), MBB0); 325 MBB1 = MF->CreateMachineBasicBlock(BB1); 326 MF->insert(MF->end(), MBB1); 327 MBB2 = MF->CreateMachineBasicBlock(BB2); 328 MF->insert(MF->end(), MBB2); 329 MBB3 = MF->CreateMachineBasicBlock(BB3); 330 MF->insert(MF->end(), MBB3); 331 MBB4 = MF->CreateMachineBasicBlock(BB4); 332 MF->insert(MF->end(), MBB4); 333 MBB0->addSuccessor(MBB1); 334 MBB1->addSuccessor(MBB2); 335 MBB2->addSuccessor(MBB2); 336 MBB2->addSuccessor(MBB3); 337 MBB3->addSuccessor(MBB1); 338 MBB3->addSuccessor(MBB4); 339 MF->RenumberBlocks(); 340 341 setupLDVObj(&*MF); 342 } 343 344 void setupNoDominatingLoop() { 345 // entry 346 // / \ 347 // / \ 348 // / \ 349 // head1 head2 350 // ^ \ / ^ 351 // ^ \ / ^ 352 // \-joinblk -/ 353 // | 354 // ret 355 llvm::Function &F = const_cast<llvm::Function &>(MF->getFunction()); 356 auto *BB0 = BasicBlock::Create(Ctx, "entry", &F); 357 auto *BB1 = BasicBlock::Create(Ctx, "head1", &F); 358 auto *BB2 = BasicBlock::Create(Ctx, "head2", &F); 359 auto *BB3 = BasicBlock::Create(Ctx, "joinblk", &F); 360 auto *BB4 = BasicBlock::Create(Ctx, "ret", &F); 361 IRBuilder<> IRB0(BB0), IRB1(BB1), IRB2(BB2), IRB3(BB3), IRB4(BB4); 362 IRB0.CreateBr(BB1); 363 IRB1.CreateBr(BB2); 364 IRB2.CreateBr(BB3); 365 IRB3.CreateBr(BB4); 366 IRB4.CreateRetVoid(); 367 MBB0 = MF->CreateMachineBasicBlock(BB0); 368 MF->insert(MF->end(), MBB0); 369 MBB1 = MF->CreateMachineBasicBlock(BB1); 370 MF->insert(MF->end(), MBB1); 371 MBB2 = MF->CreateMachineBasicBlock(BB2); 372 MF->insert(MF->end(), MBB2); 373 MBB3 = MF->CreateMachineBasicBlock(BB3); 374 MF->insert(MF->end(), MBB3); 375 MBB4 = MF->CreateMachineBasicBlock(BB4); 376 MF->insert(MF->end(), MBB4); 377 MBB0->addSuccessor(MBB1); 378 MBB0->addSuccessor(MBB2); 379 MBB1->addSuccessor(MBB3); 380 MBB2->addSuccessor(MBB3); 381 MBB3->addSuccessor(MBB1); 382 MBB3->addSuccessor(MBB2); 383 MBB3->addSuccessor(MBB4); 384 MF->RenumberBlocks(); 385 386 setupLDVObj(&*MF); 387 } 388 389 void setupBadlyNestedLoops() { 390 // entry 391 // | 392 // loop1 -o 393 // | ^ 394 // | ^ 395 // loop2 -o 396 // | ^ 397 // | ^ 398 // loop3 -o 399 // | 400 // ret 401 // 402 // NB: the loop blocks self-loop, which is a bit too fiddly to draw on 403 // accurately. 404 llvm::Function &F = const_cast<llvm::Function &>(MF->getFunction()); 405 auto *BB0 = BasicBlock::Create(Ctx, "entry", &F); 406 auto *BB1 = BasicBlock::Create(Ctx, "loop1", &F); 407 auto *BB2 = BasicBlock::Create(Ctx, "loop2", &F); 408 auto *BB3 = BasicBlock::Create(Ctx, "loop3", &F); 409 auto *BB4 = BasicBlock::Create(Ctx, "ret", &F); 410 IRBuilder<> IRB0(BB0), IRB1(BB1), IRB2(BB2), IRB3(BB3), IRB4(BB4); 411 IRB0.CreateBr(BB1); 412 IRB1.CreateBr(BB2); 413 IRB2.CreateBr(BB3); 414 IRB3.CreateBr(BB4); 415 IRB4.CreateRetVoid(); 416 MBB0 = MF->CreateMachineBasicBlock(BB0); 417 MF->insert(MF->end(), MBB0); 418 MBB1 = MF->CreateMachineBasicBlock(BB1); 419 MF->insert(MF->end(), MBB1); 420 MBB2 = MF->CreateMachineBasicBlock(BB2); 421 MF->insert(MF->end(), MBB2); 422 MBB3 = MF->CreateMachineBasicBlock(BB3); 423 MF->insert(MF->end(), MBB3); 424 MBB4 = MF->CreateMachineBasicBlock(BB4); 425 MF->insert(MF->end(), MBB4); 426 MBB0->addSuccessor(MBB1); 427 MBB1->addSuccessor(MBB1); 428 MBB1->addSuccessor(MBB2); 429 MBB2->addSuccessor(MBB1); 430 MBB2->addSuccessor(MBB2); 431 MBB2->addSuccessor(MBB3); 432 MBB3->addSuccessor(MBB2); 433 MBB3->addSuccessor(MBB3); 434 MBB3->addSuccessor(MBB4); 435 MF->RenumberBlocks(); 436 437 setupLDVObj(&*MF); 438 } 439 440 MachineFunction *readMIRBlock(const char *Input) { 441 MIRStr.clear(); 442 StringRef S = Twine(Twine(R"MIR( 443 --- | 444 target triple = "x86_64-unknown-linux-gnu" 445 define void @test() { ret void } 446 ... 447 --- 448 name: test 449 tracksRegLiveness: true 450 stack: 451 - { id: 0, name: '', type: spill-slot, offset: -16, size: 8, alignment: 8, 452 stack-id: default, callee-saved-register: '', callee-saved-restored: true, 453 debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } 454 body: | 455 bb.0: 456 liveins: $rdi, $rsi 457 )MIR") + Twine(Input) + Twine("...\n")) 458 .toNullTerminatedStringRef(MIRStr); 459 ; 460 461 // Clear the "test" function from MMI if it's still present. 462 if (Function *Fn = Mod->getFunction("test")) 463 MMI->deleteMachineFunctionFor(*Fn); 464 465 auto MemBuf = MemoryBuffer::getMemBuffer(S, "<input>"); 466 auto MIRParse = createMIRParser(std::move(MemBuf), Ctx); 467 Mod = MIRParse->parseIRModule(); 468 assert(Mod); 469 Mod->setDataLayout("e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-" 470 "n8:16:32:64-S128"); 471 472 bool Result = MIRParse->parseMachineFunctions(*Mod, *MMI); 473 assert(!Result && "Failed to parse unit test machine function?"); 474 (void)Result; 475 476 Function *Fn = Mod->getFunction("test"); 477 assert(Fn && "Failed to parse a unit test module string?"); 478 Fn->setSubprogram(OurFunc); 479 return MMI->getMachineFunction(*Fn); 480 } 481 482 void 483 produceMLocTransferFunction(MachineFunction &MF, 484 SmallVectorImpl<MLocTransferMap> &MLocTransfer, 485 unsigned MaxNumBlocks) { 486 LDV->produceMLocTransferFunction(MF, MLocTransfer, MaxNumBlocks); 487 } 488 489 std::pair<FuncValueTable, FuncValueTable> 490 allocValueTables(unsigned Blocks, unsigned Locs) { 491 FuncValueTable MOutLocs = std::make_unique<ValueTable[]>(Blocks); 492 FuncValueTable MInLocs = std::make_unique<ValueTable[]>(Blocks); 493 494 for (unsigned int I = 0; I < Blocks; ++I) { 495 MOutLocs[I] = std::make_unique<ValueIDNum[]>(Locs); 496 MInLocs[I] = std::make_unique<ValueIDNum[]>(Locs); 497 } 498 499 return std::make_pair(std::move(MOutLocs), std::move(MInLocs)); 500 } 501 }; 502 503 TEST_F(InstrRefLDVTest, MTransferDefs) { 504 MachineFunction *MF = readMIRBlock( 505 " $rax = MOV64ri 0\n" 506 " RET64 $rax\n"); 507 setupLDVObj(MF); 508 509 // We should start with only SP tracked. 510 EXPECT_TRUE(MTracker->getNumLocs() == 1); 511 512 SmallVector<MLocTransferMap, 1> TransferMap; 513 TransferMap.resize(1); 514 produceMLocTransferFunction(*MF, TransferMap, 1); 515 516 // Code contains only one register write: that should assign to each of the 517 // aliasing registers. Test that all of them get locations, and have a 518 // corresponding def at the first instr in the function. 519 const char *RegNames[] = {"RAX", "HAX", "EAX", "AX", "AH", "AL"}; 520 EXPECT_TRUE(MTracker->getNumLocs() == 7); 521 for (const char *RegName : RegNames) { 522 Register R = getRegByName(RegName); 523 ASSERT_TRUE(MTracker->isRegisterTracked(R)); 524 LocIdx L = MTracker->getRegMLoc(R); 525 ValueIDNum V = MTracker->readReg(R); 526 // Value of this register should be: block zero, instruction 1, and the 527 // location it's defined in is itself. 528 ValueIDNum ToCmp(0, 1, L); 529 EXPECT_EQ(V, ToCmp); 530 } 531 532 // Do the same again, but with an aliasing write. This should write to all 533 // the same registers again, except $ah and $hax (the upper 8 bits of $ax 534 // and 32 bits of $rax resp.). 535 MF = readMIRBlock( 536 " $rax = MOV64ri 0\n" 537 " $al = MOV8ri 0\n" 538 " RET64 $rax\n"); 539 setupLDVObj(MF); 540 TransferMap.clear(); 541 TransferMap.resize(1); 542 produceMLocTransferFunction(*MF, TransferMap, 1); 543 544 auto TestRegSetSite = [&](const char *Name, unsigned InstrNum) { 545 Register R = getRegByName(Name); 546 ASSERT_TRUE(MTracker->isRegisterTracked(R)); 547 LocIdx L = MTracker->getRegMLoc(R); 548 ValueIDNum V = MTracker->readMLoc(L); 549 ValueIDNum ToCmp(0, InstrNum, L); 550 EXPECT_EQ(V, ToCmp); 551 }; 552 553 TestRegSetSite("AL", 2); 554 TestRegSetSite("AH", 1); 555 TestRegSetSite("AX", 2); 556 TestRegSetSite("EAX", 2); 557 TestRegSetSite("HAX", 1); 558 TestRegSetSite("RAX", 2); 559 560 // This call should: 561 // * Def rax via the implicit-def, 562 // * Clobber rsi/rdi and all their subregs, via the register mask 563 // * Same for rcx, despite it not being a use in the instr, it's in the mask 564 // * NOT clobber $rsp / $esp $ sp, LiveDebugValues deliberately ignores 565 // these. 566 // * NOT clobber $rbx, because it's non-volatile 567 // * Not track every other register in the machine, only those needed. 568 MF = readMIRBlock( 569 " $rax = MOV64ri 0\n" // instr 1 570 " $rbx = MOV64ri 0\n" // instr 2 571 " $rcx = MOV64ri 0\n" // instr 3 572 " $rdi = MOV64ri 0\n" // instr 4 573 " $rsi = MOV64ri 0\n" // instr 5 574 " CALL64r $rax, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, implicit $rsi, implicit-def $rsp, implicit-def $ssp, implicit-def $rax, implicit-def $esp, implicit-def $sp\n\n\n\n" // instr 6 575 " RET64 $rax\n"); // instr 7 576 setupLDVObj(MF); 577 TransferMap.clear(); 578 TransferMap.resize(1); 579 produceMLocTransferFunction(*MF, TransferMap, 1); 580 581 const char *RegsSetInCall[] = {"AL", "AH", "AX", "EAX", "HAX", "RAX", 582 "DIL", "DIH", "DI", "EDI", "HDI", "RDI", 583 "SIL", "SIH", "SI", "ESI", "HSI", "RSI", 584 "CL", "CH", "CX", "ECX", "HCX", "RCX"}; 585 for (const char *RegSetInCall : RegsSetInCall) 586 TestRegSetSite(RegSetInCall, 6); 587 588 const char *RegsLeftAlone[] = {"BL", "BH", "BX", "EBX", "HBX", "RBX"}; 589 for (const char *RegLeftAlone : RegsLeftAlone) 590 TestRegSetSite(RegLeftAlone, 2); 591 592 // Stack pointer should be the live-in to the function, instruction zero. 593 TestRegSetSite("RSP", 0); 594 // These stack regs should not be tracked either. Nor the (fake) subregs. 595 EXPECT_FALSE(MTracker->isRegisterTracked(getRegByName("ESP"))); 596 EXPECT_FALSE(MTracker->isRegisterTracked(getRegByName("SP"))); 597 EXPECT_FALSE(MTracker->isRegisterTracked(getRegByName("SPL"))); 598 EXPECT_FALSE(MTracker->isRegisterTracked(getRegByName("SPH"))); 599 EXPECT_FALSE(MTracker->isRegisterTracked(getRegByName("HSP"))); 600 601 // Should only be tracking: 6 x {A, B, C, DI, SI} registers = 30, 602 // Plus RSP, SSP = 32. 603 EXPECT_EQ(32u, MTracker->getNumLocs()); 604 605 606 // When we DBG_PHI something, we should track all its subregs. 607 MF = readMIRBlock( 608 " DBG_PHI $rdi, 0\n" 609 " RET64\n"); 610 setupLDVObj(MF); 611 TransferMap.clear(); 612 TransferMap.resize(1); 613 produceMLocTransferFunction(*MF, TransferMap, 1); 614 615 // All DI regs and RSP tracked. 616 EXPECT_EQ(7u, MTracker->getNumLocs()); 617 618 // All the DI registers should have block live-in values, i.e. the argument 619 // to the function. 620 const char *DIRegs[] = {"DIL", "DIH", "DI", "EDI", "HDI", "RDI"}; 621 for (const char *DIReg : DIRegs) 622 TestRegSetSite(DIReg, 0); 623 } 624 625 TEST_F(InstrRefLDVTest, MTransferMeta) { 626 // Meta instructions should not have any effect on register values. 627 SmallVector<MLocTransferMap, 1> TransferMap; 628 MachineFunction *MF = readMIRBlock( 629 " $rax = MOV64ri 0\n" 630 " $rax = IMPLICIT_DEF\n" 631 " $rax = KILL killed $rax\n" 632 " RET64 $rax\n"); 633 setupLDVObj(MF); 634 TransferMap.clear(); 635 TransferMap.resize(1); 636 produceMLocTransferFunction(*MF, TransferMap, 1); 637 638 LocIdx RaxLoc = MTracker->getRegMLoc(getRegByName("RAX")); 639 ValueIDNum V = MTracker->readMLoc(RaxLoc); 640 // Def of rax should be from instruction 1, i.e., unmodified. 641 ValueIDNum Cmp(0, 1, RaxLoc); 642 EXPECT_EQ(Cmp, V); 643 } 644 645 TEST_F(InstrRefLDVTest, MTransferCopies) { 646 SmallVector<MLocTransferMap, 1> TransferMap; 647 // This memory spill should be recognised, and a spill slot created. 648 MachineFunction *MF = readMIRBlock( 649 " $rax = MOV64ri 0\n" 650 " MOV64mr $rsp, 1, $noreg, 16, $noreg, $rax :: (store 8 into %stack.0)\n" 651 " RET64 $rax\n"); 652 setupLDVObj(MF); 653 TransferMap.clear(); 654 TransferMap.resize(1); 655 produceMLocTransferFunction(*MF, TransferMap, 1); 656 657 // Check that the spill location contains the value defined in rax by 658 // instruction 1. The MIR header says -16 offset, but it's stored as -8; 659 // it's not completely clear why, but here we only care about correctly 660 // identifying the slot, not that all the surrounding data is correct. 661 SpillLoc L = {getRegByName("RSP"), StackOffset::getFixed(-8)}; 662 SpillLocationNo SpillNo = *MTracker->getOrTrackSpillLoc(L); 663 unsigned SpillLocID = MTracker->getLocID(SpillNo, {64, 0}); 664 LocIdx SpillLoc = MTracker->getSpillMLoc(SpillLocID); 665 ValueIDNum V = MTracker->readMLoc(SpillLoc); 666 Register RAX = getRegByName("RAX"); 667 LocIdx RaxLoc = MTracker->getRegMLoc(RAX); 668 ValueIDNum Cmp(0, 1, RaxLoc); 669 EXPECT_EQ(V, Cmp); 670 671 // A spill and restore should be recognised. 672 MF = readMIRBlock( 673 " $rax = MOV64ri 0\n" 674 " MOV64mr $rsp, 1, $noreg, 16, $noreg, $rax :: (store 8 into %stack.0)\n" 675 " $rbx = MOV64rm $rsp, 1, $noreg, 0, $noreg :: (load 8 from %stack.0)\n" 676 " RET64\n"); 677 setupLDVObj(MF); 678 TransferMap.clear(); 679 TransferMap.resize(1); 680 produceMLocTransferFunction(*MF, TransferMap, 1); 681 682 // Test that rbx contains rax from instruction 1. 683 RAX = getRegByName("RAX"); 684 RaxLoc = MTracker->getRegMLoc(RAX); 685 Register RBX = getRegByName("RBX"); 686 LocIdx RbxLoc = MTracker->getRegMLoc(RBX); 687 Cmp = ValueIDNum(0, 1, RaxLoc); 688 ValueIDNum RbxVal = MTracker->readMLoc(RbxLoc); 689 EXPECT_EQ(RbxVal, Cmp); 690 691 // Testing that all the subregisters are transferred happens in 692 // MTransferSubregSpills. 693 694 // Copies and x86 movs should be recognised and honoured. In addition, all 695 // of the subregisters should be copied across too. 696 MF = readMIRBlock( 697 " $rax = MOV64ri 0\n" 698 " $rcx = COPY $rax\n" 699 " $rbx = MOV64rr $rcx\n" 700 " RET64\n"); 701 setupLDVObj(MF); 702 TransferMap.clear(); 703 TransferMap.resize(1); 704 produceMLocTransferFunction(*MF, TransferMap, 1); 705 706 const char *ARegs[] = {"AL", "AH", "AX", "EAX", "HAX", "RAX"}; 707 const char *BRegs[] = {"BL", "BH", "BX", "EBX", "HBX", "RBX"}; 708 const char *CRegs[] = {"CL", "CH", "CX", "ECX", "HCX", "RCX"}; 709 auto CheckReg = [&](unsigned int I) { 710 LocIdx A = MTracker->getRegMLoc(getRegByName(ARegs[I])); 711 LocIdx B = MTracker->getRegMLoc(getRegByName(BRegs[I])); 712 LocIdx C = MTracker->getRegMLoc(getRegByName(CRegs[I])); 713 ValueIDNum ARefVal(0, 1, A); 714 ValueIDNum AVal = MTracker->readMLoc(A); 715 ValueIDNum BVal = MTracker->readMLoc(B); 716 ValueIDNum CVal = MTracker->readMLoc(C); 717 EXPECT_EQ(ARefVal, AVal); 718 EXPECT_EQ(ARefVal, BVal); 719 EXPECT_EQ(ARefVal, CVal); 720 }; 721 722 for (unsigned int I = 0; I < 6; ++I) 723 CheckReg(I); 724 725 // When we copy to a subregister, the super-register should be def'd too: it's 726 // value will have changed. 727 MF = readMIRBlock( 728 " $rax = MOV64ri 0\n" 729 " $ecx = COPY $eax\n" 730 " RET64\n"); 731 setupLDVObj(MF); 732 TransferMap.clear(); 733 TransferMap.resize(1); 734 produceMLocTransferFunction(*MF, TransferMap, 1); 735 736 // First four regs [al, ah, ax, eax] should be copied to *cx. 737 for (unsigned int I = 0; I < 4; ++I) { 738 LocIdx A = MTracker->getRegMLoc(getRegByName(ARegs[I])); 739 LocIdx C = MTracker->getRegMLoc(getRegByName(CRegs[I])); 740 ValueIDNum ARefVal(0, 1, A); 741 ValueIDNum AVal = MTracker->readMLoc(A); 742 ValueIDNum CVal = MTracker->readMLoc(C); 743 EXPECT_EQ(ARefVal, AVal); 744 EXPECT_EQ(ARefVal, CVal); 745 } 746 747 // But rcx should contain a value defined by the COPY. 748 LocIdx RcxLoc = MTracker->getRegMLoc(getRegByName("RCX")); 749 ValueIDNum RcxVal = MTracker->readMLoc(RcxLoc); 750 ValueIDNum RcxDefVal(0, 2, RcxLoc); // instr 2 -> the copy 751 EXPECT_EQ(RcxVal, RcxDefVal); 752 } 753 754 TEST_F(InstrRefLDVTest, MTransferSubregSpills) { 755 SmallVector<MLocTransferMap, 1> TransferMap; 756 MachineFunction *MF = readMIRBlock( 757 " $rax = MOV64ri 0\n" 758 " MOV64mr $rsp, 1, $noreg, 16, $noreg, $rax :: (store 8 into %stack.0)\n" 759 " $rbx = MOV64rm $rsp, 1, $noreg, 0, $noreg :: (load 8 from %stack.0)\n" 760 " RET64\n"); 761 setupLDVObj(MF); 762 TransferMap.clear(); 763 TransferMap.resize(1); 764 produceMLocTransferFunction(*MF, TransferMap, 1); 765 766 // Check that all the subregs of rax and rbx contain the same values. One 767 // should completely transfer to the other. 768 const char *ARegs[] = {"AL", "AH", "AX", "EAX", "HAX", "RAX"}; 769 const char *BRegs[] = {"BL", "BH", "BX", "EBX", "HBX", "RBX"}; 770 for (unsigned int I = 0; I < 6; ++I) { 771 LocIdx A = MTracker->getRegMLoc(getRegByName(ARegs[I])); 772 LocIdx B = MTracker->getRegMLoc(getRegByName(BRegs[I])); 773 EXPECT_EQ(MTracker->readMLoc(A), MTracker->readMLoc(B)); 774 } 775 776 // Explicitly check what's in the different subreg slots, on the stack. 777 // Pair up subreg idx fields with the corresponding subregister in $rax. 778 MLocTracker::StackSlotPos SubRegIdxes[] = {{8, 0}, {8, 8}, {16, 0}, {32, 0}, {64, 0}}; 779 const char *SubRegNames[] = {"AL", "AH", "AX", "EAX", "RAX"}; 780 for (unsigned int I = 0; I < 5; ++I) { 781 // Value number where it's defined, 782 LocIdx RegLoc = MTracker->getRegMLoc(getRegByName(SubRegNames[I])); 783 ValueIDNum DefNum(0, 1, RegLoc); 784 // Read the corresponding subreg field from the stack. 785 SpillLoc L = {getRegByName("RSP"), StackOffset::getFixed(-8)}; 786 SpillLocationNo SpillNo = *MTracker->getOrTrackSpillLoc(L); 787 unsigned SpillID = MTracker->getLocID(SpillNo, SubRegIdxes[I]); 788 LocIdx SpillLoc = MTracker->getSpillMLoc(SpillID); 789 ValueIDNum SpillValue = MTracker->readMLoc(SpillLoc); 790 EXPECT_EQ(DefNum, SpillValue); 791 } 792 793 // If we have exactly the same code, but we write $eax to the stack slot after 794 // $rax, then we should still have exactly the same output in the lower five 795 // subregisters. Storing $eax to the start of the slot will overwrite with the 796 // same values. $rax, as an aliasing register, should be reset to something 797 // else by that write. 798 // In theory, we could try and recognise that we're writing the _same_ values 799 // to the stack again, and so $rax doesn't need to be reset to something else. 800 // It seems vanishingly unlikely that LLVM would generate such code though, 801 // so the benefits would be small. 802 MF = readMIRBlock( 803 " $rax = MOV64ri 0\n" 804 " MOV64mr $rsp, 1, $noreg, 16, $noreg, $rax :: (store 8 into %stack.0)\n" 805 " MOV32mr $rsp, 1, $noreg, 16, $noreg, $eax :: (store 4 into %stack.0)\n" 806 " $rbx = MOV64rm $rsp, 1, $noreg, 0, $noreg :: (load 8 from %stack.0)\n" 807 " RET64\n"); 808 setupLDVObj(MF); 809 TransferMap.clear(); 810 TransferMap.resize(1); 811 produceMLocTransferFunction(*MF, TransferMap, 1); 812 813 // Check lower five registers up to and include $eax == $ebx, 814 for (unsigned int I = 0; I < 5; ++I) { 815 LocIdx A = MTracker->getRegMLoc(getRegByName(ARegs[I])); 816 LocIdx B = MTracker->getRegMLoc(getRegByName(BRegs[I])); 817 EXPECT_EQ(MTracker->readMLoc(A), MTracker->readMLoc(B)); 818 } 819 820 // $rbx should contain something else; today it's a def at the spill point 821 // of the 4 byte value. 822 SpillLoc L = {getRegByName("RSP"), StackOffset::getFixed(-8)}; 823 SpillLocationNo SpillNo = *MTracker->getOrTrackSpillLoc(L); 824 unsigned SpillID = MTracker->getLocID(SpillNo, {64, 0}); 825 LocIdx Spill64Loc = MTracker->getSpillMLoc(SpillID); 826 ValueIDNum DefAtSpill64(0, 3, Spill64Loc); 827 LocIdx RbxLoc = MTracker->getRegMLoc(getRegByName("RBX")); 828 EXPECT_EQ(MTracker->readMLoc(RbxLoc), DefAtSpill64); 829 830 // Same again, test that the lower four subreg slots on the stack are the 831 // value defined by $rax in instruction 1. 832 for (unsigned int I = 0; I < 4; ++I) { 833 // Value number where it's defined, 834 LocIdx RegLoc = MTracker->getRegMLoc(getRegByName(SubRegNames[I])); 835 ValueIDNum DefNum(0, 1, RegLoc); 836 // Read the corresponding subreg field from the stack. 837 SpillNo = *MTracker->getOrTrackSpillLoc(L); 838 SpillID = MTracker->getLocID(SpillNo, SubRegIdxes[I]); 839 LocIdx SpillLoc = MTracker->getSpillMLoc(SpillID); 840 ValueIDNum SpillValue = MTracker->readMLoc(SpillLoc); 841 EXPECT_EQ(DefNum, SpillValue); 842 } 843 844 // Stack slot for $rax should be a different value, today it's EmptyValue. 845 ValueIDNum SpillValue = MTracker->readMLoc(Spill64Loc); 846 EXPECT_EQ(SpillValue, DefAtSpill64); 847 848 // If we write something to the stack, then over-write with some register 849 // from a completely different hierarchy, none of the "old" values should be 850 // readable. 851 // NB: slight hack, store 16 in to a 8 byte stack slot. 852 MF = readMIRBlock( 853 " $rax = MOV64ri 0\n" 854 " MOV64mr $rsp, 1, $noreg, 16, $noreg, $rax :: (store 8 into %stack.0)\n" 855 " $xmm0 = IMPLICIT_DEF\n" 856 " MOVUPDmr $rsp, 1, $noreg, 16, $noreg, killed $xmm0 :: (store (s128) into %stack.0)\n" 857 " $rbx = MOV64rm $rsp, 1, $noreg, 0, $noreg :: (load 8 from %stack.0)\n" 858 " RET64\n"); 859 setupLDVObj(MF); 860 TransferMap.clear(); 861 TransferMap.resize(1); 862 produceMLocTransferFunction(*MF, TransferMap, 1); 863 864 for (unsigned int I = 0; I < 5; ++I) { 865 // Read subreg fields from the stack. 866 SpillLocationNo SpillNo = *MTracker->getOrTrackSpillLoc(L); 867 unsigned SpillID = MTracker->getLocID(SpillNo, SubRegIdxes[I]); 868 LocIdx SpillLoc = MTracker->getSpillMLoc(SpillID); 869 ValueIDNum SpillValue = MTracker->readMLoc(SpillLoc); 870 871 // Value should be defined by the spill-to-xmm0 instr, get value of a def 872 // at the point of the spill. 873 ValueIDNum SpillDef(0, 4, SpillLoc); 874 EXPECT_EQ(SpillValue, SpillDef); 875 } 876 877 // Read xmm0's position and ensure it has a value. Should be the live-in 878 // value to the block, as IMPLICIT_DEF isn't a real def. 879 SpillNo = *MTracker->getOrTrackSpillLoc(L); 880 SpillID = MTracker->getLocID(SpillNo, {128, 0}); 881 LocIdx Spill128Loc = MTracker->getSpillMLoc(SpillID); 882 SpillValue = MTracker->readMLoc(Spill128Loc); 883 Register XMM0 = getRegByName("XMM0"); 884 LocIdx Xmm0Loc = MTracker->getRegMLoc(XMM0); 885 EXPECT_EQ(ValueIDNum(0, 0, Xmm0Loc), SpillValue); 886 887 // What happens if we spill ah to the stack, then load al? It should find 888 // the same value. 889 MF = readMIRBlock( 890 " $rax = MOV64ri 0\n" 891 " MOV8mr $rsp, 1, $noreg, 16, $noreg, $ah :: (store 1 into %stack.0)\n" 892 " $al = MOV8rm $rsp, 1, $noreg, 0, $noreg :: (load 1 from %stack.0)\n" 893 " RET64\n"); 894 setupLDVObj(MF); 895 TransferMap.clear(); 896 TransferMap.resize(1); 897 produceMLocTransferFunction(*MF, TransferMap, 1); 898 899 Register AL = getRegByName("AL"); 900 Register AH = getRegByName("AH"); 901 LocIdx AlLoc = MTracker->getRegMLoc(AL); 902 LocIdx AhLoc = MTracker->getRegMLoc(AH); 903 ValueIDNum AHDef(0, 1, AhLoc); 904 ValueIDNum ALValue = MTracker->readMLoc(AlLoc); 905 EXPECT_EQ(ALValue, AHDef); 906 } 907 908 TEST_F(InstrRefLDVTest, MLocSingleBlock) { 909 // Test some very simple properties about interpreting the transfer function. 910 setupSingleBlock(); 911 912 // We should start with a single location, the stack pointer. 913 ASSERT_TRUE(MTracker->getNumLocs() == 1); 914 LocIdx RspLoc(0); 915 916 // Set up live-in and live-out tables for this function: two locations (we 917 // add one later) in a single block. 918 FuncValueTable MOutLocs, MInLocs; 919 std::tie(MOutLocs, MInLocs) = allocValueTables(1, 2); 920 921 // Transfer function: nothing. 922 SmallVector<MLocTransferMap, 1> TransferFunc; 923 TransferFunc.resize(1); 924 925 // Try and build value maps... 926 buildMLocValueMap(MInLocs, MOutLocs, TransferFunc); 927 928 // The result should be that RSP is marked as a live-in-PHI -- this represents 929 // an argument. And as there's no transfer function, the block live-out should 930 // be the same. 931 EXPECT_EQ(MInLocs[0][0], ValueIDNum(0, 0, RspLoc)); 932 EXPECT_EQ(MOutLocs[0][0], ValueIDNum(0, 0, RspLoc)); 933 934 // Try again, this time initialising the in-locs to be defined by an 935 // instruction. The entry block should always be re-assigned to be the 936 // arguments. 937 initValueArray(MInLocs, 1, 2); 938 initValueArray(MOutLocs, 1, 2); 939 MInLocs[0][0] = ValueIDNum(0, 1, RspLoc); 940 buildMLocValueMap(MInLocs, MOutLocs, TransferFunc); 941 EXPECT_EQ(MInLocs[0][0], ValueIDNum(0, 0, RspLoc)); 942 EXPECT_EQ(MOutLocs[0][0], ValueIDNum(0, 0, RspLoc)); 943 944 // Now insert something into the transfer function to assign to the single 945 // machine location. 946 TransferFunc[0].insert({RspLoc, ValueIDNum(0, 1, RspLoc)}); 947 initValueArray(MInLocs, 1, 2); 948 initValueArray(MOutLocs, 1, 2); 949 buildMLocValueMap(MInLocs, MOutLocs, TransferFunc); 950 EXPECT_EQ(MInLocs[0][0], ValueIDNum(0, 0, RspLoc)); 951 EXPECT_EQ(MOutLocs[0][0], ValueIDNum(0, 1, RspLoc)); 952 TransferFunc[0].clear(); 953 954 // Add a new register to be tracked, and insert it into the transfer function 955 // as a copy. The output of $rax should be the live-in value of $rsp. 956 Register RAX = getRegByName("RAX"); 957 LocIdx RaxLoc = MTracker->lookupOrTrackRegister(RAX); 958 TransferFunc[0].insert({RspLoc, ValueIDNum(0, 1, RspLoc)}); 959 TransferFunc[0].insert({RaxLoc, ValueIDNum(0, 0, RspLoc)}); 960 initValueArray(MInLocs, 1, 2); 961 initValueArray(MOutLocs, 1, 2); 962 buildMLocValueMap(MInLocs, MOutLocs, TransferFunc); 963 EXPECT_EQ(MInLocs[0][0], ValueIDNum(0, 0, RspLoc)); 964 EXPECT_EQ(MInLocs[0][1], ValueIDNum(0, 0, RaxLoc)); 965 EXPECT_EQ(MOutLocs[0][0], ValueIDNum(0, 1, RspLoc)); 966 EXPECT_EQ(MOutLocs[0][1], ValueIDNum(0, 0, RspLoc)); // Rax contains RspLoc. 967 TransferFunc[0].clear(); 968 } 969 970 TEST_F(InstrRefLDVTest, MLocDiamondBlocks) { 971 // Test that information flows from the entry block to two successors. 972 // entry 973 // / \ 974 // br1 br2 975 // \ / 976 // ret 977 setupDiamondBlocks(); 978 979 ASSERT_TRUE(MTracker->getNumLocs() == 1); 980 LocIdx RspLoc(0); 981 Register RAX = getRegByName("RAX"); 982 LocIdx RaxLoc = MTracker->lookupOrTrackRegister(RAX); 983 984 FuncValueTable MInLocs, MOutLocs; 985 std::tie(MInLocs, MOutLocs) = allocValueTables(4, 2); 986 987 // Transfer function: start with nothing. 988 SmallVector<MLocTransferMap, 1> TransferFunc; 989 TransferFunc.resize(4); 990 991 // Name some values. 992 unsigned EntryBlk = 0, BrBlk1 = 1, BrBlk2 = 2, RetBlk = 3; 993 994 ValueIDNum LiveInRsp(EntryBlk, 0, RspLoc); 995 ValueIDNum RspDefInBlk0(EntryBlk, 1, RspLoc); 996 ValueIDNum RspDefInBlk1(BrBlk1, 1, RspLoc); 997 ValueIDNum RspDefInBlk2(BrBlk2, 1, RspLoc); 998 ValueIDNum RspPHIInBlk3(RetBlk, 0, RspLoc); 999 ValueIDNum RaxLiveInBlk1(BrBlk1, 0, RaxLoc); 1000 ValueIDNum RaxLiveInBlk2(BrBlk2, 0, RaxLoc); 1001 1002 // With no transfer function, the live-in values to the entry block should 1003 // propagate to all live-outs and the live-ins to the two successor blocks. 1004 // IN ADDITION: this checks that the exit block doesn't get a PHI put in it. 1005 initValueArray(MInLocs, 4, 2); 1006 initValueArray(MOutLocs, 4, 2); 1007 buildMLocValueMap(MInLocs, MOutLocs, TransferFunc); 1008 EXPECT_EQ(MInLocs[0][0], LiveInRsp); 1009 EXPECT_EQ(MInLocs[1][0], LiveInRsp); 1010 EXPECT_EQ(MInLocs[2][0], LiveInRsp); 1011 EXPECT_EQ(MInLocs[3][0], LiveInRsp); 1012 EXPECT_EQ(MOutLocs[0][0], LiveInRsp); 1013 EXPECT_EQ(MOutLocs[1][0], LiveInRsp); 1014 EXPECT_EQ(MOutLocs[2][0], LiveInRsp); 1015 EXPECT_EQ(MOutLocs[3][0], LiveInRsp); 1016 // (Skipped writing out locations for $rax). 1017 1018 // Check that a def of $rsp in the entry block will likewise reach all the 1019 // successors. 1020 TransferFunc[0].insert({RspLoc, RspDefInBlk0}); 1021 initValueArray(MInLocs, 4, 2); 1022 initValueArray(MOutLocs, 4, 2); 1023 buildMLocValueMap(MInLocs, MOutLocs, TransferFunc); 1024 EXPECT_EQ(MInLocs[0][0], LiveInRsp); 1025 EXPECT_EQ(MInLocs[1][0], RspDefInBlk0); 1026 EXPECT_EQ(MInLocs[2][0], RspDefInBlk0); 1027 EXPECT_EQ(MInLocs[3][0], RspDefInBlk0); 1028 EXPECT_EQ(MOutLocs[0][0], RspDefInBlk0); 1029 EXPECT_EQ(MOutLocs[1][0], RspDefInBlk0); 1030 EXPECT_EQ(MOutLocs[2][0], RspDefInBlk0); 1031 EXPECT_EQ(MOutLocs[3][0], RspDefInBlk0); 1032 TransferFunc[0].clear(); 1033 1034 // Def in one branch of the diamond means that we need a PHI in the ret block 1035 TransferFunc[0].insert({RspLoc, RspDefInBlk0}); 1036 TransferFunc[1].insert({RspLoc, RspDefInBlk1}); 1037 initValueArray(MInLocs, 4, 2); 1038 initValueArray(MOutLocs, 4, 2); 1039 buildMLocValueMap(MInLocs, MOutLocs, TransferFunc); 1040 // This value map: like above, where RspDefInBlk0 is propagated through one 1041 // branch of the diamond, but is def'ed in the live-outs of the other. The 1042 // ret / merging block should have a PHI in its live-ins. 1043 EXPECT_EQ(MInLocs[0][0], LiveInRsp); 1044 EXPECT_EQ(MInLocs[1][0], RspDefInBlk0); 1045 EXPECT_EQ(MInLocs[2][0], RspDefInBlk0); 1046 EXPECT_EQ(MInLocs[3][0], RspPHIInBlk3); 1047 EXPECT_EQ(MOutLocs[0][0], RspDefInBlk0); 1048 EXPECT_EQ(MOutLocs[1][0], RspDefInBlk1); 1049 EXPECT_EQ(MOutLocs[2][0], RspDefInBlk0); 1050 EXPECT_EQ(MOutLocs[3][0], RspPHIInBlk3); 1051 TransferFunc[0].clear(); 1052 TransferFunc[1].clear(); 1053 1054 // If we have differeing defs in either side of the diamond, we should 1055 // continue to produce a PHI, 1056 TransferFunc[0].insert({RspLoc, RspDefInBlk0}); 1057 TransferFunc[1].insert({RspLoc, RspDefInBlk1}); 1058 TransferFunc[2].insert({RspLoc, RspDefInBlk2}); 1059 initValueArray(MInLocs, 4, 2); 1060 initValueArray(MOutLocs, 4, 2); 1061 buildMLocValueMap(MInLocs, MOutLocs, TransferFunc); 1062 EXPECT_EQ(MInLocs[0][0], LiveInRsp); 1063 EXPECT_EQ(MInLocs[1][0], RspDefInBlk0); 1064 EXPECT_EQ(MInLocs[2][0], RspDefInBlk0); 1065 EXPECT_EQ(MInLocs[3][0], RspPHIInBlk3); 1066 EXPECT_EQ(MOutLocs[0][0], RspDefInBlk0); 1067 EXPECT_EQ(MOutLocs[1][0], RspDefInBlk1); 1068 EXPECT_EQ(MOutLocs[2][0], RspDefInBlk2); 1069 EXPECT_EQ(MOutLocs[3][0], RspPHIInBlk3); 1070 TransferFunc[0].clear(); 1071 TransferFunc[1].clear(); 1072 TransferFunc[2].clear(); 1073 1074 // If we have defs of the same value on either side of the branch, a PHI will 1075 // initially be created, however value propagation should then eliminate it. 1076 // Encode this by copying the live-in value to $rax, and copying it to $rsp 1077 // from $rax in each branch of the diamond. We don't allow the definition of 1078 // arbitary values in transfer functions. 1079 TransferFunc[0].insert({RspLoc, RspDefInBlk0}); 1080 TransferFunc[0].insert({RaxLoc, LiveInRsp}); 1081 TransferFunc[1].insert({RspLoc, RaxLiveInBlk1}); 1082 TransferFunc[2].insert({RspLoc, RaxLiveInBlk2}); 1083 initValueArray(MInLocs, 4, 2); 1084 initValueArray(MOutLocs, 4, 2); 1085 buildMLocValueMap(MInLocs, MOutLocs, TransferFunc); 1086 EXPECT_EQ(MInLocs[0][0], LiveInRsp); 1087 EXPECT_EQ(MInLocs[1][0], RspDefInBlk0); 1088 EXPECT_EQ(MInLocs[2][0], RspDefInBlk0); 1089 EXPECT_EQ(MInLocs[3][0], LiveInRsp); 1090 EXPECT_EQ(MOutLocs[0][0], RspDefInBlk0); 1091 EXPECT_EQ(MOutLocs[1][0], LiveInRsp); 1092 EXPECT_EQ(MOutLocs[2][0], LiveInRsp); 1093 EXPECT_EQ(MOutLocs[3][0], LiveInRsp); 1094 TransferFunc[0].clear(); 1095 TransferFunc[1].clear(); 1096 TransferFunc[2].clear(); 1097 } 1098 1099 TEST_F(InstrRefLDVTest, MLocDiamondSpills) { 1100 // Test that defs in stack locations that require PHIs, cause PHIs to be 1101 // installed in aliasing locations. i.e., if there's a PHI in the lower 1102 // 8 bits of the stack, there should be PHIs for 16/32/64 bit locations 1103 // on the stack too. 1104 // Technically this isn't needed for accuracy: we should calculate PHIs 1105 // independently for each location. However, because there's an optimisation 1106 // that only places PHIs for the lower "interfering" parts of stack slots, 1107 // test for this behaviour. 1108 setupDiamondBlocks(); 1109 1110 ASSERT_TRUE(MTracker->getNumLocs() == 1); 1111 LocIdx RspLoc(0); 1112 1113 // Create a stack location and ensure it's tracked. 1114 SpillLoc SL = {getRegByName("RSP"), StackOffset::getFixed(-8)}; 1115 SpillLocationNo SpillNo = *MTracker->getOrTrackSpillLoc(SL); 1116 ASSERT_EQ(MTracker->getNumLocs(), 10u); // Tracks all possible stack locs. 1117 // Locations are: RSP, stack slots from 2^3 bits wide up to 2^9 for zmm regs, 1118 // then slots for sub_8bit_hi and sub_16bit_hi ({8, 8} and {16, 16}). 1119 1120 // Pick out the locations on the stack that various x86 regs would be written 1121 // to. HAX is the upper 16 bits of EAX. 1122 unsigned ALID = MTracker->getLocID(SpillNo, {8, 0}); 1123 unsigned AHID = MTracker->getLocID(SpillNo, {8, 8}); 1124 unsigned AXID = MTracker->getLocID(SpillNo, {16, 0}); 1125 unsigned EAXID = MTracker->getLocID(SpillNo, {32, 0}); 1126 unsigned HAXID = MTracker->getLocID(SpillNo, {16, 16}); 1127 unsigned RAXID = MTracker->getLocID(SpillNo, {64, 0}); 1128 LocIdx ALStackLoc = MTracker->getSpillMLoc(ALID); 1129 LocIdx AHStackLoc = MTracker->getSpillMLoc(AHID); 1130 LocIdx AXStackLoc = MTracker->getSpillMLoc(AXID); 1131 LocIdx EAXStackLoc = MTracker->getSpillMLoc(EAXID); 1132 LocIdx HAXStackLoc = MTracker->getSpillMLoc(HAXID); 1133 LocIdx RAXStackLoc = MTracker->getSpillMLoc(RAXID); 1134 // There are other locations, for things like xmm0, which we're going to 1135 // ignore here. 1136 1137 FuncValueTable MInLocs, MOutLocs; 1138 std::tie(MInLocs, MOutLocs) = allocValueTables(4, 10); 1139 1140 // Transfer function: start with nothing. 1141 SmallVector<MLocTransferMap, 1> TransferFunc; 1142 TransferFunc.resize(4); 1143 1144 // Name some values. 1145 unsigned EntryBlk = 0, Blk1 = 1, RetBlk = 3; 1146 1147 ValueIDNum LiveInRsp(EntryBlk, 0, RspLoc); 1148 ValueIDNum ALLiveIn(EntryBlk, 0, ALStackLoc); 1149 ValueIDNum AHLiveIn(EntryBlk, 0, AHStackLoc); 1150 ValueIDNum HAXLiveIn(EntryBlk, 0, HAXStackLoc); 1151 ValueIDNum ALPHI(RetBlk, 0, ALStackLoc); 1152 ValueIDNum AXPHI(RetBlk, 0, AXStackLoc); 1153 ValueIDNum EAXPHI(RetBlk, 0, EAXStackLoc); 1154 ValueIDNum HAXPHI(RetBlk, 0, HAXStackLoc); 1155 ValueIDNum RAXPHI(RetBlk, 0, RAXStackLoc); 1156 1157 ValueIDNum ALDefInBlk1(Blk1, 1, ALStackLoc); 1158 ValueIDNum HAXDefInBlk1(Blk1, 1, HAXStackLoc); 1159 1160 SmallPtrSet<MachineBasicBlock *, 4> AllBlocks{MBB0, MBB1, MBB2, MBB3}; 1161 1162 // If we put defs into one side of the diamond, for AL and HAX, then we should 1163 // find all aliasing positions have PHIs placed. This isn't technically what 1164 // the transfer function says to do: but we're testing that the optimisation 1165 // to reduce IDF calculation does the right thing. 1166 // AH should not be def'd: it don't alias AL or HAX. 1167 // 1168 // NB: we don't call buildMLocValueMap, because it will try to eliminate the 1169 // upper-slot PHIs, and succeed because of our slightly cooked transfer 1170 // function. 1171 TransferFunc[1].insert({ALStackLoc, ALDefInBlk1}); 1172 TransferFunc[1].insert({HAXStackLoc, HAXDefInBlk1}); 1173 initValueArray(MInLocs, 4, 10); 1174 placeMLocPHIs(*MF, AllBlocks, MInLocs, TransferFunc); 1175 EXPECT_EQ(MInLocs[3][ALStackLoc.asU64()], ALPHI); 1176 EXPECT_EQ(MInLocs[3][AXStackLoc.asU64()], AXPHI); 1177 EXPECT_EQ(MInLocs[3][EAXStackLoc.asU64()], EAXPHI); 1178 EXPECT_EQ(MInLocs[3][HAXStackLoc.asU64()], HAXPHI); 1179 EXPECT_EQ(MInLocs[3][RAXStackLoc.asU64()], RAXPHI); 1180 // AH should be left untouched, 1181 EXPECT_EQ(MInLocs[3][AHStackLoc.asU64()], ValueIDNum::EmptyValue); 1182 } 1183 1184 TEST_F(InstrRefLDVTest, MLocSimpleLoop) { 1185 // entry 1186 // | 1187 // |/-----\ 1188 // loopblk | 1189 // |\-----/ 1190 // | 1191 // ret 1192 setupSimpleLoop(); 1193 1194 ASSERT_TRUE(MTracker->getNumLocs() == 1); 1195 LocIdx RspLoc(0); 1196 Register RAX = getRegByName("RAX"); 1197 LocIdx RaxLoc = MTracker->lookupOrTrackRegister(RAX); 1198 1199 FuncValueTable MInLocs, MOutLocs; 1200 std::tie(MInLocs, MOutLocs) = allocValueTables(3, 2); 1201 1202 SmallVector<MLocTransferMap, 1> TransferFunc; 1203 TransferFunc.resize(3); 1204 1205 // Name some values. 1206 unsigned EntryBlk = 0, LoopBlk = 1, RetBlk = 2; 1207 1208 ValueIDNum LiveInRsp(EntryBlk, 0, RspLoc); 1209 ValueIDNum RspPHIInBlk1(LoopBlk, 0, RspLoc); 1210 ValueIDNum RspDefInBlk1(LoopBlk, 1, RspLoc); 1211 ValueIDNum LiveInRax(EntryBlk, 0, RaxLoc); 1212 ValueIDNum RaxPHIInBlk1(LoopBlk, 0, RaxLoc); 1213 ValueIDNum RaxPHIInBlk2(RetBlk, 0, RaxLoc); 1214 1215 // Begin test with all locations being live-through. 1216 initValueArray(MInLocs, 3, 2); 1217 initValueArray(MOutLocs, 3, 2); 1218 buildMLocValueMap(MInLocs, MOutLocs, TransferFunc); 1219 EXPECT_EQ(MInLocs[0][0], LiveInRsp); 1220 EXPECT_EQ(MInLocs[1][0], LiveInRsp); 1221 EXPECT_EQ(MInLocs[2][0], LiveInRsp); 1222 EXPECT_EQ(MOutLocs[0][0], LiveInRsp); 1223 EXPECT_EQ(MOutLocs[1][0], LiveInRsp); 1224 EXPECT_EQ(MOutLocs[2][0], LiveInRsp); 1225 1226 // Add a def of $rsp to the loop block: it should be in the live-outs, but 1227 // should cause a PHI to be placed in the live-ins. Test the transfer function 1228 // by copying that PHI into $rax in the loop, then back to $rsp in the ret 1229 // block. 1230 TransferFunc[1].insert({RspLoc, RspDefInBlk1}); 1231 TransferFunc[1].insert({RaxLoc, RspPHIInBlk1}); 1232 TransferFunc[2].insert({RspLoc, RaxPHIInBlk2}); 1233 initValueArray(MInLocs, 3, 2); 1234 initValueArray(MOutLocs, 3, 2); 1235 buildMLocValueMap(MInLocs, MOutLocs, TransferFunc); 1236 EXPECT_EQ(MInLocs[0][0], LiveInRsp); 1237 EXPECT_EQ(MInLocs[1][0], RspPHIInBlk1); 1238 EXPECT_EQ(MInLocs[2][0], RspDefInBlk1); 1239 EXPECT_EQ(MOutLocs[0][0], LiveInRsp); 1240 EXPECT_EQ(MOutLocs[1][0], RspDefInBlk1); 1241 EXPECT_EQ(MOutLocs[2][0], RspPHIInBlk1); 1242 // Check rax as well, 1243 EXPECT_EQ(MInLocs[0][1], LiveInRax); 1244 EXPECT_EQ(MInLocs[1][1], RaxPHIInBlk1); 1245 EXPECT_EQ(MInLocs[2][1], RspPHIInBlk1); 1246 EXPECT_EQ(MOutLocs[0][1], LiveInRax); 1247 EXPECT_EQ(MOutLocs[1][1], RspPHIInBlk1); 1248 EXPECT_EQ(MOutLocs[2][1], RspPHIInBlk1); 1249 TransferFunc[1].clear(); 1250 TransferFunc[2].clear(); 1251 1252 // As with the diamond case, a PHI will be created if there's a (implicit) 1253 // def in the entry block and loop block; but should be value propagated away 1254 // if it copies in the same value. Copy live-in $rsp to $rax, then copy it 1255 // into $rsp in the loop. Encoded as copying the live-in $rax value in block 1 1256 // to $rsp. 1257 TransferFunc[0].insert({RaxLoc, LiveInRsp}); 1258 TransferFunc[1].insert({RspLoc, RaxPHIInBlk1}); 1259 initValueArray(MInLocs, 3, 2); 1260 initValueArray(MOutLocs, 3, 2); 1261 buildMLocValueMap(MInLocs, MOutLocs, TransferFunc); 1262 EXPECT_EQ(MInLocs[0][0], LiveInRsp); 1263 EXPECT_EQ(MInLocs[1][0], LiveInRsp); 1264 EXPECT_EQ(MInLocs[2][0], LiveInRsp); 1265 EXPECT_EQ(MOutLocs[0][0], LiveInRsp); 1266 EXPECT_EQ(MOutLocs[1][0], LiveInRsp); 1267 EXPECT_EQ(MOutLocs[2][0], LiveInRsp); 1268 // Check $rax's values. 1269 EXPECT_EQ(MInLocs[0][1], LiveInRax); 1270 EXPECT_EQ(MInLocs[1][1], LiveInRsp); 1271 EXPECT_EQ(MInLocs[2][1], LiveInRsp); 1272 EXPECT_EQ(MOutLocs[0][1], LiveInRsp); 1273 EXPECT_EQ(MOutLocs[1][1], LiveInRsp); 1274 EXPECT_EQ(MOutLocs[2][1], LiveInRsp); 1275 TransferFunc[0].clear(); 1276 TransferFunc[1].clear(); 1277 } 1278 1279 TEST_F(InstrRefLDVTest, MLocNestedLoop) { 1280 // entry 1281 // | 1282 // loop1 1283 // ^\ 1284 // | \ /-\ 1285 // | loop2 | 1286 // | / \-/ 1287 // ^ / 1288 // join 1289 // | 1290 // ret 1291 setupNestedLoops(); 1292 1293 ASSERT_TRUE(MTracker->getNumLocs() == 1); 1294 LocIdx RspLoc(0); 1295 Register RAX = getRegByName("RAX"); 1296 LocIdx RaxLoc = MTracker->lookupOrTrackRegister(RAX); 1297 1298 FuncValueTable MInLocs, MOutLocs; 1299 std::tie(MInLocs, MOutLocs) = allocValueTables(5, 2); 1300 1301 SmallVector<MLocTransferMap, 1> TransferFunc; 1302 TransferFunc.resize(5); 1303 1304 unsigned EntryBlk = 0, Loop1Blk = 1, Loop2Blk = 2, JoinBlk = 3; 1305 1306 ValueIDNum LiveInRsp(EntryBlk, 0, RspLoc); 1307 ValueIDNum RspPHIInBlk1(Loop1Blk, 0, RspLoc); 1308 ValueIDNum RspDefInBlk1(Loop1Blk, 1, RspLoc); 1309 ValueIDNum RspPHIInBlk2(Loop2Blk, 0, RspLoc); 1310 ValueIDNum RspDefInBlk2(Loop2Blk, 1, RspLoc); 1311 ValueIDNum RspDefInBlk3(JoinBlk, 1, RspLoc); 1312 ValueIDNum LiveInRax(EntryBlk, 0, RaxLoc); 1313 ValueIDNum RaxPHIInBlk1(Loop1Blk, 0, RaxLoc); 1314 ValueIDNum RaxPHIInBlk2(Loop2Blk, 0, RaxLoc); 1315 1316 // Like the other tests: first ensure that if there's nothing in the transfer 1317 // function, then everything is live-through (check $rsp). 1318 initValueArray(MInLocs, 5, 2); 1319 initValueArray(MOutLocs, 5, 2); 1320 buildMLocValueMap(MInLocs, MOutLocs, TransferFunc); 1321 EXPECT_EQ(MInLocs[0][0], LiveInRsp); 1322 EXPECT_EQ(MInLocs[1][0], LiveInRsp); 1323 EXPECT_EQ(MInLocs[2][0], LiveInRsp); 1324 EXPECT_EQ(MInLocs[3][0], LiveInRsp); 1325 EXPECT_EQ(MInLocs[4][0], LiveInRsp); 1326 EXPECT_EQ(MOutLocs[0][0], LiveInRsp); 1327 EXPECT_EQ(MOutLocs[1][0], LiveInRsp); 1328 EXPECT_EQ(MOutLocs[2][0], LiveInRsp); 1329 EXPECT_EQ(MOutLocs[3][0], LiveInRsp); 1330 EXPECT_EQ(MOutLocs[4][0], LiveInRsp); 1331 1332 // A def in the inner loop means we should get PHIs at the heads of both 1333 // loops. Live-outs of the last three blocks will be the def, as it dominates 1334 // those. 1335 TransferFunc[2].insert({RspLoc, RspDefInBlk2}); 1336 initValueArray(MInLocs, 5, 2); 1337 initValueArray(MOutLocs, 5, 2); 1338 buildMLocValueMap(MInLocs, MOutLocs, TransferFunc); 1339 EXPECT_EQ(MInLocs[0][0], LiveInRsp); 1340 EXPECT_EQ(MInLocs[1][0], RspPHIInBlk1); 1341 EXPECT_EQ(MInLocs[2][0], RspPHIInBlk2); 1342 EXPECT_EQ(MInLocs[3][0], RspDefInBlk2); 1343 EXPECT_EQ(MInLocs[4][0], RspDefInBlk2); 1344 EXPECT_EQ(MOutLocs[0][0], LiveInRsp); 1345 EXPECT_EQ(MOutLocs[1][0], RspPHIInBlk1); 1346 EXPECT_EQ(MOutLocs[2][0], RspDefInBlk2); 1347 EXPECT_EQ(MOutLocs[3][0], RspDefInBlk2); 1348 EXPECT_EQ(MOutLocs[4][0], RspDefInBlk2); 1349 TransferFunc[2].clear(); 1350 1351 // Adding a def to the outer loop header shouldn't affect this much -- the 1352 // live-out of block 1 changes. 1353 TransferFunc[1].insert({RspLoc, RspDefInBlk1}); 1354 TransferFunc[2].insert({RspLoc, RspDefInBlk2}); 1355 initValueArray(MInLocs, 5, 2); 1356 initValueArray(MOutLocs, 5, 2); 1357 buildMLocValueMap(MInLocs, MOutLocs, TransferFunc); 1358 EXPECT_EQ(MInLocs[0][0], LiveInRsp); 1359 EXPECT_EQ(MInLocs[1][0], RspPHIInBlk1); 1360 EXPECT_EQ(MInLocs[2][0], RspPHIInBlk2); 1361 EXPECT_EQ(MInLocs[3][0], RspDefInBlk2); 1362 EXPECT_EQ(MInLocs[4][0], RspDefInBlk2); 1363 EXPECT_EQ(MOutLocs[0][0], LiveInRsp); 1364 EXPECT_EQ(MOutLocs[1][0], RspDefInBlk1); 1365 EXPECT_EQ(MOutLocs[2][0], RspDefInBlk2); 1366 EXPECT_EQ(MOutLocs[3][0], RspDefInBlk2); 1367 EXPECT_EQ(MOutLocs[4][0], RspDefInBlk2); 1368 TransferFunc[1].clear(); 1369 TransferFunc[2].clear(); 1370 1371 // Likewise, putting a def in the outer loop tail shouldn't affect where 1372 // the PHIs go, and should propagate into the ret block. 1373 1374 TransferFunc[1].insert({RspLoc, RspDefInBlk1}); 1375 TransferFunc[2].insert({RspLoc, RspDefInBlk2}); 1376 TransferFunc[3].insert({RspLoc, RspDefInBlk3}); 1377 initValueArray(MInLocs, 5, 2); 1378 initValueArray(MOutLocs, 5, 2); 1379 buildMLocValueMap(MInLocs, MOutLocs, TransferFunc); 1380 EXPECT_EQ(MInLocs[0][0], LiveInRsp); 1381 EXPECT_EQ(MInLocs[1][0], RspPHIInBlk1); 1382 EXPECT_EQ(MInLocs[2][0], RspPHIInBlk2); 1383 EXPECT_EQ(MInLocs[3][0], RspDefInBlk2); 1384 EXPECT_EQ(MInLocs[4][0], RspDefInBlk3); 1385 EXPECT_EQ(MOutLocs[0][0], LiveInRsp); 1386 EXPECT_EQ(MOutLocs[1][0], RspDefInBlk1); 1387 EXPECT_EQ(MOutLocs[2][0], RspDefInBlk2); 1388 EXPECT_EQ(MOutLocs[3][0], RspDefInBlk3); 1389 EXPECT_EQ(MOutLocs[4][0], RspDefInBlk3); 1390 TransferFunc[1].clear(); 1391 TransferFunc[2].clear(); 1392 TransferFunc[3].clear(); 1393 1394 // However: if we don't def in the inner-loop, then we just have defs in the 1395 // head and tail of the outer loop. The inner loop should be live-through. 1396 TransferFunc[1].insert({RspLoc, RspDefInBlk1}); 1397 TransferFunc[3].insert({RspLoc, RspDefInBlk3}); 1398 initValueArray(MInLocs, 5, 2); 1399 initValueArray(MOutLocs, 5, 2); 1400 buildMLocValueMap(MInLocs, MOutLocs, TransferFunc); 1401 EXPECT_EQ(MInLocs[0][0], LiveInRsp); 1402 EXPECT_EQ(MInLocs[1][0], RspPHIInBlk1); 1403 EXPECT_EQ(MInLocs[2][0], RspDefInBlk1); 1404 EXPECT_EQ(MInLocs[3][0], RspDefInBlk1); 1405 EXPECT_EQ(MInLocs[4][0], RspDefInBlk3); 1406 EXPECT_EQ(MOutLocs[0][0], LiveInRsp); 1407 EXPECT_EQ(MOutLocs[1][0], RspDefInBlk1); 1408 EXPECT_EQ(MOutLocs[2][0], RspDefInBlk1); 1409 EXPECT_EQ(MOutLocs[3][0], RspDefInBlk3); 1410 EXPECT_EQ(MOutLocs[4][0], RspDefInBlk3); 1411 TransferFunc[1].clear(); 1412 TransferFunc[3].clear(); 1413 1414 // Check that this still works if we copy RspDefInBlk1 to $rax and then 1415 // copy it back into $rsp in the inner loop. 1416 TransferFunc[1].insert({RspLoc, RspDefInBlk1}); 1417 TransferFunc[1].insert({RaxLoc, RspDefInBlk1}); 1418 TransferFunc[2].insert({RspLoc, RaxPHIInBlk2}); 1419 TransferFunc[3].insert({RspLoc, RspDefInBlk3}); 1420 initValueArray(MInLocs, 5, 2); 1421 initValueArray(MOutLocs, 5, 2); 1422 buildMLocValueMap(MInLocs, MOutLocs, TransferFunc); 1423 EXPECT_EQ(MInLocs[0][0], LiveInRsp); 1424 EXPECT_EQ(MInLocs[1][0], RspPHIInBlk1); 1425 EXPECT_EQ(MInLocs[2][0], RspDefInBlk1); 1426 EXPECT_EQ(MInLocs[3][0], RspDefInBlk1); 1427 EXPECT_EQ(MInLocs[4][0], RspDefInBlk3); 1428 EXPECT_EQ(MOutLocs[0][0], LiveInRsp); 1429 EXPECT_EQ(MOutLocs[1][0], RspDefInBlk1); 1430 EXPECT_EQ(MOutLocs[2][0], RspDefInBlk1); 1431 EXPECT_EQ(MOutLocs[3][0], RspDefInBlk3); 1432 EXPECT_EQ(MOutLocs[4][0], RspDefInBlk3); 1433 // Look at raxes value in the relevant blocks, 1434 EXPECT_EQ(MInLocs[2][1], RspDefInBlk1); 1435 EXPECT_EQ(MOutLocs[1][1], RspDefInBlk1); 1436 TransferFunc[1].clear(); 1437 TransferFunc[2].clear(); 1438 TransferFunc[3].clear(); 1439 1440 // If we have a single def in the tail of the outer loop, that should produce 1441 // a PHI at the loop head, and be live-through the inner loop. 1442 TransferFunc[3].insert({RspLoc, RspDefInBlk3}); 1443 initValueArray(MInLocs, 5, 2); 1444 initValueArray(MOutLocs, 5, 2); 1445 buildMLocValueMap(MInLocs, MOutLocs, TransferFunc); 1446 EXPECT_EQ(MInLocs[0][0], LiveInRsp); 1447 EXPECT_EQ(MInLocs[1][0], RspPHIInBlk1); 1448 EXPECT_EQ(MInLocs[2][0], RspPHIInBlk1); 1449 EXPECT_EQ(MInLocs[3][0], RspPHIInBlk1); 1450 EXPECT_EQ(MInLocs[4][0], RspDefInBlk3); 1451 EXPECT_EQ(MOutLocs[0][0], LiveInRsp); 1452 EXPECT_EQ(MOutLocs[1][0], RspPHIInBlk1); 1453 EXPECT_EQ(MOutLocs[2][0], RspPHIInBlk1); 1454 EXPECT_EQ(MOutLocs[3][0], RspDefInBlk3); 1455 EXPECT_EQ(MOutLocs[4][0], RspDefInBlk3); 1456 TransferFunc[3].clear(); 1457 1458 // And if we copy from $rsp to $rax in block 2, it should resolve to the PHI 1459 // in block 1, and we should keep that value in rax until the ret block. 1460 // There'll be a PHI in block 1 and 2, because we're putting a def in the 1461 // inner loop. 1462 TransferFunc[2].insert({RaxLoc, RspPHIInBlk2}); 1463 TransferFunc[3].insert({RspLoc, RspDefInBlk3}); 1464 initValueArray(MInLocs, 5, 2); 1465 initValueArray(MOutLocs, 5, 2); 1466 buildMLocValueMap(MInLocs, MOutLocs, TransferFunc); 1467 // Examining the values of rax, 1468 EXPECT_EQ(MInLocs[0][1], LiveInRax); 1469 EXPECT_EQ(MInLocs[1][1], RaxPHIInBlk1); 1470 EXPECT_EQ(MInLocs[2][1], RaxPHIInBlk2); 1471 EXPECT_EQ(MInLocs[3][1], RspPHIInBlk1); 1472 EXPECT_EQ(MInLocs[4][1], RspPHIInBlk1); 1473 EXPECT_EQ(MOutLocs[0][1], LiveInRax); 1474 EXPECT_EQ(MOutLocs[1][1], RaxPHIInBlk1); 1475 EXPECT_EQ(MOutLocs[2][1], RspPHIInBlk1); 1476 EXPECT_EQ(MOutLocs[3][1], RspPHIInBlk1); 1477 EXPECT_EQ(MOutLocs[4][1], RspPHIInBlk1); 1478 TransferFunc[2].clear(); 1479 TransferFunc[3].clear(); 1480 } 1481 1482 TEST_F(InstrRefLDVTest, MLocNoDominatingLoop) { 1483 // entry 1484 // / \ 1485 // / \ 1486 // / \ 1487 // head1 head2 1488 // ^ \ / ^ 1489 // ^ \ / ^ 1490 // \-joinblk -/ 1491 // | 1492 // ret 1493 setupNoDominatingLoop(); 1494 1495 ASSERT_TRUE(MTracker->getNumLocs() == 1); 1496 LocIdx RspLoc(0); 1497 Register RAX = getRegByName("RAX"); 1498 LocIdx RaxLoc = MTracker->lookupOrTrackRegister(RAX); 1499 1500 FuncValueTable MInLocs, MOutLocs; 1501 std::tie(MInLocs, MOutLocs) = allocValueTables(5, 2); 1502 1503 SmallVector<MLocTransferMap, 1> TransferFunc; 1504 TransferFunc.resize(5); 1505 1506 unsigned EntryBlk = 0, Head1Blk = 1, Head2Blk = 2, JoinBlk = 3; 1507 1508 ValueIDNum LiveInRsp(EntryBlk, 0, RspLoc); 1509 ValueIDNum RspPHIInBlk1(Head1Blk, 0, RspLoc); 1510 ValueIDNum RspDefInBlk1(Head1Blk, 1, RspLoc); 1511 ValueIDNum RspPHIInBlk2(Head2Blk, 0, RspLoc); 1512 ValueIDNum RspDefInBlk2(Head2Blk, 1, RspLoc); 1513 ValueIDNum RspPHIInBlk3(JoinBlk, 0, RspLoc); 1514 ValueIDNum RspDefInBlk3(JoinBlk, 1, RspLoc); 1515 ValueIDNum RaxPHIInBlk1(Head1Blk, 0, RaxLoc); 1516 ValueIDNum RaxPHIInBlk2(Head2Blk, 0, RaxLoc); 1517 1518 // As ever, test that everything is live-through if there are no defs. 1519 initValueArray(MInLocs, 5, 2); 1520 initValueArray(MOutLocs, 5, 2); 1521 buildMLocValueMap(MInLocs, MOutLocs, TransferFunc); 1522 EXPECT_EQ(MInLocs[0][0], LiveInRsp); 1523 EXPECT_EQ(MInLocs[1][0], LiveInRsp); 1524 EXPECT_EQ(MInLocs[2][0], LiveInRsp); 1525 EXPECT_EQ(MInLocs[3][0], LiveInRsp); 1526 EXPECT_EQ(MInLocs[4][0], LiveInRsp); 1527 EXPECT_EQ(MOutLocs[0][0], LiveInRsp); 1528 EXPECT_EQ(MOutLocs[1][0], LiveInRsp); 1529 EXPECT_EQ(MOutLocs[2][0], LiveInRsp); 1530 EXPECT_EQ(MOutLocs[3][0], LiveInRsp); 1531 EXPECT_EQ(MOutLocs[4][0], LiveInRsp); 1532 1533 // Putting a def in the 'join' block will cause us to have two distinct 1534 // PHIs in each loop head, then on entry to the join block. 1535 TransferFunc[3].insert({RspLoc, RspDefInBlk3}); 1536 initValueArray(MInLocs, 5, 2); 1537 initValueArray(MOutLocs, 5, 2); 1538 buildMLocValueMap(MInLocs, MOutLocs, TransferFunc); 1539 EXPECT_EQ(MInLocs[0][0], LiveInRsp); 1540 EXPECT_EQ(MInLocs[1][0], RspPHIInBlk1); 1541 EXPECT_EQ(MInLocs[2][0], RspPHIInBlk2); 1542 EXPECT_EQ(MInLocs[3][0], RspPHIInBlk3); 1543 EXPECT_EQ(MInLocs[4][0], RspDefInBlk3); 1544 EXPECT_EQ(MOutLocs[0][0], LiveInRsp); 1545 EXPECT_EQ(MOutLocs[1][0], RspPHIInBlk1); 1546 EXPECT_EQ(MOutLocs[2][0], RspPHIInBlk2); 1547 EXPECT_EQ(MOutLocs[3][0], RspDefInBlk3); 1548 EXPECT_EQ(MOutLocs[4][0], RspDefInBlk3); 1549 TransferFunc[3].clear(); 1550 1551 // We should get the same behaviour if we put the def in either of the 1552 // loop heads -- it should force the other head to be a PHI. 1553 TransferFunc[1].insert({RspLoc, RspDefInBlk1}); 1554 initValueArray(MInLocs, 5, 2); 1555 initValueArray(MOutLocs, 5, 2); 1556 buildMLocValueMap(MInLocs, MOutLocs, TransferFunc); 1557 EXPECT_EQ(MInLocs[0][0], LiveInRsp); 1558 EXPECT_EQ(MInLocs[1][0], RspPHIInBlk1); 1559 EXPECT_EQ(MInLocs[2][0], RspPHIInBlk2); 1560 EXPECT_EQ(MInLocs[3][0], RspPHIInBlk3); 1561 EXPECT_EQ(MInLocs[4][0], RspPHIInBlk3); 1562 EXPECT_EQ(MOutLocs[0][0], LiveInRsp); 1563 EXPECT_EQ(MOutLocs[1][0], RspDefInBlk1); 1564 EXPECT_EQ(MOutLocs[2][0], RspPHIInBlk2); 1565 EXPECT_EQ(MOutLocs[3][0], RspPHIInBlk3); 1566 EXPECT_EQ(MOutLocs[4][0], RspPHIInBlk3); 1567 TransferFunc[1].clear(); 1568 1569 // Check symmetry, 1570 TransferFunc[2].insert({RspLoc, RspDefInBlk2}); 1571 initValueArray(MInLocs, 5, 2); 1572 initValueArray(MOutLocs, 5, 2); 1573 buildMLocValueMap(MInLocs, MOutLocs, TransferFunc); 1574 EXPECT_EQ(MInLocs[0][0], LiveInRsp); 1575 EXPECT_EQ(MInLocs[1][0], RspPHIInBlk1); 1576 EXPECT_EQ(MInLocs[2][0], RspPHIInBlk2); 1577 EXPECT_EQ(MInLocs[3][0], RspPHIInBlk3); 1578 EXPECT_EQ(MInLocs[4][0], RspPHIInBlk3); 1579 EXPECT_EQ(MOutLocs[0][0], LiveInRsp); 1580 EXPECT_EQ(MOutLocs[1][0], RspPHIInBlk1); 1581 EXPECT_EQ(MOutLocs[2][0], RspDefInBlk2); 1582 EXPECT_EQ(MOutLocs[3][0], RspPHIInBlk3); 1583 EXPECT_EQ(MOutLocs[4][0], RspPHIInBlk3); 1584 TransferFunc[2].clear(); 1585 1586 // Test some scenarios where there _shouldn't_ be any PHIs created at heads. 1587 // These are those PHIs are created, but value propagation eliminates them. 1588 // For example, lets copy rsp-livein to $rsp inside each loop head, so that 1589 // there's no need for a PHI in the join block. Put a def of $rsp in block 3 1590 // to force PHIs elsewhere. 1591 TransferFunc[0].insert({RaxLoc, LiveInRsp}); 1592 TransferFunc[1].insert({RspLoc, RaxPHIInBlk1}); 1593 TransferFunc[2].insert({RspLoc, RaxPHIInBlk2}); 1594 TransferFunc[3].insert({RspLoc, RspDefInBlk3}); 1595 initValueArray(MInLocs, 5, 2); 1596 initValueArray(MOutLocs, 5, 2); 1597 buildMLocValueMap(MInLocs, MOutLocs, TransferFunc); 1598 EXPECT_EQ(MInLocs[0][0], LiveInRsp); 1599 EXPECT_EQ(MInLocs[1][0], RspPHIInBlk1); 1600 EXPECT_EQ(MInLocs[2][0], RspPHIInBlk2); 1601 EXPECT_EQ(MInLocs[3][0], LiveInRsp); 1602 EXPECT_EQ(MInLocs[4][0], RspDefInBlk3); 1603 EXPECT_EQ(MOutLocs[0][0], LiveInRsp); 1604 EXPECT_EQ(MOutLocs[1][0], LiveInRsp); 1605 EXPECT_EQ(MOutLocs[2][0], LiveInRsp); 1606 EXPECT_EQ(MOutLocs[3][0], RspDefInBlk3); 1607 EXPECT_EQ(MOutLocs[4][0], RspDefInBlk3); 1608 TransferFunc[0].clear(); 1609 TransferFunc[1].clear(); 1610 TransferFunc[2].clear(); 1611 TransferFunc[3].clear(); 1612 1613 // In fact, if we eliminate the def in block 3, none of those PHIs are 1614 // necessary, as we're just repeatedly copying LiveInRsp into $rsp. They 1615 // should all be value propagated out. 1616 TransferFunc[0].insert({RaxLoc, LiveInRsp}); 1617 TransferFunc[1].insert({RspLoc, RaxPHIInBlk1}); 1618 TransferFunc[2].insert({RspLoc, RaxPHIInBlk2}); 1619 initValueArray(MInLocs, 5, 2); 1620 initValueArray(MOutLocs, 5, 2); 1621 buildMLocValueMap(MInLocs, MOutLocs, TransferFunc); 1622 EXPECT_EQ(MInLocs[0][0], LiveInRsp); 1623 EXPECT_EQ(MInLocs[1][0], LiveInRsp); 1624 EXPECT_EQ(MInLocs[2][0], LiveInRsp); 1625 EXPECT_EQ(MInLocs[3][0], LiveInRsp); 1626 EXPECT_EQ(MInLocs[4][0], LiveInRsp); 1627 EXPECT_EQ(MOutLocs[0][0], LiveInRsp); 1628 EXPECT_EQ(MOutLocs[1][0], LiveInRsp); 1629 EXPECT_EQ(MOutLocs[2][0], LiveInRsp); 1630 EXPECT_EQ(MOutLocs[3][0], LiveInRsp); 1631 EXPECT_EQ(MOutLocs[4][0], LiveInRsp); 1632 TransferFunc[0].clear(); 1633 TransferFunc[1].clear(); 1634 TransferFunc[2].clear(); 1635 } 1636 1637 TEST_F(InstrRefLDVTest, MLocBadlyNestedLoops) { 1638 // entry 1639 // | 1640 // loop1 -o 1641 // | ^ 1642 // | ^ 1643 // loop2 -o 1644 // | ^ 1645 // | ^ 1646 // loop3 -o 1647 // | 1648 // ret 1649 setupBadlyNestedLoops(); 1650 1651 ASSERT_TRUE(MTracker->getNumLocs() == 1); 1652 LocIdx RspLoc(0); 1653 Register RAX = getRegByName("RAX"); 1654 LocIdx RaxLoc = MTracker->lookupOrTrackRegister(RAX); 1655 1656 FuncValueTable MInLocs, MOutLocs; 1657 std::tie(MInLocs, MOutLocs) = allocValueTables(5, 2); 1658 1659 SmallVector<MLocTransferMap, 1> TransferFunc; 1660 TransferFunc.resize(5); 1661 1662 unsigned EntryBlk = 0, Loop1Blk = 1, Loop2Blk = 2, Loop3Blk = 3; 1663 1664 ValueIDNum LiveInRsp(EntryBlk, 0, RspLoc); 1665 ValueIDNum RspPHIInBlk1(Loop1Blk, 0, RspLoc); 1666 ValueIDNum RspDefInBlk1(Loop1Blk, 1, RspLoc); 1667 ValueIDNum RspPHIInBlk2(Loop2Blk, 0, RspLoc); 1668 ValueIDNum RspPHIInBlk3(Loop3Blk, 0, RspLoc); 1669 ValueIDNum RspDefInBlk3(Loop3Blk, 1, RspLoc); 1670 ValueIDNum LiveInRax(EntryBlk, 0, RaxLoc); 1671 ValueIDNum RaxPHIInBlk3(Loop3Blk, 0, RaxLoc); 1672 1673 // As ever, test that everything is live-through if there are no defs. 1674 initValueArray(MInLocs, 5, 2); 1675 initValueArray(MOutLocs, 5, 2); 1676 buildMLocValueMap(MInLocs, MOutLocs, TransferFunc); 1677 EXPECT_EQ(MInLocs[0][0], LiveInRsp); 1678 EXPECT_EQ(MInLocs[1][0], LiveInRsp); 1679 EXPECT_EQ(MInLocs[2][0], LiveInRsp); 1680 EXPECT_EQ(MInLocs[3][0], LiveInRsp); 1681 EXPECT_EQ(MInLocs[4][0], LiveInRsp); 1682 EXPECT_EQ(MOutLocs[0][0], LiveInRsp); 1683 EXPECT_EQ(MOutLocs[1][0], LiveInRsp); 1684 EXPECT_EQ(MOutLocs[2][0], LiveInRsp); 1685 EXPECT_EQ(MOutLocs[3][0], LiveInRsp); 1686 EXPECT_EQ(MOutLocs[4][0], LiveInRsp); 1687 1688 // A def in loop3 should cause PHIs in every loop block: they're all 1689 // reachable from each other. 1690 TransferFunc[3].insert({RspLoc, RspDefInBlk3}); 1691 initValueArray(MInLocs, 5, 2); 1692 initValueArray(MOutLocs, 5, 2); 1693 buildMLocValueMap(MInLocs, MOutLocs, TransferFunc); 1694 EXPECT_EQ(MInLocs[0][0], LiveInRsp); 1695 EXPECT_EQ(MInLocs[1][0], RspPHIInBlk1); 1696 EXPECT_EQ(MInLocs[2][0], RspPHIInBlk2); 1697 EXPECT_EQ(MInLocs[3][0], RspPHIInBlk3); 1698 EXPECT_EQ(MInLocs[4][0], RspDefInBlk3); 1699 EXPECT_EQ(MOutLocs[0][0], LiveInRsp); 1700 EXPECT_EQ(MOutLocs[1][0], RspPHIInBlk1); 1701 EXPECT_EQ(MOutLocs[2][0], RspPHIInBlk2); 1702 EXPECT_EQ(MOutLocs[3][0], RspDefInBlk3); 1703 EXPECT_EQ(MOutLocs[4][0], RspDefInBlk3); 1704 TransferFunc[3].clear(); 1705 1706 // A def in loop1 should cause a PHI in loop1, but not the other blocks. 1707 // loop2 and loop3 are dominated by the def in loop1, so they should have 1708 // that value live-through. 1709 TransferFunc[1].insert({RspLoc, RspDefInBlk1}); 1710 initValueArray(MInLocs, 5, 2); 1711 initValueArray(MOutLocs, 5, 2); 1712 buildMLocValueMap(MInLocs, MOutLocs, TransferFunc); 1713 EXPECT_EQ(MInLocs[0][0], LiveInRsp); 1714 EXPECT_EQ(MInLocs[1][0], RspPHIInBlk1); 1715 EXPECT_EQ(MInLocs[2][0], RspDefInBlk1); 1716 EXPECT_EQ(MInLocs[3][0], RspDefInBlk1); 1717 EXPECT_EQ(MInLocs[4][0], RspDefInBlk1); 1718 EXPECT_EQ(MOutLocs[0][0], LiveInRsp); 1719 EXPECT_EQ(MOutLocs[1][0], RspDefInBlk1); 1720 EXPECT_EQ(MOutLocs[2][0], RspDefInBlk1); 1721 EXPECT_EQ(MOutLocs[3][0], RspDefInBlk1); 1722 EXPECT_EQ(MOutLocs[4][0], RspDefInBlk1); 1723 TransferFunc[1].clear(); 1724 1725 // As with earlier tricks: copy $rsp to $rax in the entry block, then $rax 1726 // to $rsp in block 3. The only def of $rsp is simply copying the same value 1727 // back into itself, and the value of $rsp is LiveInRsp all the way through. 1728 // PHIs should be created, then value-propagated away... however this 1729 // doesn't work in practice. 1730 // Consider the entry to loop3: we can determine that there's an incoming 1731 // PHI value from loop2, and LiveInRsp from the self-loop. This would still 1732 // justify having a PHI on entry to loop3. The only way to completely 1733 // value-propagate these PHIs away would be to speculatively explore what 1734 // PHIs could be eliminated and what that would lead to; which is 1735 // combinatorially complex. 1736 // Happily: 1737 // a) In this scenario, we always have a tracked location for LiveInRsp 1738 // anyway, so there's no loss in availability, 1739 // b) Only DBG_PHIs of a register would be vunlerable to this scenario, and 1740 // even then only if a true PHI became a DBG_PHI and was then optimised 1741 // through branch folding to no longer be at a CFG join, 1742 // c) The register allocator can spot this kind of redundant COPY easily, 1743 // and eliminate it. 1744 // 1745 // This unit test left in as a reference for the limitations of this 1746 // approach. PHIs will be left in $rsp on entry to each block. 1747 TransferFunc[0].insert({RaxLoc, LiveInRsp}); 1748 TransferFunc[3].insert({RspLoc, RaxPHIInBlk3}); 1749 initValueArray(MInLocs, 5, 2); 1750 initValueArray(MOutLocs, 5, 2); 1751 buildMLocValueMap(MInLocs, MOutLocs, TransferFunc); 1752 EXPECT_EQ(MInLocs[0][0], LiveInRsp); 1753 EXPECT_EQ(MInLocs[1][0], RspPHIInBlk1); 1754 EXPECT_EQ(MInLocs[2][0], RspPHIInBlk2); 1755 EXPECT_EQ(MInLocs[3][0], RspPHIInBlk3); 1756 EXPECT_EQ(MInLocs[4][0], LiveInRsp); 1757 EXPECT_EQ(MOutLocs[0][0], LiveInRsp); 1758 EXPECT_EQ(MOutLocs[1][0], RspPHIInBlk1); 1759 EXPECT_EQ(MOutLocs[2][0], RspPHIInBlk2); 1760 EXPECT_EQ(MOutLocs[3][0], LiveInRsp); 1761 EXPECT_EQ(MOutLocs[4][0], LiveInRsp); 1762 // Check $rax's value. It should have $rsps value from the entry block 1763 // onwards. 1764 EXPECT_EQ(MInLocs[0][1], LiveInRax); 1765 EXPECT_EQ(MInLocs[1][1], LiveInRsp); 1766 EXPECT_EQ(MInLocs[2][1], LiveInRsp); 1767 EXPECT_EQ(MInLocs[3][1], LiveInRsp); 1768 EXPECT_EQ(MInLocs[4][1], LiveInRsp); 1769 EXPECT_EQ(MOutLocs[0][1], LiveInRsp); 1770 EXPECT_EQ(MOutLocs[1][1], LiveInRsp); 1771 EXPECT_EQ(MOutLocs[2][1], LiveInRsp); 1772 EXPECT_EQ(MOutLocs[3][1], LiveInRsp); 1773 EXPECT_EQ(MOutLocs[4][1], LiveInRsp); 1774 } 1775 1776 TEST_F(InstrRefLDVTest, pickVPHILocDiamond) { 1777 // entry 1778 // / \ 1779 // br1 br2 1780 // \ / 1781 // ret 1782 setupDiamondBlocks(); 1783 1784 ASSERT_TRUE(MTracker->getNumLocs() == 1); 1785 LocIdx RspLoc(0); 1786 Register RAX = getRegByName("RAX"); 1787 LocIdx RaxLoc = MTracker->lookupOrTrackRegister(RAX); 1788 1789 FuncValueTable MInLocs, MOutLocs; 1790 std::tie(MInLocs, MOutLocs) = allocValueTables(4, 2); 1791 1792 initValueArray(MOutLocs, 4, 2); 1793 1794 unsigned EntryBlk = 0, Br2Blk = 2, RetBlk = 3; 1795 1796 ValueIDNum LiveInRsp(EntryBlk, 0, RspLoc); 1797 ValueIDNum LiveInRax(EntryBlk, 0, RaxLoc); 1798 ValueIDNum RspPHIInBlk2(Br2Blk, 0, RspLoc); 1799 ValueIDNum RspPHIInBlk3(RetBlk, 0, RspLoc); 1800 1801 DebugVariable Var(FuncVariable, None, nullptr); 1802 DbgValueProperties EmptyProps(EmptyExpr, false); 1803 SmallVector<DbgValue, 32> VLiveOuts; 1804 VLiveOuts.resize(4, DbgValue(EmptyProps, DbgValue::Undef)); 1805 InstrRefBasedLDV::LiveIdxT VLiveOutIdx; 1806 VLiveOutIdx[MBB0] = &VLiveOuts[0]; 1807 VLiveOutIdx[MBB1] = &VLiveOuts[1]; 1808 VLiveOutIdx[MBB2] = &VLiveOuts[2]; 1809 VLiveOutIdx[MBB3] = &VLiveOuts[3]; 1810 1811 SmallVector<const MachineBasicBlock *, 2> Preds; 1812 for (const auto *Pred : MBB3->predecessors()) 1813 Preds.push_back(Pred); 1814 1815 // Specify the live-outs around the joining block. 1816 MOutLocs[1][0] = LiveInRsp; 1817 MOutLocs[2][0] = LiveInRax; 1818 1819 Optional<ValueIDNum> Result; 1820 1821 // Simple case: join two distinct values on entry to the block. 1822 VLiveOuts[1] = DbgValue(LiveInRsp, EmptyProps, DbgValue::Def); 1823 VLiveOuts[2] = DbgValue(LiveInRax, EmptyProps, DbgValue::Def); 1824 Result = pickVPHILoc(*MBB3, Var, VLiveOutIdx, MOutLocs, Preds); 1825 // Should have picked a PHI in $rsp in block 3. 1826 EXPECT_TRUE(Result); 1827 if (Result) { 1828 EXPECT_EQ(*Result, RspPHIInBlk3); 1829 } 1830 1831 // If the incoming values are swapped between blocks, we should not 1832 // successfully join. The CFG merge would select the right values, but in 1833 // the wrong conditions. 1834 std::swap(VLiveOuts[1], VLiveOuts[2]); 1835 Result = pickVPHILoc(*MBB3, Var, VLiveOutIdx, MOutLocs, Preds); 1836 EXPECT_FALSE(Result); 1837 1838 // Swap back, 1839 std::swap(VLiveOuts[1], VLiveOuts[2]); 1840 // Setting one of these to being a constant should prohibit merging. 1841 VLiveOuts[1].Kind = DbgValue::Const; 1842 VLiveOuts[1].MO = MachineOperand::CreateImm(0); 1843 Result = pickVPHILoc(*MBB3, Var, VLiveOutIdx, MOutLocs, Preds); 1844 EXPECT_FALSE(Result); 1845 1846 // Seeing both to being a constant -> still prohibit, it shouldn't become 1847 // a value in the register file anywhere. 1848 VLiveOuts[2] = VLiveOuts[1]; 1849 Result = pickVPHILoc(*MBB3, Var, VLiveOutIdx, MOutLocs, Preds); 1850 EXPECT_FALSE(Result); 1851 1852 // NoVals shouldn't join with anything else. 1853 VLiveOuts[1] = DbgValue(LiveInRsp, EmptyProps, DbgValue::Def); 1854 VLiveOuts[2] = DbgValue(2, EmptyProps, DbgValue::NoVal); 1855 Result = pickVPHILoc(*MBB3, Var, VLiveOutIdx, MOutLocs, Preds); 1856 EXPECT_FALSE(Result); 1857 1858 // We might merge in another VPHI in such a join. Present pickVPHILoc with 1859 // such a scenario: first, where one incoming edge has a VPHI with no known 1860 // value. This represents an edge where there was a PHI value that can't be 1861 // found in the register file -- we can't subsequently find a PHI here. 1862 VLiveOuts[1] = DbgValue(LiveInRsp, EmptyProps, DbgValue::Def); 1863 VLiveOuts[2] = DbgValue(2, EmptyProps, DbgValue::VPHI); 1864 EXPECT_EQ(VLiveOuts[2].ID, ValueIDNum::EmptyValue); 1865 Result = pickVPHILoc(*MBB3, Var, VLiveOutIdx, MOutLocs, Preds); 1866 EXPECT_FALSE(Result); 1867 1868 // However, if we know the value of the incoming VPHI, we can search for its 1869 // location. Use a PHI machine-value for doing this, as VPHIs should always 1870 // have PHI values, or they should have been eliminated. 1871 MOutLocs[2][0] = RspPHIInBlk2; 1872 VLiveOuts[1] = DbgValue(LiveInRsp, EmptyProps, DbgValue::Def); 1873 VLiveOuts[2] = DbgValue(2, EmptyProps, DbgValue::VPHI); 1874 VLiveOuts[2].ID = RspPHIInBlk2; // Set location where PHI happens. 1875 Result = pickVPHILoc(*MBB3, Var, VLiveOutIdx, MOutLocs, Preds); 1876 EXPECT_TRUE(Result); 1877 if (Result) { 1878 EXPECT_EQ(*Result, RspPHIInBlk3); 1879 } 1880 1881 // If that value isn't available from that block, don't join. 1882 MOutLocs[2][0] = LiveInRsp; 1883 Result = pickVPHILoc(*MBB3, Var, VLiveOutIdx, MOutLocs, Preds); 1884 EXPECT_FALSE(Result); 1885 1886 // Check that we don't pick values when the properties disagree, for example 1887 // different indirectness or DIExpression. 1888 DIExpression *NewExpr = 1889 DIExpression::prepend(EmptyExpr, DIExpression::ApplyOffset, 4); 1890 DbgValueProperties PropsWithExpr(NewExpr, false); 1891 VLiveOuts[1] = DbgValue(LiveInRsp, EmptyProps, DbgValue::Def); 1892 VLiveOuts[2] = DbgValue(LiveInRsp, PropsWithExpr, DbgValue::Def); 1893 Result = pickVPHILoc(*MBB3, Var, VLiveOutIdx, MOutLocs, Preds); 1894 EXPECT_FALSE(Result); 1895 1896 DbgValueProperties PropsWithIndirect(EmptyExpr, true); 1897 VLiveOuts[1] = DbgValue(LiveInRsp, EmptyProps, DbgValue::Def); 1898 VLiveOuts[2] = DbgValue(LiveInRsp, PropsWithIndirect, DbgValue::Def); 1899 Result = pickVPHILoc(*MBB3, Var, VLiveOutIdx, MOutLocs, Preds); 1900 EXPECT_FALSE(Result); 1901 } 1902 1903 TEST_F(InstrRefLDVTest, pickVPHILocLoops) { 1904 setupSimpleLoop(); 1905 // entry 1906 // | 1907 // |/-----\ 1908 // loopblk | 1909 // |\-----/ 1910 // | 1911 // ret 1912 1913 ASSERT_TRUE(MTracker->getNumLocs() == 1); 1914 LocIdx RspLoc(0); 1915 Register RAX = getRegByName("RAX"); 1916 LocIdx RaxLoc = MTracker->lookupOrTrackRegister(RAX); 1917 1918 FuncValueTable MInLocs, MOutLocs; 1919 std::tie(MInLocs, MOutLocs) = allocValueTables(3, 2); 1920 1921 initValueArray(MOutLocs, 3, 2); 1922 1923 unsigned EntryBlk = 0, LoopBlk = 1; 1924 1925 ValueIDNum LiveInRsp(EntryBlk, 0, RspLoc); 1926 ValueIDNum LiveInRax(EntryBlk, 0, RaxLoc); 1927 ValueIDNum RspPHIInBlk1(LoopBlk, 0, RspLoc); 1928 ValueIDNum RaxPHIInBlk1(LoopBlk, 0, RaxLoc); 1929 1930 DebugVariable Var(FuncVariable, None, nullptr); 1931 DbgValueProperties EmptyProps(EmptyExpr, false); 1932 SmallVector<DbgValue, 32> VLiveOuts; 1933 VLiveOuts.resize(3, DbgValue(EmptyProps, DbgValue::Undef)); 1934 InstrRefBasedLDV::LiveIdxT VLiveOutIdx; 1935 VLiveOutIdx[MBB0] = &VLiveOuts[0]; 1936 VLiveOutIdx[MBB1] = &VLiveOuts[1]; 1937 VLiveOutIdx[MBB2] = &VLiveOuts[2]; 1938 1939 SmallVector<const MachineBasicBlock *, 2> Preds; 1940 for (const auto *Pred : MBB1->predecessors()) 1941 Preds.push_back(Pred); 1942 1943 // Specify the live-outs around the joining block. 1944 MOutLocs[0][0] = LiveInRsp; 1945 MOutLocs[1][0] = LiveInRax; 1946 1947 Optional<ValueIDNum> Result; 1948 1949 // See that we can merge as normal on a backedge. 1950 VLiveOuts[0] = DbgValue(LiveInRsp, EmptyProps, DbgValue::Def); 1951 VLiveOuts[1] = DbgValue(LiveInRax, EmptyProps, DbgValue::Def); 1952 Result = pickVPHILoc(*MBB1, Var, VLiveOutIdx, MOutLocs, Preds); 1953 // Should have picked a PHI in $rsp in block 1. 1954 EXPECT_TRUE(Result); 1955 if (Result) { 1956 EXPECT_EQ(*Result, RspPHIInBlk1); 1957 } 1958 1959 // And that, if the desired values aren't available, we don't merge. 1960 MOutLocs[1][0] = LiveInRsp; 1961 Result = pickVPHILoc(*MBB1, Var, VLiveOutIdx, MOutLocs, Preds); 1962 EXPECT_FALSE(Result); 1963 1964 // Test the backedge behaviour: PHIs that feed back into themselves can 1965 // carry this variables value. Feed in LiveInRsp in both $rsp and $rax 1966 // from the entry block, but only put an appropriate backedge PHI in $rax. 1967 // Only the $rax location can form the correct PHI. 1968 MOutLocs[0][0] = LiveInRsp; 1969 MOutLocs[0][1] = LiveInRsp; 1970 MOutLocs[1][0] = RaxPHIInBlk1; 1971 MOutLocs[1][1] = RaxPHIInBlk1; 1972 VLiveOuts[0] = DbgValue(LiveInRsp, EmptyProps, DbgValue::Def); 1973 // Crucially, a VPHI originating in this block: 1974 VLiveOuts[1] = DbgValue(1, EmptyProps, DbgValue::VPHI); 1975 Result = pickVPHILoc(*MBB1, Var, VLiveOutIdx, MOutLocs, Preds); 1976 EXPECT_TRUE(Result); 1977 if (Result) { 1978 EXPECT_EQ(*Result, RaxPHIInBlk1); 1979 } 1980 1981 // Merging should not be permitted if there's a usable PHI on the backedge, 1982 // but it's in the wrong place. (Overwrite $rax). 1983 MOutLocs[1][1] = LiveInRax; 1984 Result = pickVPHILoc(*MBB1, Var, VLiveOutIdx, MOutLocs, Preds); 1985 EXPECT_FALSE(Result); 1986 1987 // Additionally, if the VPHI coming back on the loop backedge isn't from 1988 // this block (block 1), we can't merge it. 1989 MOutLocs[1][1] = RaxPHIInBlk1; 1990 VLiveOuts[0] = DbgValue(LiveInRsp, EmptyProps, DbgValue::Def); 1991 VLiveOuts[1] = DbgValue(0, EmptyProps, DbgValue::VPHI); 1992 Result = pickVPHILoc(*MBB1, Var, VLiveOutIdx, MOutLocs, Preds); 1993 EXPECT_FALSE(Result); 1994 } 1995 1996 TEST_F(InstrRefLDVTest, pickVPHILocBadlyNestedLoops) { 1997 // Run some tests similar to pickVPHILocLoops, with more than one backedge, 1998 // and check that we merge correctly over many candidate locations. 1999 setupBadlyNestedLoops(); 2000 // entry 2001 // | 2002 // loop1 -o 2003 // | ^ 2004 // | ^ 2005 // loop2 -o 2006 // | ^ 2007 // | ^ 2008 // loop3 -o 2009 // | 2010 // ret 2011 ASSERT_TRUE(MTracker->getNumLocs() == 1); 2012 LocIdx RspLoc(0); 2013 Register RAX = getRegByName("RAX"); 2014 LocIdx RaxLoc = MTracker->lookupOrTrackRegister(RAX); 2015 Register RBX = getRegByName("RBX"); 2016 LocIdx RbxLoc = MTracker->lookupOrTrackRegister(RBX); 2017 2018 FuncValueTable MInLocs, MOutLocs; 2019 std::tie(MInLocs, MOutLocs) = allocValueTables(5, 3); 2020 2021 initValueArray(MOutLocs, 5, 3); 2022 2023 unsigned EntryBlk = 0, Loop1Blk = 1; 2024 2025 ValueIDNum LiveInRsp(EntryBlk, 0, RspLoc); 2026 ValueIDNum LiveInRax(EntryBlk, 0, RaxLoc); 2027 ValueIDNum LiveInRbx(EntryBlk, 0, RbxLoc); 2028 ValueIDNum RspPHIInBlk1(Loop1Blk, 0, RspLoc); 2029 ValueIDNum RaxPHIInBlk1(Loop1Blk, 0, RaxLoc); 2030 ValueIDNum RbxPHIInBlk1(Loop1Blk, 0, RbxLoc); 2031 2032 DebugVariable Var(FuncVariable, None, nullptr); 2033 DbgValueProperties EmptyProps(EmptyExpr, false); 2034 SmallVector<DbgValue, 32> VLiveOuts; 2035 VLiveOuts.resize(5, DbgValue(EmptyProps, DbgValue::Undef)); 2036 InstrRefBasedLDV::LiveIdxT VLiveOutIdx; 2037 VLiveOutIdx[MBB0] = &VLiveOuts[0]; 2038 VLiveOutIdx[MBB1] = &VLiveOuts[1]; 2039 VLiveOutIdx[MBB2] = &VLiveOuts[2]; 2040 VLiveOutIdx[MBB3] = &VLiveOuts[3]; 2041 VLiveOutIdx[MBB4] = &VLiveOuts[4]; 2042 2043 // We're going to focus on block 1. 2044 SmallVector<const MachineBasicBlock *, 2> Preds; 2045 for (const auto *Pred : MBB1->predecessors()) 2046 Preds.push_back(Pred); 2047 2048 // Specify the live-outs around the joining block. Incoming edges from the 2049 // entry block, self, and loop2. 2050 MOutLocs[0][0] = LiveInRsp; 2051 MOutLocs[1][0] = LiveInRax; 2052 MOutLocs[2][0] = LiveInRbx; 2053 2054 Optional<ValueIDNum> Result; 2055 2056 // See that we can merge as normal on a backedge. 2057 VLiveOuts[0] = DbgValue(LiveInRsp, EmptyProps, DbgValue::Def); 2058 VLiveOuts[1] = DbgValue(LiveInRax, EmptyProps, DbgValue::Def); 2059 VLiveOuts[2] = DbgValue(LiveInRbx, EmptyProps, DbgValue::Def); 2060 Result = pickVPHILoc(*MBB1, Var, VLiveOutIdx, MOutLocs, Preds); 2061 // Should have picked a PHI in $rsp in block 1. 2062 EXPECT_TRUE(Result); 2063 if (Result) { 2064 EXPECT_EQ(*Result, RspPHIInBlk1); 2065 } 2066 2067 // Check too that permuting the live-out locations prevents merging 2068 MOutLocs[0][0] = LiveInRax; 2069 MOutLocs[1][0] = LiveInRbx; 2070 MOutLocs[2][0] = LiveInRsp; 2071 Result = pickVPHILoc(*MBB1, Var, VLiveOutIdx, MOutLocs, Preds); 2072 EXPECT_FALSE(Result); 2073 2074 MOutLocs[0][0] = LiveInRsp; 2075 MOutLocs[1][0] = LiveInRax; 2076 MOutLocs[2][0] = LiveInRbx; 2077 2078 // Feeding a PHI back on one backedge shouldn't merge (block 1 self backedge 2079 // wants LiveInRax). 2080 MOutLocs[1][0] = RspPHIInBlk1; 2081 Result = pickVPHILoc(*MBB1, Var, VLiveOutIdx, MOutLocs, Preds); 2082 EXPECT_FALSE(Result); 2083 2084 // If the variables value on that edge is a VPHI feeding into itself, that's 2085 // fine. 2086 VLiveOuts[0] = DbgValue(LiveInRsp, EmptyProps, DbgValue::Def); 2087 VLiveOuts[1] = DbgValue(1, EmptyProps, DbgValue::VPHI); 2088 VLiveOuts[2] = DbgValue(LiveInRbx, EmptyProps, DbgValue::Def); 2089 Result = pickVPHILoc(*MBB1, Var, VLiveOutIdx, MOutLocs, Preds); 2090 EXPECT_TRUE(Result); 2091 if (Result) { 2092 EXPECT_EQ(*Result, RspPHIInBlk1); 2093 } 2094 2095 // Likewise: the other backedge being a VPHI from block 1 should be accepted. 2096 MOutLocs[2][0] = RspPHIInBlk1; 2097 VLiveOuts[0] = DbgValue(LiveInRsp, EmptyProps, DbgValue::Def); 2098 VLiveOuts[1] = DbgValue(1, EmptyProps, DbgValue::VPHI); 2099 VLiveOuts[2] = DbgValue(1, EmptyProps, DbgValue::VPHI); 2100 Result = pickVPHILoc(*MBB1, Var, VLiveOutIdx, MOutLocs, Preds); 2101 EXPECT_TRUE(Result); 2102 if (Result) { 2103 EXPECT_EQ(*Result, RspPHIInBlk1); 2104 } 2105 2106 // Here's where it becomes tricky: we should not merge if there are two 2107 // _distinct_ backedge PHIs. We can't have a PHI that happens in both rsp 2108 // and rax for example. We can only pick one location as the live-in. 2109 MOutLocs[2][0] = RaxPHIInBlk1; 2110 Result = pickVPHILoc(*MBB1, Var, VLiveOutIdx, MOutLocs, Preds); 2111 EXPECT_FALSE(Result); 2112 2113 // The above test sources correct machine-PHI-value from two places. Now 2114 // try with one machine-PHI-value, but placed in two different locations 2115 // on the backedge. Again, we can't merge a location here, there's no 2116 // location that works on all paths. 2117 MOutLocs[0][0] = LiveInRsp; 2118 MOutLocs[1][0] = RspPHIInBlk1; 2119 MOutLocs[2][0] = LiveInRsp; 2120 MOutLocs[2][1] = RspPHIInBlk1; 2121 Result = pickVPHILoc(*MBB1, Var, VLiveOutIdx, MOutLocs, Preds); 2122 EXPECT_FALSE(Result); 2123 2124 // Scatter various PHI values across the available locations. Only rbx (loc 2) 2125 // has the right value in both backedges -- that's the loc that should be 2126 // picked. 2127 MOutLocs[0][2] = LiveInRsp; 2128 MOutLocs[1][0] = RspPHIInBlk1; 2129 MOutLocs[1][1] = RaxPHIInBlk1; 2130 MOutLocs[1][2] = RbxPHIInBlk1; 2131 MOutLocs[2][0] = LiveInRsp; 2132 MOutLocs[2][1] = RspPHIInBlk1; 2133 MOutLocs[2][2] = RbxPHIInBlk1; 2134 Result = pickVPHILoc(*MBB1, Var, VLiveOutIdx, MOutLocs, Preds); 2135 EXPECT_TRUE(Result); 2136 if (Result) { 2137 EXPECT_EQ(*Result, RbxPHIInBlk1); 2138 } 2139 } 2140 2141 TEST_F(InstrRefLDVTest, vlocJoinDiamond) { 2142 // entry 2143 // / \ 2144 // br1 br2 2145 // \ / 2146 // ret 2147 setupDiamondBlocks(); 2148 2149 ASSERT_TRUE(MTracker->getNumLocs() == 1); 2150 LocIdx RspLoc(0); 2151 Register RAX = getRegByName("RAX"); 2152 LocIdx RaxLoc = MTracker->lookupOrTrackRegister(RAX); 2153 2154 unsigned EntryBlk = 0, Br2Blk = 2, RetBlk = 3; 2155 2156 ValueIDNum LiveInRsp(EntryBlk, 0, RspLoc); 2157 ValueIDNum LiveInRax(EntryBlk, 0, RaxLoc); 2158 ValueIDNum RspPHIInBlkBr2Blk(Br2Blk, 0, RspLoc); 2159 ValueIDNum RspPHIInBlkRetBlk(RetBlk, 0, RspLoc); 2160 2161 DebugVariable Var(FuncVariable, None, nullptr); 2162 DbgValueProperties EmptyProps(EmptyExpr, false); 2163 SmallVector<DbgValue, 32> VLiveOuts; 2164 VLiveOuts.resize(4, DbgValue(EmptyProps, DbgValue::Undef)); 2165 InstrRefBasedLDV::LiveIdxT VLiveOutIdx; 2166 VLiveOutIdx[MBB0] = &VLiveOuts[0]; 2167 VLiveOutIdx[MBB1] = &VLiveOuts[1]; 2168 VLiveOutIdx[MBB2] = &VLiveOuts[2]; 2169 VLiveOutIdx[MBB3] = &VLiveOuts[3]; 2170 2171 SmallPtrSet<const MachineBasicBlock *, 8> AllBlocks; 2172 AllBlocks.insert(MBB0); 2173 AllBlocks.insert(MBB1); 2174 AllBlocks.insert(MBB2); 2175 AllBlocks.insert(MBB3); 2176 2177 SmallVector<const MachineBasicBlock *, 2> Preds; 2178 for (const auto *Pred : MBB3->predecessors()) 2179 Preds.push_back(Pred); 2180 2181 SmallSet<DebugVariable, 4> AllVars; 2182 AllVars.insert(Var); 2183 2184 // vlocJoin is here to propagate incoming values, and eliminate PHIs. Start 2185 // off by propagating a value into the merging block, number 3. 2186 DbgValue JoinedLoc = DbgValue(3, EmptyProps, DbgValue::NoVal); 2187 VLiveOuts[1] = DbgValue(LiveInRsp, EmptyProps, DbgValue::Def); 2188 VLiveOuts[2] = DbgValue(LiveInRsp, EmptyProps, DbgValue::Def); 2189 bool Result = vlocJoin(*MBB3, VLiveOutIdx, AllBlocks, JoinedLoc); 2190 EXPECT_TRUE(Result); // Output locs should have changed. 2191 EXPECT_EQ(JoinedLoc.Kind, DbgValue::Def); 2192 EXPECT_EQ(JoinedLoc.ID, LiveInRsp); 2193 2194 // And if we did it a second time, leaving the live-ins as it was, then 2195 // we should report no change. 2196 Result = vlocJoin(*MBB3, VLiveOutIdx, AllBlocks, JoinedLoc); 2197 EXPECT_FALSE(Result); 2198 2199 // If the live-in variable values are different, but there's no PHI placed 2200 // in this block, then just pick a location. It should be the first (in RPO) 2201 // predecessor to avoid being a backedge. 2202 VLiveOuts[1] = DbgValue(LiveInRsp, EmptyProps, DbgValue::Def); 2203 VLiveOuts[2] = DbgValue(LiveInRax, EmptyProps, DbgValue::Def); 2204 JoinedLoc = DbgValue(3, EmptyProps, DbgValue::NoVal); 2205 Result = vlocJoin(*MBB3, VLiveOutIdx, AllBlocks, JoinedLoc); 2206 EXPECT_TRUE(Result); 2207 EXPECT_EQ(JoinedLoc.Kind, DbgValue::Def); 2208 // RPO is blocks 0 2 1 3, so LiveInRax is picked as the first predecessor 2209 // of this join. 2210 EXPECT_EQ(JoinedLoc.ID, LiveInRax); 2211 2212 // No tests for whether vlocJoin will pass-through a variable with differing 2213 // expressions / properties. Those can only come about due to assignments; and 2214 // for any assignment at all, a PHI should have been placed at the dominance 2215 // frontier. We rely on the IDF calculator being accurate (which is OK, 2216 // because so does the rest of LLVM). 2217 2218 // Try placing a PHI. With differing input values (LiveInRsp, LiveInRax), 2219 // this PHI should not be eliminated. 2220 JoinedLoc = DbgValue(3, EmptyProps, DbgValue::VPHI); 2221 Result = vlocJoin(*MBB3, VLiveOutIdx, AllBlocks, JoinedLoc); 2222 // Expect no change. 2223 EXPECT_FALSE(Result); 2224 EXPECT_EQ(JoinedLoc.Kind, DbgValue::VPHI); 2225 // This should not have been assigned a fixed value. 2226 EXPECT_EQ(JoinedLoc.ID, ValueIDNum::EmptyValue); 2227 EXPECT_EQ(JoinedLoc.BlockNo, 3); 2228 2229 // Try a simple PHI elimination. Put a PHI in block 3, but LiveInRsp on both 2230 // incoming edges. Re-load in and out-locs with unrelated values; they're 2231 // irrelevant. 2232 VLiveOuts[1] = DbgValue(LiveInRsp, EmptyProps, DbgValue::Def); 2233 VLiveOuts[2] = DbgValue(LiveInRsp, EmptyProps, DbgValue::Def); 2234 JoinedLoc = DbgValue(3, EmptyProps, DbgValue::VPHI); 2235 Result = vlocJoin(*MBB3, VLiveOutIdx, AllBlocks, JoinedLoc); 2236 EXPECT_TRUE(Result); 2237 EXPECT_EQ(JoinedLoc.Kind, DbgValue::Def); 2238 EXPECT_EQ(JoinedLoc.ID, LiveInRsp); 2239 2240 // If the "current" live-in is a VPHI, but not a VPHI generated in the current 2241 // block, then it's the remains of an earlier value propagation. We should 2242 // value propagate through this merge. Even if the current incoming values 2243 // disagree, because we've previously determined any VPHI here is redundant. 2244 VLiveOuts[1] = DbgValue(LiveInRsp, EmptyProps, DbgValue::Def); 2245 VLiveOuts[2] = DbgValue(LiveInRax, EmptyProps, DbgValue::Def); 2246 JoinedLoc = DbgValue(2, EmptyProps, DbgValue::VPHI); 2247 Result = vlocJoin(*MBB3, VLiveOutIdx, AllBlocks, JoinedLoc); 2248 EXPECT_TRUE(Result); 2249 EXPECT_EQ(JoinedLoc.Kind, DbgValue::Def); 2250 EXPECT_EQ(JoinedLoc.ID, LiveInRax); // from block 2 2251 2252 // The above test, but test that we will install one value-propagated VPHI 2253 // over another. 2254 VLiveOuts[1] = DbgValue(LiveInRsp, EmptyProps, DbgValue::Def); 2255 VLiveOuts[2] = DbgValue(0, EmptyProps, DbgValue::VPHI); 2256 JoinedLoc = DbgValue(2, EmptyProps, DbgValue::VPHI); 2257 Result = vlocJoin(*MBB3, VLiveOutIdx, AllBlocks, JoinedLoc); 2258 EXPECT_TRUE(Result); 2259 EXPECT_EQ(JoinedLoc.Kind, DbgValue::VPHI); 2260 EXPECT_EQ(JoinedLoc.BlockNo, 0); 2261 2262 // We shouldn't eliminate PHIs when properties disagree. 2263 DbgValueProperties PropsWithIndirect(EmptyExpr, true); 2264 VLiveOuts[1] = DbgValue(LiveInRsp, EmptyProps, DbgValue::Def); 2265 VLiveOuts[2] = DbgValue(LiveInRsp, PropsWithIndirect, DbgValue::Def); 2266 JoinedLoc = DbgValue(3, EmptyProps, DbgValue::VPHI); 2267 Result = vlocJoin(*MBB3, VLiveOutIdx, AllBlocks, JoinedLoc); 2268 EXPECT_FALSE(Result); 2269 EXPECT_EQ(JoinedLoc.Kind, DbgValue::VPHI); 2270 EXPECT_EQ(JoinedLoc.BlockNo, 3); 2271 2272 // Even if properties disagree, we should still value-propagate if there's no 2273 // PHI to be eliminated. The disagreeing values should work themselves out, 2274 // seeing how we've determined no PHI is necessary. 2275 VLiveOuts[1] = DbgValue(LiveInRsp, EmptyProps, DbgValue::Def); 2276 VLiveOuts[2] = DbgValue(LiveInRsp, PropsWithIndirect, DbgValue::Def); 2277 JoinedLoc = DbgValue(2, EmptyProps, DbgValue::VPHI); 2278 Result = vlocJoin(*MBB3, VLiveOutIdx, AllBlocks, JoinedLoc); 2279 EXPECT_TRUE(Result); 2280 EXPECT_EQ(JoinedLoc.Kind, DbgValue::Def); 2281 EXPECT_EQ(JoinedLoc.ID, LiveInRsp); 2282 // Also check properties come from block 2, the first RPO predecessor to block 2283 // three. 2284 EXPECT_EQ(JoinedLoc.Properties, PropsWithIndirect); 2285 2286 // Again, disagreeing properties, this time the expr, should cause a PHI to 2287 // not be eliminated. 2288 DIExpression *NewExpr = 2289 DIExpression::prepend(EmptyExpr, DIExpression::ApplyOffset, 4); 2290 DbgValueProperties PropsWithExpr(NewExpr, false); 2291 VLiveOuts[1] = DbgValue(LiveInRsp, EmptyProps, DbgValue::Def); 2292 VLiveOuts[2] = DbgValue(LiveInRsp, PropsWithExpr, DbgValue::Def); 2293 JoinedLoc = DbgValue(3, EmptyProps, DbgValue::VPHI); 2294 Result = vlocJoin(*MBB3, VLiveOutIdx, AllBlocks, JoinedLoc); 2295 EXPECT_FALSE(Result); 2296 } 2297 2298 TEST_F(InstrRefLDVTest, vlocJoinLoops) { 2299 setupSimpleLoop(); 2300 // entry 2301 // | 2302 // |/-----\ 2303 // loopblk | 2304 // |\-----/ 2305 // | 2306 // ret 2307 ASSERT_TRUE(MTracker->getNumLocs() == 1); 2308 LocIdx RspLoc(0); 2309 Register RAX = getRegByName("RAX"); 2310 LocIdx RaxLoc = MTracker->lookupOrTrackRegister(RAX); 2311 2312 unsigned EntryBlk = 0, LoopBlk = 1; 2313 2314 ValueIDNum LiveInRsp(EntryBlk, 0, RspLoc); 2315 ValueIDNum LiveInRax(EntryBlk, 0, RaxLoc); 2316 ValueIDNum RspPHIInBlk1(LoopBlk, 0, RspLoc); 2317 2318 DebugVariable Var(FuncVariable, None, nullptr); 2319 DbgValueProperties EmptyProps(EmptyExpr, false); 2320 SmallVector<DbgValue, 32> VLiveOuts; 2321 VLiveOuts.resize(3, DbgValue(EmptyProps, DbgValue::Undef)); 2322 InstrRefBasedLDV::LiveIdxT VLiveOutIdx; 2323 VLiveOutIdx[MBB0] = &VLiveOuts[0]; 2324 VLiveOutIdx[MBB1] = &VLiveOuts[1]; 2325 VLiveOutIdx[MBB2] = &VLiveOuts[2]; 2326 2327 SmallPtrSet<const MachineBasicBlock *, 8> AllBlocks; 2328 AllBlocks.insert(MBB0); 2329 AllBlocks.insert(MBB1); 2330 AllBlocks.insert(MBB2); 2331 2332 SmallVector<const MachineBasicBlock *, 2> Preds; 2333 for (const auto *Pred : MBB1->predecessors()) 2334 Preds.push_back(Pred); 2335 2336 SmallSet<DebugVariable, 4> AllVars; 2337 AllVars.insert(Var); 2338 2339 // Test some back-edge-specific behaviours of vloc join. Mostly: the fact that 2340 // VPHIs that arrive on backedges can be eliminated, despite having different 2341 // values to the predecessor. 2342 2343 // First: when there's no VPHI placed already, propagate the live-in value of 2344 // the first RPO predecessor. 2345 VLiveOuts[0] = DbgValue(LiveInRsp, EmptyProps, DbgValue::Def); 2346 VLiveOuts[1] = DbgValue(LiveInRax, EmptyProps, DbgValue::Def); 2347 DbgValue JoinedLoc = DbgValue(LiveInRax, EmptyProps, DbgValue::Def); 2348 bool Result = vlocJoin(*MBB1, VLiveOutIdx, AllBlocks, JoinedLoc); 2349 EXPECT_TRUE(Result); 2350 EXPECT_EQ(JoinedLoc.Kind, DbgValue::Def); 2351 EXPECT_EQ(JoinedLoc.ID, LiveInRsp); 2352 2353 // If there is a VPHI: don't elimiante it if there are disagreeing values. 2354 VLiveOuts[0] = DbgValue(LiveInRsp, EmptyProps, DbgValue::Def); 2355 VLiveOuts[1] = DbgValue(LiveInRax, EmptyProps, DbgValue::Def); 2356 JoinedLoc = DbgValue(1, EmptyProps, DbgValue::VPHI); 2357 Result = vlocJoin(*MBB1, VLiveOutIdx, AllBlocks, JoinedLoc); 2358 EXPECT_FALSE(Result); 2359 EXPECT_EQ(JoinedLoc.Kind, DbgValue::VPHI); 2360 EXPECT_EQ(JoinedLoc.BlockNo, 1); 2361 2362 // If we feed this VPHI back into itself though, we can eliminate it. 2363 VLiveOuts[0] = DbgValue(LiveInRsp, EmptyProps, DbgValue::Def); 2364 VLiveOuts[1] = DbgValue(1, EmptyProps, DbgValue::VPHI); 2365 JoinedLoc = DbgValue(1, EmptyProps, DbgValue::VPHI); 2366 Result = vlocJoin(*MBB1, VLiveOutIdx, AllBlocks, JoinedLoc); 2367 EXPECT_TRUE(Result); 2368 EXPECT_EQ(JoinedLoc.Kind, DbgValue::Def); 2369 EXPECT_EQ(JoinedLoc.ID, LiveInRsp); 2370 2371 // Don't eliminate backedge VPHIs if the predecessors have different 2372 // properties. 2373 DIExpression *NewExpr = 2374 DIExpression::prepend(EmptyExpr, DIExpression::ApplyOffset, 4); 2375 DbgValueProperties PropsWithExpr(NewExpr, false); 2376 VLiveOuts[0] = DbgValue(LiveInRsp, EmptyProps, DbgValue::Def); 2377 VLiveOuts[1] = DbgValue(1, PropsWithExpr, DbgValue::VPHI); 2378 JoinedLoc = DbgValue(1, EmptyProps, DbgValue::VPHI); 2379 Result = vlocJoin(*MBB1, VLiveOutIdx, AllBlocks, JoinedLoc); 2380 EXPECT_FALSE(Result); 2381 EXPECT_EQ(JoinedLoc.Kind, DbgValue::VPHI); 2382 EXPECT_EQ(JoinedLoc.BlockNo, 1); 2383 2384 // Backedges with VPHIs, but from the wrong block, shouldn't be eliminated. 2385 VLiveOuts[0] = DbgValue(LiveInRsp, EmptyProps, DbgValue::Def); 2386 VLiveOuts[1] = DbgValue(0, EmptyProps, DbgValue::VPHI); 2387 JoinedLoc = DbgValue(1, EmptyProps, DbgValue::VPHI); 2388 Result = vlocJoin(*MBB1, VLiveOutIdx, AllBlocks, JoinedLoc); 2389 EXPECT_FALSE(Result); 2390 EXPECT_EQ(JoinedLoc.Kind, DbgValue::VPHI); 2391 EXPECT_EQ(JoinedLoc.BlockNo, 1); 2392 } 2393 2394 TEST_F(InstrRefLDVTest, vlocJoinBadlyNestedLoops) { 2395 // Test PHI elimination in the presence of multiple backedges. 2396 setupBadlyNestedLoops(); 2397 // entry 2398 // | 2399 // loop1 -o 2400 // | ^ 2401 // | ^ 2402 // loop2 -o 2403 // | ^ 2404 // | ^ 2405 // loop3 -o 2406 // | 2407 // ret 2408 ASSERT_TRUE(MTracker->getNumLocs() == 1); 2409 LocIdx RspLoc(0); 2410 Register RAX = getRegByName("RAX"); 2411 LocIdx RaxLoc = MTracker->lookupOrTrackRegister(RAX); 2412 Register RBX = getRegByName("RBX"); 2413 LocIdx RbxLoc = MTracker->lookupOrTrackRegister(RBX); 2414 2415 unsigned EntryBlk = 0; 2416 2417 ValueIDNum LiveInRsp(EntryBlk, 0, RspLoc); 2418 ValueIDNum LiveInRax(EntryBlk, 0, RaxLoc); 2419 ValueIDNum LiveInRbx(EntryBlk, 0, RbxLoc); 2420 2421 DebugVariable Var(FuncVariable, None, nullptr); 2422 DbgValueProperties EmptyProps(EmptyExpr, false); 2423 SmallVector<DbgValue, 32> VLiveOuts; 2424 VLiveOuts.resize(5, DbgValue(EmptyProps, DbgValue::Undef)); 2425 InstrRefBasedLDV::LiveIdxT VLiveOutIdx; 2426 VLiveOutIdx[MBB0] = &VLiveOuts[0]; 2427 VLiveOutIdx[MBB1] = &VLiveOuts[1]; 2428 VLiveOutIdx[MBB2] = &VLiveOuts[2]; 2429 VLiveOutIdx[MBB3] = &VLiveOuts[3]; 2430 VLiveOutIdx[MBB4] = &VLiveOuts[4]; 2431 2432 SmallPtrSet<const MachineBasicBlock *, 8> AllBlocks; 2433 AllBlocks.insert(MBB0); 2434 AllBlocks.insert(MBB1); 2435 AllBlocks.insert(MBB2); 2436 AllBlocks.insert(MBB3); 2437 AllBlocks.insert(MBB4); 2438 2439 // We're going to focus on block 1. 2440 SmallVector<const MachineBasicBlock *, 3> Preds; 2441 for (const auto *Pred : MBB1->predecessors()) 2442 Preds.push_back(Pred); 2443 2444 SmallSet<DebugVariable, 4> AllVars; 2445 AllVars.insert(Var); 2446 2447 // Test a normal VPHI isn't eliminated. 2448 VLiveOuts[0] = DbgValue(LiveInRsp, EmptyProps, DbgValue::Def); 2449 VLiveOuts[1] = DbgValue(LiveInRax, EmptyProps, DbgValue::Def); 2450 VLiveOuts[2] = DbgValue(LiveInRbx, EmptyProps, DbgValue::Def); 2451 DbgValue JoinedLoc = DbgValue(1, EmptyProps, DbgValue::VPHI); 2452 bool Result = vlocJoin(*MBB1, VLiveOutIdx, AllBlocks, JoinedLoc); 2453 EXPECT_FALSE(Result); 2454 EXPECT_EQ(JoinedLoc.Kind, DbgValue::VPHI); 2455 EXPECT_EQ(JoinedLoc.BlockNo, 1); 2456 2457 // Common VPHIs on backedges should merge. 2458 VLiveOuts[0] = DbgValue(LiveInRsp, EmptyProps, DbgValue::Def); 2459 VLiveOuts[1] = DbgValue(1, EmptyProps, DbgValue::VPHI); 2460 VLiveOuts[2] = DbgValue(1, EmptyProps, DbgValue::VPHI); 2461 JoinedLoc = DbgValue(1, EmptyProps, DbgValue::VPHI); 2462 Result = vlocJoin(*MBB1, VLiveOutIdx, AllBlocks, JoinedLoc); 2463 EXPECT_TRUE(Result); 2464 EXPECT_EQ(JoinedLoc.Kind, DbgValue::Def); 2465 EXPECT_EQ(JoinedLoc.ID, LiveInRsp); 2466 2467 // They shouldn't merge if one of their properties is different. 2468 DbgValueProperties PropsWithIndirect(EmptyExpr, true); 2469 VLiveOuts[0] = DbgValue(LiveInRsp, EmptyProps, DbgValue::Def); 2470 VLiveOuts[1] = DbgValue(1, EmptyProps, DbgValue::VPHI); 2471 VLiveOuts[2] = DbgValue(1, PropsWithIndirect, DbgValue::VPHI); 2472 JoinedLoc = DbgValue(1, EmptyProps, DbgValue::VPHI); 2473 Result = vlocJoin(*MBB1, VLiveOutIdx, AllBlocks, JoinedLoc); 2474 EXPECT_FALSE(Result); 2475 EXPECT_EQ(JoinedLoc.Kind, DbgValue::VPHI); 2476 EXPECT_EQ(JoinedLoc.BlockNo, 1); 2477 2478 // VPHIs from different blocks should not merge. 2479 VLiveOuts[0] = DbgValue(LiveInRsp, EmptyProps, DbgValue::Def); 2480 VLiveOuts[1] = DbgValue(1, EmptyProps, DbgValue::VPHI); 2481 VLiveOuts[2] = DbgValue(2, EmptyProps, DbgValue::VPHI); 2482 JoinedLoc = DbgValue(1, EmptyProps, DbgValue::VPHI); 2483 Result = vlocJoin(*MBB1, VLiveOutIdx, AllBlocks, JoinedLoc); 2484 EXPECT_FALSE(Result); 2485 EXPECT_EQ(JoinedLoc.Kind, DbgValue::VPHI); 2486 EXPECT_EQ(JoinedLoc.BlockNo, 1); 2487 } 2488 2489 // Above are tests for picking VPHI locations, and eliminating VPHIs. No 2490 // unit-tests are written for evaluating the transfer function as that's 2491 // pretty straight forwards, or applying VPHI-location-picking to live-ins. 2492 // Instead, pre-set some machine locations and apply buildVLocValueMap to the 2493 // existing CFG patterns. 2494 TEST_F(InstrRefLDVTest, VLocSingleBlock) { 2495 setupSingleBlock(); 2496 2497 ASSERT_TRUE(MTracker->getNumLocs() == 1); 2498 LocIdx RspLoc(0); 2499 2500 FuncValueTable MInLocs, MOutLocs; 2501 std::tie(MInLocs, MOutLocs) = allocValueTables(1, 2); 2502 2503 ValueIDNum LiveInRsp = ValueIDNum(0, 0, RspLoc); 2504 MInLocs[0][0] = MOutLocs[0][0] = LiveInRsp; 2505 2506 DebugVariable Var(FuncVariable, None, nullptr); 2507 DbgValueProperties EmptyProps(EmptyExpr, false); 2508 2509 SmallSet<DebugVariable, 4> AllVars; 2510 AllVars.insert(Var); 2511 2512 // Mild hack: rather than constructing machine instructions in each block 2513 // and creating lexical scopes across them, instead just tell 2514 // buildVLocValueMap that there's an assignment in every block. That makes 2515 // every block in scope. 2516 SmallPtrSet<MachineBasicBlock *, 4> AssignBlocks; 2517 AssignBlocks.insert(MBB0); 2518 2519 SmallVector<VLocTracker, 1> VLocs; 2520 VLocs.resize(1, VLocTracker(Overlaps, EmptyExpr)); 2521 2522 InstrRefBasedLDV::LiveInsT Output; 2523 2524 // Test that, with no assignments at all, no mappings are created for the 2525 // variable in this function. 2526 buildVLocValueMap(OutermostLoc, AllVars, AssignBlocks, Output, 2527 MOutLocs, MInLocs, VLocs); 2528 EXPECT_EQ(Output.size(), 0ul); 2529 2530 // If we put an assignment in the transfer function, that should... well, 2531 // do nothing, because we don't store the live-outs. 2532 VLocs[0].Vars.insert({Var, DbgValue(LiveInRsp, EmptyProps, DbgValue::Def)}); 2533 buildVLocValueMap(OutermostLoc, AllVars, AssignBlocks, Output, 2534 MOutLocs, MInLocs, VLocs); 2535 EXPECT_EQ(Output.size(), 0ul); 2536 2537 // There is pretty much nothing else of interest to test with a single block. 2538 // It's not relevant to the SSA-construction parts of variable values. 2539 } 2540 2541 TEST_F(InstrRefLDVTest, VLocDiamondBlocks) { 2542 setupDiamondBlocks(); 2543 // entry 2544 // / \ 2545 // br1 br2 2546 // \ / 2547 // ret 2548 2549 ASSERT_TRUE(MTracker->getNumLocs() == 1); 2550 LocIdx RspLoc(0); 2551 Register RAX = getRegByName("RAX"); 2552 LocIdx RaxLoc = MTracker->lookupOrTrackRegister(RAX); 2553 2554 unsigned EntryBlk = 0, RetBlk = 3; 2555 2556 ValueIDNum LiveInRsp = ValueIDNum(EntryBlk, 0, RspLoc); 2557 ValueIDNum LiveInRax = ValueIDNum(EntryBlk, 0, RaxLoc); 2558 ValueIDNum RspPHIInBlk3 = ValueIDNum(RetBlk, 0, RspLoc); 2559 2560 FuncValueTable MInLocs, MOutLocs; 2561 std::tie(MInLocs, MOutLocs) = allocValueTables(4, 2); 2562 2563 initValueArray(MInLocs, 4, 2); 2564 initValueArray(MOutLocs, 4, 2); 2565 2566 DebugVariable Var(FuncVariable, None, nullptr); 2567 DbgValueProperties EmptyProps(EmptyExpr, false); 2568 2569 SmallSet<DebugVariable, 4> AllVars; 2570 AllVars.insert(Var); 2571 2572 // Mild hack: rather than constructing machine instructions in each block 2573 // and creating lexical scopes across them, instead just tell 2574 // buildVLocValueMap that there's an assignment in every block. That makes 2575 // every block in scope. 2576 SmallPtrSet<MachineBasicBlock *, 4> AssignBlocks; 2577 AssignBlocks.insert(MBB0); 2578 AssignBlocks.insert(MBB1); 2579 AssignBlocks.insert(MBB2); 2580 AssignBlocks.insert(MBB3); 2581 2582 SmallVector<VLocTracker, 1> VLocs; 2583 VLocs.resize(4, VLocTracker(Overlaps, EmptyExpr)); 2584 2585 InstrRefBasedLDV::LiveInsT Output; 2586 2587 // Start off with LiveInRsp in every location. 2588 for (unsigned int I = 0; I < 4; ++I) { 2589 MInLocs[I][0] = MInLocs[I][1] = LiveInRsp; 2590 MOutLocs[I][0] = MOutLocs[I][1] = LiveInRsp; 2591 } 2592 2593 auto ClearOutputs = [&]() { 2594 for (auto &Elem : Output) 2595 Elem.clear(); 2596 }; 2597 Output.resize(4); 2598 2599 // No assignments -> no values. 2600 buildVLocValueMap(OutermostLoc, AllVars, AssignBlocks, Output, 2601 MOutLocs, MInLocs, VLocs); 2602 EXPECT_EQ(Output[0].size(), 0ul); 2603 EXPECT_EQ(Output[1].size(), 0ul); 2604 EXPECT_EQ(Output[2].size(), 0ul); 2605 EXPECT_EQ(Output[3].size(), 0ul); 2606 2607 // An assignment in the end block should also not affect other blocks; or 2608 // produce any live-ins. 2609 VLocs[3].Vars.insert({Var, DbgValue(LiveInRsp, EmptyProps, DbgValue::Def)}); 2610 buildVLocValueMap(OutermostLoc, AllVars, AssignBlocks, Output, 2611 MOutLocs, MInLocs, VLocs); 2612 EXPECT_EQ(Output[0].size(), 0ul); 2613 EXPECT_EQ(Output[1].size(), 0ul); 2614 EXPECT_EQ(Output[2].size(), 0ul); 2615 EXPECT_EQ(Output[3].size(), 0ul); 2616 ClearOutputs(); 2617 2618 // Assignments in either of the side-of-diamond blocks should also not be 2619 // propagated anywhere. 2620 VLocs[3].Vars.clear(); 2621 VLocs[2].Vars.insert({Var, DbgValue(LiveInRsp, EmptyProps, DbgValue::Def)}); 2622 buildVLocValueMap(OutermostLoc, AllVars, AssignBlocks, Output, 2623 MOutLocs, MInLocs, VLocs); 2624 EXPECT_EQ(Output[0].size(), 0ul); 2625 EXPECT_EQ(Output[1].size(), 0ul); 2626 EXPECT_EQ(Output[2].size(), 0ul); 2627 EXPECT_EQ(Output[3].size(), 0ul); 2628 VLocs[2].Vars.clear(); 2629 ClearOutputs(); 2630 2631 VLocs[1].Vars.insert({Var, DbgValue(LiveInRsp, EmptyProps, DbgValue::Def)}); 2632 buildVLocValueMap(OutermostLoc, AllVars, AssignBlocks, Output, 2633 MOutLocs, MInLocs, VLocs); 2634 EXPECT_EQ(Output[0].size(), 0ul); 2635 EXPECT_EQ(Output[1].size(), 0ul); 2636 EXPECT_EQ(Output[2].size(), 0ul); 2637 EXPECT_EQ(Output[3].size(), 0ul); 2638 VLocs[1].Vars.clear(); 2639 ClearOutputs(); 2640 2641 // However: putting an assignment in the first block should propagate variable 2642 // values through to all other blocks, as it dominates. 2643 VLocs[0].Vars.insert({Var, DbgValue(LiveInRsp, EmptyProps, DbgValue::Def)}); 2644 buildVLocValueMap(OutermostLoc, AllVars, AssignBlocks, Output, 2645 MOutLocs, MInLocs, VLocs); 2646 EXPECT_EQ(Output[0].size(), 0ul); 2647 ASSERT_EQ(Output[1].size(), 1ul); 2648 ASSERT_EQ(Output[2].size(), 1ul); 2649 ASSERT_EQ(Output[3].size(), 1ul); 2650 EXPECT_EQ(Output[1][0].second.Kind, DbgValue::Def); 2651 EXPECT_EQ(Output[1][0].second.ID, LiveInRsp); 2652 EXPECT_EQ(Output[2][0].second.Kind, DbgValue::Def); 2653 EXPECT_EQ(Output[2][0].second.ID, LiveInRsp); 2654 EXPECT_EQ(Output[3][0].second.Kind, DbgValue::Def); 2655 EXPECT_EQ(Output[3][0].second.ID, LiveInRsp); 2656 ClearOutputs(); 2657 VLocs[0].Vars.clear(); 2658 2659 // Additionally, even if that value isn't available in the register file, it 2660 // should still be propagated, as buildVLocValueMap shouldn't care about 2661 // what's in the registers (except for PHIs). 2662 // values through to all other blocks, as it dominates. 2663 VLocs[0].Vars.insert({Var, DbgValue(LiveInRax, EmptyProps, DbgValue::Def)}); 2664 buildVLocValueMap(OutermostLoc, AllVars, AssignBlocks, Output, 2665 MOutLocs, MInLocs, VLocs); 2666 EXPECT_EQ(Output[0].size(), 0ul); 2667 ASSERT_EQ(Output[1].size(), 1ul); 2668 ASSERT_EQ(Output[2].size(), 1ul); 2669 ASSERT_EQ(Output[3].size(), 1ul); 2670 EXPECT_EQ(Output[1][0].second.Kind, DbgValue::Def); 2671 EXPECT_EQ(Output[1][0].second.ID, LiveInRax); 2672 EXPECT_EQ(Output[2][0].second.Kind, DbgValue::Def); 2673 EXPECT_EQ(Output[2][0].second.ID, LiveInRax); 2674 EXPECT_EQ(Output[3][0].second.Kind, DbgValue::Def); 2675 EXPECT_EQ(Output[3][0].second.ID, LiveInRax); 2676 ClearOutputs(); 2677 VLocs[0].Vars.clear(); 2678 2679 // We should get a live-in to the merging block, if there are two assigns of 2680 // the same value in either side of the diamond. 2681 VLocs[1].Vars.insert({Var, DbgValue(LiveInRsp, EmptyProps, DbgValue::Def)}); 2682 VLocs[2].Vars.insert({Var, DbgValue(LiveInRsp, EmptyProps, DbgValue::Def)}); 2683 buildVLocValueMap(OutermostLoc, AllVars, AssignBlocks, Output, 2684 MOutLocs, MInLocs, VLocs); 2685 EXPECT_EQ(Output[0].size(), 0ul); 2686 EXPECT_EQ(Output[1].size(), 0ul); 2687 EXPECT_EQ(Output[2].size(), 0ul); 2688 ASSERT_EQ(Output[3].size(), 1ul); 2689 EXPECT_EQ(Output[3][0].second.Kind, DbgValue::Def); 2690 EXPECT_EQ(Output[3][0].second.ID, LiveInRsp); 2691 ClearOutputs(); 2692 VLocs[1].Vars.clear(); 2693 VLocs[2].Vars.clear(); 2694 2695 // If we assign a value in the entry block, then 'undef' on a branch, we 2696 // shouldn't have a live-in in the merge block. 2697 VLocs[0].Vars.insert({Var, DbgValue(LiveInRsp, EmptyProps, DbgValue::Def)}); 2698 VLocs[1].Vars.insert({Var, DbgValue(EmptyProps, DbgValue::Undef)}); 2699 buildVLocValueMap(OutermostLoc, AllVars, AssignBlocks, Output, 2700 MOutLocs, MInLocs, VLocs); 2701 EXPECT_EQ(Output[0].size(), 0ul); 2702 ASSERT_EQ(Output[1].size(), 1ul); 2703 ASSERT_EQ(Output[2].size(), 1ul); 2704 EXPECT_EQ(Output[3].size(), 0ul); 2705 EXPECT_EQ(Output[1][0].second.Kind, DbgValue::Def); 2706 EXPECT_EQ(Output[1][0].second.ID, LiveInRsp); 2707 EXPECT_EQ(Output[2][0].second.Kind, DbgValue::Def); 2708 EXPECT_EQ(Output[2][0].second.ID, LiveInRsp); 2709 ClearOutputs(); 2710 VLocs[0].Vars.clear(); 2711 VLocs[1].Vars.clear(); 2712 2713 // Having different values joining into the merge block should mean we have 2714 // no live-in in that block. Block ones LiveInRax value doesn't appear as a 2715 // live-in anywhere, it's block internal. 2716 VLocs[0].Vars.insert({Var, DbgValue(LiveInRsp, EmptyProps, DbgValue::Def)}); 2717 VLocs[1].Vars.insert({Var, DbgValue(LiveInRax, EmptyProps, DbgValue::Def)}); 2718 buildVLocValueMap(OutermostLoc, AllVars, AssignBlocks, Output, 2719 MOutLocs, MInLocs, VLocs); 2720 EXPECT_EQ(Output[0].size(), 0ul); 2721 ASSERT_EQ(Output[1].size(), 1ul); 2722 ASSERT_EQ(Output[2].size(), 1ul); 2723 EXPECT_EQ(Output[3].size(), 0ul); 2724 EXPECT_EQ(Output[1][0].second.Kind, DbgValue::Def); 2725 EXPECT_EQ(Output[1][0].second.ID, LiveInRsp); 2726 EXPECT_EQ(Output[2][0].second.Kind, DbgValue::Def); 2727 EXPECT_EQ(Output[2][0].second.ID, LiveInRsp); 2728 ClearOutputs(); 2729 VLocs[0].Vars.clear(); 2730 VLocs[1].Vars.clear(); 2731 2732 // But on the other hand, if there's a location in the register file where 2733 // those two values can be joined, do so. 2734 MOutLocs[1][0] = LiveInRax; 2735 VLocs[0].Vars.insert({Var, DbgValue(LiveInRsp, EmptyProps, DbgValue::Def)}); 2736 VLocs[1].Vars.insert({Var, DbgValue(LiveInRax, EmptyProps, DbgValue::Def)}); 2737 buildVLocValueMap(OutermostLoc, AllVars, AssignBlocks, Output, 2738 MOutLocs, MInLocs, VLocs); 2739 EXPECT_EQ(Output[0].size(), 0ul); 2740 ASSERT_EQ(Output[1].size(), 1ul); 2741 ASSERT_EQ(Output[2].size(), 1ul); 2742 ASSERT_EQ(Output[3].size(), 1ul); 2743 EXPECT_EQ(Output[1][0].second.Kind, DbgValue::Def); 2744 EXPECT_EQ(Output[1][0].second.ID, LiveInRsp); 2745 EXPECT_EQ(Output[2][0].second.Kind, DbgValue::Def); 2746 EXPECT_EQ(Output[2][0].second.ID, LiveInRsp); 2747 EXPECT_EQ(Output[3][0].second.Kind, DbgValue::Def); 2748 EXPECT_EQ(Output[3][0].second.ID, RspPHIInBlk3); 2749 ClearOutputs(); 2750 VLocs[0].Vars.clear(); 2751 VLocs[1].Vars.clear(); 2752 } 2753 2754 TEST_F(InstrRefLDVTest, VLocSimpleLoop) { 2755 setupSimpleLoop(); 2756 // entry 2757 // | 2758 // |/-----\ 2759 // loopblk | 2760 // |\-----/ 2761 // | 2762 // ret 2763 2764 ASSERT_TRUE(MTracker->getNumLocs() == 1); 2765 LocIdx RspLoc(0); 2766 Register RAX = getRegByName("RAX"); 2767 LocIdx RaxLoc = MTracker->lookupOrTrackRegister(RAX); 2768 2769 unsigned EntryBlk = 0, LoopBlk = 1; 2770 2771 ValueIDNum LiveInRsp = ValueIDNum(EntryBlk, 0, RspLoc); 2772 ValueIDNum LiveInRax = ValueIDNum(EntryBlk, 0, RaxLoc); 2773 ValueIDNum RspPHIInBlk1 = ValueIDNum(LoopBlk, 0, RspLoc); 2774 ValueIDNum RspDefInBlk1 = ValueIDNum(LoopBlk, 1, RspLoc); 2775 ValueIDNum RaxPHIInBlk1 = ValueIDNum(LoopBlk, 0, RaxLoc); 2776 2777 FuncValueTable MInLocs, MOutLocs; 2778 std::tie(MInLocs, MOutLocs) = allocValueTables(3, 2); 2779 2780 initValueArray(MInLocs, 3, 2); 2781 initValueArray(MOutLocs, 3, 2); 2782 2783 DebugVariable Var(FuncVariable, None, nullptr); 2784 DbgValueProperties EmptyProps(EmptyExpr, false); 2785 2786 SmallSet<DebugVariable, 4> AllVars; 2787 AllVars.insert(Var); 2788 2789 SmallPtrSet<MachineBasicBlock *, 4> AssignBlocks; 2790 AssignBlocks.insert(MBB0); 2791 AssignBlocks.insert(MBB1); 2792 AssignBlocks.insert(MBB2); 2793 2794 SmallVector<VLocTracker, 3> VLocs; 2795 VLocs.resize(3, VLocTracker(Overlaps, EmptyExpr)); 2796 2797 InstrRefBasedLDV::LiveInsT Output; 2798 2799 // Start off with LiveInRsp in every location. 2800 for (unsigned int I = 0; I < 3; ++I) { 2801 MInLocs[I][0] = MInLocs[I][1] = LiveInRsp; 2802 MOutLocs[I][0] = MOutLocs[I][1] = LiveInRsp; 2803 } 2804 2805 auto ClearOutputs = [&]() { 2806 for (auto &Elem : Output) 2807 Elem.clear(); 2808 }; 2809 Output.resize(3); 2810 2811 // Easy starter: a dominating assign should propagate to all blocks. 2812 VLocs[0].Vars.insert({Var, DbgValue(LiveInRsp, EmptyProps, DbgValue::Def)}); 2813 buildVLocValueMap(OutermostLoc, AllVars, AssignBlocks, Output, 2814 MOutLocs, MInLocs, VLocs); 2815 EXPECT_EQ(Output[0].size(), 0ul); 2816 ASSERT_EQ(Output[1].size(), 1ul); 2817 ASSERT_EQ(Output[2].size(), 1ul); 2818 EXPECT_EQ(Output[1][0].second.Kind, DbgValue::Def); 2819 EXPECT_EQ(Output[1][0].second.ID, LiveInRsp); 2820 EXPECT_EQ(Output[2][0].second.Kind, DbgValue::Def); 2821 EXPECT_EQ(Output[2][0].second.ID, LiveInRsp); 2822 ClearOutputs(); 2823 VLocs[0].Vars.clear(); 2824 VLocs[1].Vars.clear(); 2825 2826 // Put an undef assignment in the loop. Should get no live-in value. 2827 VLocs[0].Vars.insert({Var, DbgValue(LiveInRsp, EmptyProps, DbgValue::Def)}); 2828 VLocs[1].Vars.insert({Var, DbgValue(EmptyProps, DbgValue::Undef)}); 2829 buildVLocValueMap(OutermostLoc, AllVars, AssignBlocks, Output, 2830 MOutLocs, MInLocs, VLocs); 2831 EXPECT_EQ(Output[0].size(), 0ul); 2832 EXPECT_EQ(Output[1].size(), 0ul); 2833 EXPECT_EQ(Output[2].size(), 0ul); 2834 ClearOutputs(); 2835 VLocs[0].Vars.clear(); 2836 VLocs[1].Vars.clear(); 2837 2838 // Assignment of the same value should naturally join. 2839 VLocs[0].Vars.insert({Var, DbgValue(LiveInRsp, EmptyProps, DbgValue::Def)}); 2840 VLocs[1].Vars.insert({Var, DbgValue(LiveInRsp, EmptyProps, DbgValue::Def)}); 2841 buildVLocValueMap(OutermostLoc, AllVars, AssignBlocks, Output, 2842 MOutLocs, MInLocs, VLocs); 2843 EXPECT_EQ(Output[0].size(), 0ul); 2844 ASSERT_EQ(Output[1].size(), 1ul); 2845 ASSERT_EQ(Output[2].size(), 1ul); 2846 EXPECT_EQ(Output[1][0].second.Kind, DbgValue::Def); 2847 EXPECT_EQ(Output[1][0].second.ID, LiveInRsp); 2848 EXPECT_EQ(Output[2][0].second.Kind, DbgValue::Def); 2849 EXPECT_EQ(Output[2][0].second.ID, LiveInRsp); 2850 ClearOutputs(); 2851 VLocs[0].Vars.clear(); 2852 VLocs[1].Vars.clear(); 2853 2854 // Assignment of different values shouldn't join with no machine PHI vals. 2855 // Will be live-in to exit block as it's dominated. 2856 VLocs[0].Vars.insert({Var, DbgValue(LiveInRsp, EmptyProps, DbgValue::Def)}); 2857 VLocs[1].Vars.insert({Var, DbgValue(LiveInRax, EmptyProps, DbgValue::Def)}); 2858 buildVLocValueMap(OutermostLoc, AllVars, AssignBlocks, Output, 2859 MOutLocs, MInLocs, VLocs); 2860 EXPECT_EQ(Output[0].size(), 0ul); 2861 EXPECT_EQ(Output[1].size(), 0ul); 2862 ASSERT_EQ(Output[2].size(), 1ul); 2863 EXPECT_EQ(Output[2][0].second.Kind, DbgValue::Def); 2864 EXPECT_EQ(Output[2][0].second.ID, LiveInRax); 2865 ClearOutputs(); 2866 VLocs[0].Vars.clear(); 2867 VLocs[1].Vars.clear(); 2868 2869 // Install a completely unrelated PHI value, that we should not join on. Try 2870 // with unrelated assign in loop block again. 2871 MInLocs[1][0] = RspPHIInBlk1; 2872 MOutLocs[1][0] = RspDefInBlk1; 2873 VLocs[0].Vars.insert({Var, DbgValue(LiveInRsp, EmptyProps, DbgValue::Def)}); 2874 VLocs[1].Vars.insert({Var, DbgValue(LiveInRax, EmptyProps, DbgValue::Def)}); 2875 buildVLocValueMap(OutermostLoc, AllVars, AssignBlocks, Output, 2876 MOutLocs, MInLocs, VLocs); 2877 EXPECT_EQ(Output[0].size(), 0ul); 2878 EXPECT_EQ(Output[1].size(), 0ul); 2879 ASSERT_EQ(Output[2].size(), 1ul); 2880 EXPECT_EQ(Output[2][0].second.Kind, DbgValue::Def); 2881 EXPECT_EQ(Output[2][0].second.ID, LiveInRax); 2882 ClearOutputs(); 2883 VLocs[0].Vars.clear(); 2884 VLocs[1].Vars.clear(); 2885 2886 // Now, if we assign RspDefInBlk1 in the loop block, we should be able to 2887 // find the appropriate PHI. 2888 MInLocs[1][0] = RspPHIInBlk1; 2889 MOutLocs[1][0] = RspDefInBlk1; 2890 VLocs[0].Vars.insert({Var, DbgValue(LiveInRsp, EmptyProps, DbgValue::Def)}); 2891 VLocs[1].Vars.insert({Var, DbgValue(RspDefInBlk1, EmptyProps, DbgValue::Def)}); 2892 buildVLocValueMap(OutermostLoc, AllVars, AssignBlocks, Output, 2893 MOutLocs, MInLocs, VLocs); 2894 EXPECT_EQ(Output[0].size(), 0ul); 2895 ASSERT_EQ(Output[1].size(), 1ul); 2896 ASSERT_EQ(Output[2].size(), 1ul); 2897 EXPECT_EQ(Output[1][0].second.Kind, DbgValue::Def); 2898 EXPECT_EQ(Output[1][0].second.ID, RspPHIInBlk1); 2899 EXPECT_EQ(Output[2][0].second.Kind, DbgValue::Def); 2900 EXPECT_EQ(Output[2][0].second.ID, RspDefInBlk1); 2901 ClearOutputs(); 2902 VLocs[0].Vars.clear(); 2903 VLocs[1].Vars.clear(); 2904 2905 // If the PHI happens in a different location, the live-in should happen 2906 // there. 2907 MInLocs[1][0] = LiveInRsp; 2908 MOutLocs[1][0] = LiveInRsp; 2909 MInLocs[1][1] = RaxPHIInBlk1; 2910 MOutLocs[1][1] = RspDefInBlk1; 2911 VLocs[0].Vars.insert({Var, DbgValue(LiveInRsp, EmptyProps, DbgValue::Def)}); 2912 VLocs[1].Vars.insert({Var, DbgValue(RspDefInBlk1, EmptyProps, DbgValue::Def)}); 2913 buildVLocValueMap(OutermostLoc, AllVars, AssignBlocks, Output, 2914 MOutLocs, MInLocs, VLocs); 2915 EXPECT_EQ(Output[0].size(), 0ul); 2916 ASSERT_EQ(Output[1].size(), 1ul); 2917 ASSERT_EQ(Output[2].size(), 1ul); 2918 EXPECT_EQ(Output[1][0].second.Kind, DbgValue::Def); 2919 EXPECT_EQ(Output[1][0].second.ID, RaxPHIInBlk1); 2920 EXPECT_EQ(Output[2][0].second.Kind, DbgValue::Def); 2921 EXPECT_EQ(Output[2][0].second.ID, RspDefInBlk1); 2922 ClearOutputs(); 2923 VLocs[0].Vars.clear(); 2924 VLocs[1].Vars.clear(); 2925 2926 // The PHI happening in both places should be handled too. Exactly where 2927 // isn't important, but if the location picked changes, this test will let 2928 // you know. 2929 MInLocs[1][0] = RaxPHIInBlk1; 2930 MOutLocs[1][0] = RspDefInBlk1; 2931 MInLocs[1][1] = RaxPHIInBlk1; 2932 MOutLocs[1][1] = RspDefInBlk1; 2933 VLocs[0].Vars.insert({Var, DbgValue(LiveInRsp, EmptyProps, DbgValue::Def)}); 2934 VLocs[1].Vars.insert({Var, DbgValue(RspDefInBlk1, EmptyProps, DbgValue::Def)}); 2935 buildVLocValueMap(OutermostLoc, AllVars, AssignBlocks, Output, 2936 MOutLocs, MInLocs, VLocs); 2937 EXPECT_EQ(Output[0].size(), 0ul); 2938 ASSERT_EQ(Output[1].size(), 1ul); 2939 ASSERT_EQ(Output[2].size(), 1ul); 2940 EXPECT_EQ(Output[1][0].second.Kind, DbgValue::Def); 2941 // Today, the first register is picked. 2942 EXPECT_EQ(Output[1][0].second.ID, RspPHIInBlk1); 2943 EXPECT_EQ(Output[2][0].second.Kind, DbgValue::Def); 2944 EXPECT_EQ(Output[2][0].second.ID, RspDefInBlk1); 2945 ClearOutputs(); 2946 VLocs[0].Vars.clear(); 2947 VLocs[1].Vars.clear(); 2948 2949 // If the loop block looked a bit like this: 2950 // %0 = PHI %1, %2 2951 // [...] 2952 // DBG_VALUE %0 2953 // Then with instr-ref it becomes: 2954 // DBG_PHI %0 2955 // [...] 2956 // DBG_INSTR_REF 2957 // And we would be feeding a machine PHI-value back around the loop. However: 2958 // this does not mean we can eliminate the variable value PHI and use the 2959 // variable value from the entry block: they are distinct values that must be 2960 // joined at some location by the control flow. 2961 // [This test input would never occur naturally, the machine-PHI would be 2962 // eliminated] 2963 MInLocs[1][0] = RspPHIInBlk1; 2964 MOutLocs[1][0] = RspPHIInBlk1; 2965 MInLocs[1][1] = LiveInRax; 2966 MOutLocs[1][1] = LiveInRax; 2967 VLocs[0].Vars.insert({Var, DbgValue(LiveInRsp, EmptyProps, DbgValue::Def)}); 2968 VLocs[1].Vars.insert({Var, DbgValue(RspPHIInBlk1, EmptyProps, DbgValue::Def)}); 2969 buildVLocValueMap(OutermostLoc, AllVars, AssignBlocks, Output, 2970 MOutLocs, MInLocs, VLocs); 2971 EXPECT_EQ(Output[0].size(), 0ul); 2972 ASSERT_EQ(Output[1].size(), 1ul); 2973 ASSERT_EQ(Output[2].size(), 1ul); 2974 EXPECT_EQ(Output[1][0].second.Kind, DbgValue::Def); 2975 EXPECT_EQ(Output[1][0].second.ID, RspPHIInBlk1); 2976 EXPECT_EQ(Output[2][0].second.Kind, DbgValue::Def); 2977 EXPECT_EQ(Output[2][0].second.ID, RspPHIInBlk1); 2978 ClearOutputs(); 2979 VLocs[0].Vars.clear(); 2980 VLocs[1].Vars.clear(); 2981 2982 // Test that we can eliminate PHIs. A PHI will be placed at the loop head 2983 // because there's a def in in. 2984 MInLocs[1][0] = LiveInRsp; 2985 MOutLocs[1][0] = LiveInRsp; 2986 VLocs[0].Vars.insert({Var, DbgValue(LiveInRsp, EmptyProps, DbgValue::Def)}); 2987 VLocs[1].Vars.insert({Var, DbgValue(LiveInRsp, EmptyProps, DbgValue::Def)}); 2988 buildVLocValueMap(OutermostLoc, AllVars, AssignBlocks, Output, 2989 MOutLocs, MInLocs, VLocs); 2990 EXPECT_EQ(Output[0].size(), 0ul); 2991 ASSERT_EQ(Output[1].size(), 1ul); 2992 ASSERT_EQ(Output[2].size(), 1ul); 2993 EXPECT_EQ(Output[1][0].second.Kind, DbgValue::Def); 2994 EXPECT_EQ(Output[1][0].second.ID, LiveInRsp); 2995 EXPECT_EQ(Output[2][0].second.Kind, DbgValue::Def); 2996 EXPECT_EQ(Output[2][0].second.ID, LiveInRsp); 2997 ClearOutputs(); 2998 VLocs[0].Vars.clear(); 2999 VLocs[1].Vars.clear(); 3000 } 3001 3002 // test phi elimination with the nested situation 3003 TEST_F(InstrRefLDVTest, VLocNestedLoop) { 3004 // entry 3005 // | 3006 // loop1 3007 // ^\ 3008 // | \ /-\ 3009 // | loop2 | 3010 // | / \-/ 3011 // ^ / 3012 // join 3013 // | 3014 // ret 3015 setupNestedLoops(); 3016 3017 ASSERT_TRUE(MTracker->getNumLocs() == 1); 3018 LocIdx RspLoc(0); 3019 Register RAX = getRegByName("RAX"); 3020 LocIdx RaxLoc = MTracker->lookupOrTrackRegister(RAX); 3021 3022 unsigned EntryBlk = 0, Loop1Blk = 1, Loop2Blk = 2; 3023 3024 ValueIDNum LiveInRsp = ValueIDNum(EntryBlk, 0, RspLoc); 3025 ValueIDNum LiveInRax = ValueIDNum(EntryBlk, 0, RaxLoc); 3026 ValueIDNum RspPHIInBlk1 = ValueIDNum(Loop1Blk, 0, RspLoc); 3027 ValueIDNum RspPHIInBlk2 = ValueIDNum(Loop2Blk, 0, RspLoc); 3028 ValueIDNum RspDefInBlk2 = ValueIDNum(Loop2Blk, 1, RspLoc); 3029 3030 FuncValueTable MInLocs, MOutLocs; 3031 std::tie(MInLocs, MOutLocs) = allocValueTables(5, 2); 3032 3033 initValueArray(MInLocs, 5, 2); 3034 initValueArray(MOutLocs, 5, 2); 3035 3036 DebugVariable Var(FuncVariable, None, nullptr); 3037 DbgValueProperties EmptyProps(EmptyExpr, false); 3038 3039 SmallSet<DebugVariable, 4> AllVars; 3040 AllVars.insert(Var); 3041 3042 SmallPtrSet<MachineBasicBlock *, 5> AssignBlocks; 3043 AssignBlocks.insert(MBB0); 3044 AssignBlocks.insert(MBB1); 3045 AssignBlocks.insert(MBB2); 3046 AssignBlocks.insert(MBB3); 3047 AssignBlocks.insert(MBB4); 3048 3049 SmallVector<VLocTracker, 5> VLocs; 3050 VLocs.resize(5, VLocTracker(Overlaps, EmptyExpr)); 3051 3052 InstrRefBasedLDV::LiveInsT Output; 3053 3054 // Start off with LiveInRsp in every location. 3055 for (unsigned int I = 0; I < 5; ++I) { 3056 MInLocs[I][0] = MInLocs[I][1] = LiveInRsp; 3057 MOutLocs[I][0] = MOutLocs[I][1] = LiveInRsp; 3058 } 3059 3060 auto ClearOutputs = [&]() { 3061 for (auto &Elem : Output) 3062 Elem.clear(); 3063 }; 3064 Output.resize(5); 3065 3066 // A dominating assign should propagate to all blocks. 3067 VLocs[0].Vars.insert({Var, DbgValue(LiveInRsp, EmptyProps, DbgValue::Def)}); 3068 buildVLocValueMap(OutermostLoc, AllVars, AssignBlocks, Output, 3069 MOutLocs, MInLocs, VLocs); 3070 EXPECT_EQ(Output[0].size(), 0ul); 3071 ASSERT_EQ(Output[1].size(), 1ul); 3072 ASSERT_EQ(Output[2].size(), 1ul); 3073 ASSERT_EQ(Output[3].size(), 1ul); 3074 ASSERT_EQ(Output[4].size(), 1ul); 3075 EXPECT_EQ(Output[1][0].second.Kind, DbgValue::Def); 3076 EXPECT_EQ(Output[1][0].second.ID, LiveInRsp); 3077 EXPECT_EQ(Output[2][0].second.Kind, DbgValue::Def); 3078 EXPECT_EQ(Output[2][0].second.ID, LiveInRsp); 3079 EXPECT_EQ(Output[3][0].second.Kind, DbgValue::Def); 3080 EXPECT_EQ(Output[3][0].second.ID, LiveInRsp); 3081 EXPECT_EQ(Output[4][0].second.Kind, DbgValue::Def); 3082 EXPECT_EQ(Output[4][0].second.ID, LiveInRsp); 3083 ClearOutputs(); 3084 VLocs[0].Vars.clear(); 3085 3086 // Test that an assign in the inner loop causes unresolved PHIs at the heads 3087 // of both loops, and no output location. Dominated blocks do get values. 3088 VLocs[0].Vars.insert({Var, DbgValue(LiveInRsp, EmptyProps, DbgValue::Def)}); 3089 VLocs[2].Vars.insert({Var, DbgValue(LiveInRax, EmptyProps, DbgValue::Def)}); 3090 buildVLocValueMap(OutermostLoc, AllVars, AssignBlocks, Output, 3091 MOutLocs, MInLocs, VLocs); 3092 EXPECT_EQ(Output[0].size(), 0ul); 3093 EXPECT_EQ(Output[1].size(), 0ul); 3094 EXPECT_EQ(Output[2].size(), 0ul); 3095 ASSERT_EQ(Output[3].size(), 1ul); 3096 ASSERT_EQ(Output[4].size(), 1ul); 3097 EXPECT_EQ(Output[3][0].second.Kind, DbgValue::Def); 3098 EXPECT_EQ(Output[3][0].second.ID, LiveInRax); 3099 EXPECT_EQ(Output[4][0].second.Kind, DbgValue::Def); 3100 EXPECT_EQ(Output[4][0].second.ID, LiveInRax); 3101 ClearOutputs(); 3102 VLocs[0].Vars.clear(); 3103 VLocs[2].Vars.clear(); 3104 3105 // Same test, but with no assignment in block 0. We should still get values 3106 // in dominated blocks. 3107 VLocs[2].Vars.insert({Var, DbgValue(LiveInRax, EmptyProps, DbgValue::Def)}); 3108 buildVLocValueMap(OutermostLoc, AllVars, AssignBlocks, Output, 3109 MOutLocs, MInLocs, VLocs); 3110 EXPECT_EQ(Output[0].size(), 0ul); 3111 EXPECT_EQ(Output[1].size(), 0ul); 3112 EXPECT_EQ(Output[2].size(), 0ul); 3113 ASSERT_EQ(Output[3].size(), 1ul); 3114 ASSERT_EQ(Output[4].size(), 1ul); 3115 EXPECT_EQ(Output[3][0].second.Kind, DbgValue::Def); 3116 EXPECT_EQ(Output[3][0].second.ID, LiveInRax); 3117 EXPECT_EQ(Output[4][0].second.Kind, DbgValue::Def); 3118 EXPECT_EQ(Output[4][0].second.ID, LiveInRax); 3119 ClearOutputs(); 3120 VLocs[2].Vars.clear(); 3121 3122 // Similarly, assignments in the outer loop gives location to dominated 3123 // blocks, but no PHI locations are found at the outer loop head. 3124 VLocs[0].Vars.insert({Var, DbgValue(LiveInRsp, EmptyProps, DbgValue::Def)}); 3125 VLocs[3].Vars.insert({Var, DbgValue(LiveInRax, EmptyProps, DbgValue::Def)}); 3126 buildVLocValueMap(OutermostLoc, AllVars, AssignBlocks, Output, 3127 MOutLocs, MInLocs, VLocs); 3128 EXPECT_EQ(Output[0].size(), 0ul); 3129 EXPECT_EQ(Output[1].size(), 0ul); 3130 EXPECT_EQ(Output[2].size(), 0ul); 3131 EXPECT_EQ(Output[3].size(), 0ul); 3132 ASSERT_EQ(Output[4].size(), 1ul); 3133 EXPECT_EQ(Output[4][0].second.Kind, DbgValue::Def); 3134 EXPECT_EQ(Output[4][0].second.ID, LiveInRax); 3135 ClearOutputs(); 3136 VLocs[0].Vars.clear(); 3137 VLocs[3].Vars.clear(); 3138 3139 VLocs[0].Vars.insert({Var, DbgValue(LiveInRsp, EmptyProps, DbgValue::Def)}); 3140 VLocs[1].Vars.insert({Var, DbgValue(LiveInRax, EmptyProps, DbgValue::Def)}); 3141 buildVLocValueMap(OutermostLoc, AllVars, AssignBlocks, Output, 3142 MOutLocs, MInLocs, VLocs); 3143 EXPECT_EQ(Output[0].size(), 0ul); 3144 EXPECT_EQ(Output[1].size(), 0ul); 3145 ASSERT_EQ(Output[2].size(), 1ul); 3146 ASSERT_EQ(Output[3].size(), 1ul); 3147 ASSERT_EQ(Output[4].size(), 1ul); 3148 EXPECT_EQ(Output[2][0].second.Kind, DbgValue::Def); 3149 EXPECT_EQ(Output[2][0].second.ID, LiveInRax); 3150 EXPECT_EQ(Output[3][0].second.Kind, DbgValue::Def); 3151 EXPECT_EQ(Output[3][0].second.ID, LiveInRax); 3152 EXPECT_EQ(Output[4][0].second.Kind, DbgValue::Def); 3153 EXPECT_EQ(Output[4][0].second.ID, LiveInRax); 3154 ClearOutputs(); 3155 VLocs[0].Vars.clear(); 3156 VLocs[1].Vars.clear(); 3157 3158 // With an assignment of the same value in the inner loop, we should work out 3159 // that all PHIs can be eliminated and the same value is live-through the 3160 // whole function. 3161 VLocs[0].Vars.insert({Var, DbgValue(LiveInRsp, EmptyProps, DbgValue::Def)}); 3162 VLocs[2].Vars.insert({Var, DbgValue(LiveInRsp, EmptyProps, DbgValue::Def)}); 3163 buildVLocValueMap(OutermostLoc, AllVars, AssignBlocks, Output, 3164 MOutLocs, MInLocs, VLocs); 3165 EXPECT_EQ(Output[0].size(), 0ul); 3166 EXPECT_EQ(Output[1].size(), 1ul); 3167 EXPECT_EQ(Output[2].size(), 1ul); 3168 ASSERT_EQ(Output[3].size(), 1ul); 3169 ASSERT_EQ(Output[4].size(), 1ul); 3170 EXPECT_EQ(Output[1][0].second.Kind, DbgValue::Def); 3171 EXPECT_EQ(Output[1][0].second.ID, LiveInRsp); 3172 EXPECT_EQ(Output[2][0].second.Kind, DbgValue::Def); 3173 EXPECT_EQ(Output[2][0].second.ID, LiveInRsp); 3174 EXPECT_EQ(Output[3][0].second.Kind, DbgValue::Def); 3175 EXPECT_EQ(Output[3][0].second.ID, LiveInRsp); 3176 EXPECT_EQ(Output[4][0].second.Kind, DbgValue::Def); 3177 EXPECT_EQ(Output[4][0].second.ID, LiveInRsp); 3178 ClearOutputs(); 3179 VLocs[0].Vars.clear(); 3180 VLocs[2].Vars.clear(); 3181 3182 // If we have an assignment in the inner loop, and a PHI for it at the inner 3183 // loop head, we could find a live-in location for the inner loop. But because 3184 // the outer loop has no PHI, we can't find a variable value for outer loop 3185 // head, so can't have a live-in value for the inner loop head. 3186 MInLocs[2][0] = RspPHIInBlk2; 3187 MOutLocs[2][0] = LiveInRax; 3188 // NB: all other machine locations are LiveInRsp, disallowing a PHI in block 3189 // one. Even though RspPHIInBlk2 isn't available later in the function, we 3190 // should still produce a live-in value. The fact it's unavailable is a 3191 // different concern. 3192 VLocs[0].Vars.insert({Var, DbgValue(LiveInRsp, EmptyProps, DbgValue::Def)}); 3193 VLocs[2].Vars.insert({Var, DbgValue(LiveInRax, EmptyProps, DbgValue::Def)}); 3194 buildVLocValueMap(OutermostLoc, AllVars, AssignBlocks, Output, 3195 MOutLocs, MInLocs, VLocs); 3196 EXPECT_EQ(Output[0].size(), 0ul); 3197 EXPECT_EQ(Output[1].size(), 0ul); 3198 EXPECT_EQ(Output[2].size(), 0ul); 3199 ASSERT_EQ(Output[3].size(), 1ul); 3200 ASSERT_EQ(Output[4].size(), 1ul); 3201 EXPECT_EQ(Output[3][0].second.Kind, DbgValue::Def); 3202 EXPECT_EQ(Output[3][0].second.ID, LiveInRax); 3203 EXPECT_EQ(Output[4][0].second.Kind, DbgValue::Def); 3204 EXPECT_EQ(Output[4][0].second.ID, LiveInRax); 3205 ClearOutputs(); 3206 VLocs[0].Vars.clear(); 3207 VLocs[2].Vars.clear(); 3208 3209 // Have an assignment in inner loop that can have a PHI resolved; and add a 3210 // machine value PHI to the outer loop head, so that we can find a location 3211 // all the way through the function. 3212 MInLocs[1][0] = RspPHIInBlk1; 3213 MOutLocs[1][0] = RspPHIInBlk1; 3214 MInLocs[2][0] = RspPHIInBlk2; 3215 MOutLocs[2][0] = RspDefInBlk2; 3216 MInLocs[3][0] = RspDefInBlk2; 3217 MOutLocs[3][0] = RspDefInBlk2; 3218 VLocs[0].Vars.insert({Var, DbgValue(LiveInRsp, EmptyProps, DbgValue::Def)}); 3219 VLocs[2].Vars.insert({Var, DbgValue(RspDefInBlk2, EmptyProps, DbgValue::Def)}); 3220 buildVLocValueMap(OutermostLoc, AllVars, AssignBlocks, Output, 3221 MOutLocs, MInLocs, VLocs); 3222 EXPECT_EQ(Output[0].size(), 0ul); 3223 ASSERT_EQ(Output[1].size(), 1ul); 3224 ASSERT_EQ(Output[2].size(), 1ul); 3225 ASSERT_EQ(Output[3].size(), 1ul); 3226 ASSERT_EQ(Output[4].size(), 1ul); 3227 EXPECT_EQ(Output[1][0].second.Kind, DbgValue::Def); 3228 EXPECT_EQ(Output[1][0].second.ID, RspPHIInBlk1); 3229 EXPECT_EQ(Output[2][0].second.Kind, DbgValue::Def); 3230 EXPECT_EQ(Output[2][0].second.ID, RspPHIInBlk2); 3231 EXPECT_EQ(Output[3][0].second.Kind, DbgValue::Def); 3232 EXPECT_EQ(Output[3][0].second.ID, RspDefInBlk2); 3233 EXPECT_EQ(Output[4][0].second.Kind, DbgValue::Def); 3234 EXPECT_EQ(Output[4][0].second.ID, RspDefInBlk2); 3235 ClearOutputs(); 3236 VLocs[0].Vars.clear(); 3237 VLocs[2].Vars.clear(); 3238 } 3239 3240