1 //===-- SerialSnippetGenerator.cpp ------------------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "SerialSnippetGenerator.h" 10 11 #include "CodeTemplate.h" 12 #include "MCInstrDescView.h" 13 #include "Target.h" 14 #include <algorithm> 15 #include <numeric> 16 #include <vector> 17 18 namespace llvm { 19 namespace exegesis { 20 21 struct ExecutionClass { 22 ExecutionMode Mask; 23 const char *Description; 24 } static const kExecutionClasses[] = { 25 {ExecutionMode::ALWAYS_SERIAL_IMPLICIT_REGS_ALIAS | 26 ExecutionMode::ALWAYS_SERIAL_TIED_REGS_ALIAS, 27 "Repeating a single implicitly serial instruction"}, 28 {ExecutionMode::SERIAL_VIA_EXPLICIT_REGS, 29 "Repeating a single explicitly serial instruction"}, 30 {ExecutionMode::SERIAL_VIA_MEMORY_INSTR | 31 ExecutionMode::SERIAL_VIA_NON_MEMORY_INSTR, 32 "Repeating two instructions"}, 33 }; 34 35 static constexpr size_t kMaxAliasingInstructions = 10; 36 37 static std::vector<const Instruction *> 38 computeAliasingInstructions(const LLVMState &State, const Instruction *Instr, 39 size_t MaxAliasingInstructions, 40 const BitVector &ForbiddenRegisters) { 41 const auto &ET = State.getExegesisTarget(); 42 const auto AvailableFeatures = State.getSubtargetInfo().getFeatureBits(); 43 // Randomly iterate the set of instructions. 44 std::vector<unsigned> Opcodes; 45 Opcodes.resize(State.getInstrInfo().getNumOpcodes()); 46 std::iota(Opcodes.begin(), Opcodes.end(), 0U); 47 llvm::shuffle(Opcodes.begin(), Opcodes.end(), randomGenerator()); 48 49 std::vector<const Instruction *> AliasingInstructions; 50 for (const unsigned OtherOpcode : Opcodes) { 51 if (!ET.isOpcodeAvailable(OtherOpcode, AvailableFeatures)) 52 continue; 53 if (OtherOpcode == Instr->Description.getOpcode()) 54 continue; 55 const Instruction &OtherInstr = State.getIC().getInstr(OtherOpcode); 56 const MCInstrDesc &OtherInstrDesc = OtherInstr.Description; 57 if (OtherInstr.hasMemoryOperands()) 58 continue; 59 if (!ET.allowAsBackToBack(OtherInstr)) 60 continue; 61 if (Instr->hasAliasingRegistersThrough(OtherInstr, ForbiddenRegisters)) 62 AliasingInstructions.push_back(&OtherInstr); 63 if (AliasingInstructions.size() >= MaxAliasingInstructions) 64 break; 65 } 66 return AliasingInstructions; 67 } 68 69 static ExecutionMode getExecutionModes(const Instruction &Instr, 70 const BitVector &ForbiddenRegisters) { 71 ExecutionMode EM = ExecutionMode::UNKNOWN; 72 if (Instr.hasAliasingImplicitRegisters()) 73 EM |= ExecutionMode::ALWAYS_SERIAL_IMPLICIT_REGS_ALIAS; 74 if (Instr.hasTiedRegisters()) 75 EM |= ExecutionMode::ALWAYS_SERIAL_TIED_REGS_ALIAS; 76 if (Instr.hasMemoryOperands()) 77 EM |= ExecutionMode::SERIAL_VIA_MEMORY_INSTR; 78 if (Instr.hasAliasingNotMemoryRegisters(ForbiddenRegisters)) 79 EM |= ExecutionMode::SERIAL_VIA_EXPLICIT_REGS; 80 if (Instr.hasOneUseOrOneDef()) 81 EM |= ExecutionMode::SERIAL_VIA_NON_MEMORY_INSTR; 82 return EM; 83 } 84 85 static void appendCodeTemplates(const LLVMState &State, 86 InstructionTemplate Variant, 87 const BitVector &ForbiddenRegisters, 88 ExecutionMode ExecutionModeBit, 89 StringRef ExecutionClassDescription, 90 std::vector<CodeTemplate> &CodeTemplates) { 91 assert(isEnumValue(ExecutionModeBit) && "Bit must be a power of two"); 92 switch (ExecutionModeBit) { 93 case ExecutionMode::ALWAYS_SERIAL_IMPLICIT_REGS_ALIAS: 94 // Nothing to do, the instruction is always serial. 95 [[fallthrough]]; 96 case ExecutionMode::ALWAYS_SERIAL_TIED_REGS_ALIAS: { 97 // Picking whatever value for the tied variable will make the instruction 98 // serial. 99 CodeTemplate CT; 100 CT.Execution = ExecutionModeBit; 101 CT.Info = std::string(ExecutionClassDescription); 102 CT.Instructions.push_back(std::move(Variant)); 103 CodeTemplates.push_back(std::move(CT)); 104 return; 105 } 106 case ExecutionMode::SERIAL_VIA_MEMORY_INSTR: { 107 // Select back-to-back memory instruction. 108 // TODO: Implement me. 109 return; 110 } 111 case ExecutionMode::SERIAL_VIA_EXPLICIT_REGS: { 112 // Making the execution of this instruction serial by selecting one def 113 // register to alias with one use register. 114 const AliasingConfigurations SelfAliasing( 115 Variant.getInstr(), Variant.getInstr(), ForbiddenRegisters); 116 assert(!SelfAliasing.empty() && !SelfAliasing.hasImplicitAliasing() && 117 "Instr must alias itself explicitly"); 118 // This is a self aliasing instruction so defs and uses are from the same 119 // instance, hence twice Variant in the following call. 120 setRandomAliasing(SelfAliasing, Variant, Variant); 121 CodeTemplate CT; 122 CT.Execution = ExecutionModeBit; 123 CT.Info = std::string(ExecutionClassDescription); 124 CT.Instructions.push_back(std::move(Variant)); 125 CodeTemplates.push_back(std::move(CT)); 126 return; 127 } 128 case ExecutionMode::SERIAL_VIA_NON_MEMORY_INSTR: { 129 const Instruction &Instr = Variant.getInstr(); 130 // Select back-to-back non-memory instruction. 131 for (const auto *OtherInstr : computeAliasingInstructions( 132 State, &Instr, kMaxAliasingInstructions, ForbiddenRegisters)) { 133 const AliasingConfigurations Forward(Instr, *OtherInstr, 134 ForbiddenRegisters); 135 const AliasingConfigurations Back(*OtherInstr, Instr, ForbiddenRegisters); 136 InstructionTemplate ThisIT(Variant); 137 InstructionTemplate OtherIT(OtherInstr); 138 if (!Forward.hasImplicitAliasing()) 139 setRandomAliasing(Forward, ThisIT, OtherIT); 140 else if (!Back.hasImplicitAliasing()) 141 setRandomAliasing(Back, OtherIT, ThisIT); 142 CodeTemplate CT; 143 CT.Execution = ExecutionModeBit; 144 CT.Info = std::string(ExecutionClassDescription); 145 CT.Instructions.push_back(std::move(ThisIT)); 146 CT.Instructions.push_back(std::move(OtherIT)); 147 CodeTemplates.push_back(std::move(CT)); 148 } 149 return; 150 } 151 default: 152 llvm_unreachable("Unhandled enum value"); 153 } 154 } 155 156 SerialSnippetGenerator::~SerialSnippetGenerator() = default; 157 158 Expected<std::vector<CodeTemplate>> 159 SerialSnippetGenerator::generateCodeTemplates( 160 InstructionTemplate Variant, const BitVector &ForbiddenRegisters) const { 161 std::vector<CodeTemplate> Results; 162 const ExecutionMode EM = 163 getExecutionModes(Variant.getInstr(), ForbiddenRegisters); 164 for (const auto EC : kExecutionClasses) { 165 for (const auto ExecutionModeBit : getExecutionModeBits(EM & EC.Mask)) 166 appendCodeTemplates(State, Variant, ForbiddenRegisters, ExecutionModeBit, 167 EC.Description, Results); 168 if (!Results.empty()) 169 break; 170 } 171 if (Results.empty()) 172 return make_error<Failure>( 173 "No strategy found to make the execution serial"); 174 return std::move(Results); 175 } 176 177 } // namespace exegesis 178 } // namespace llvm 179