xref: /llvm-project/llvm/test/Transforms/VectorCombine/X86/select-shuffle.ll (revision c3677e45222a9461eed0224b99bd8ea19bc52bf6)
1af39acdaSSanjay Patel; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2af39acdaSSanjay Patel; RUN: opt < %s -passes=vector-combine -S -mtriple=x86_64-- | FileCheck %s
3af39acdaSSanjay Patel
4af39acdaSSanjay Pateltarget datalayout = "e-p:64:64-i64:64-f80:128-n8:16:32:64-S128"
5af39acdaSSanjay Patel
6af39acdaSSanjay Patel; This would insert before a phi instruction which is invalid IR.
7af39acdaSSanjay Patel
8af39acdaSSanjay Pateldefine <4 x double> @PR60649() {
9af39acdaSSanjay Patel; CHECK-LABEL: @PR60649(
10af39acdaSSanjay Patel; CHECK-NEXT:  entry:
11af39acdaSSanjay Patel; CHECK-NEXT:    br label [[END:%.*]]
12af39acdaSSanjay Patel; CHECK:       unreachable:
13af39acdaSSanjay Patel; CHECK-NEXT:    br label [[END]]
14af39acdaSSanjay Patel; CHECK:       end:
15*c3677e45SDavid Green; CHECK-NEXT:    [[T0:%.*]] = phi <4 x double> [ zeroinitializer, [[ENTRY:%.*]] ], [ zeroinitializer, [[UNREACHABLE:%.*]] ]
16af39acdaSSanjay Patel; CHECK-NEXT:    [[T1:%.*]] = phi <4 x double> [ zeroinitializer, [[ENTRY]] ], [ zeroinitializer, [[UNREACHABLE]] ]
17*c3677e45SDavid Green; CHECK-NEXT:    [[TMP0:%.*]] = shufflevector <4 x double> [[T0]], <4 x double> [[T0]], <4 x i32> <i32 2, i32 3, i32 poison, i32 poison>
18*c3677e45SDavid Green; CHECK-NEXT:    [[TMP1:%.*]] = shufflevector <4 x double> [[T0]], <4 x double> [[T0]], <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
19*c3677e45SDavid Green; CHECK-NEXT:    [[TMP2:%.*]] = fdiv <4 x double> [[TMP1]], <double 0.000000e+00, double 0.000000e+00, double undef, double undef>
20*c3677e45SDavid Green; CHECK-NEXT:    [[TMP3:%.*]] = fmul <4 x double> [[TMP0]], <double 0.000000e+00, double 0.000000e+00, double undef, double undef>
21af39acdaSSanjay Patel; CHECK-NEXT:    [[T5:%.*]] = shufflevector <4 x double> [[TMP2]], <4 x double> [[TMP3]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
22af39acdaSSanjay Patel; CHECK-NEXT:    ret <4 x double> [[T5]]
23af39acdaSSanjay Patel;
24af39acdaSSanjay Patelentry:
25af39acdaSSanjay Patel  br label %end
26af39acdaSSanjay Patel
27af39acdaSSanjay Patelunreachable:
28af39acdaSSanjay Patel  br label %end
29af39acdaSSanjay Patel
30af39acdaSSanjay Patelend:
31af39acdaSSanjay Patel  %t0 = phi <4 x double> [ zeroinitializer, %entry ], [ zeroinitializer, %unreachable ]
32af39acdaSSanjay Patel  %t1 = phi <4 x double> [ zeroinitializer, %entry ], [ zeroinitializer, %unreachable ]
33af39acdaSSanjay Patel  %t2 = shufflevector <4 x double> zeroinitializer, <4 x double> zeroinitializer, <4 x i32> <i32 0, i32 0, i32 1, i32 1>
34af39acdaSSanjay Patel  %t3 = fdiv <4 x double> %t0, %t2
35af39acdaSSanjay Patel  %t4 = fmul <4 x double> %t0, %t2
36af39acdaSSanjay Patel  %t5 = shufflevector <4 x double> %t3, <4 x double> %t4, <4 x i32> <i32 0, i32 1, i32 6, i32 7>
37af39acdaSSanjay Patel  ret <4 x double> %t5
38af39acdaSSanjay Patel}
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