xref: /llvm-project/llvm/test/Transforms/VectorCombine/X86/no-sse.ll (revision 5e4dbd7a2fb095a6c25ec4758b806571c033e88e)
1cc892fd9SSanjay Patel; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2*5e4dbd7aSBjorn Pettersson; RUN: opt < %s -passes=vector-combine -S -mtriple=x86_64-- -mattr=-sse | FileCheck %s
3cc892fd9SSanjay Patel
4cc892fd9SSanjay Patel; Don't spend time on vector transforms if the target does not support vectors.
589a7f64aSSanjay Patel
689a7f64aSSanjay Pateldefine <4 x float> @bitcast_shuf_same_size(<4 x i32> %v) {
789a7f64aSSanjay Patel; CHECK-LABEL: @bitcast_shuf_same_size(
8cc892fd9SSanjay Patel; CHECK-NEXT:    [[SHUF:%.*]] = shufflevector <4 x i32> [[V:%.*]], <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
9cc892fd9SSanjay Patel; CHECK-NEXT:    [[R:%.*]] = bitcast <4 x i32> [[SHUF]] to <4 x float>
1089a7f64aSSanjay Patel; CHECK-NEXT:    ret <4 x float> [[R]]
1189a7f64aSSanjay Patel;
1289a7f64aSSanjay Patel  %shuf = shufflevector <4 x i32> %v, <4 x i32> undef, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
1389a7f64aSSanjay Patel  %r = bitcast <4 x i32> %shuf to <4 x float>
1489a7f64aSSanjay Patel  ret <4 x float> %r
1589a7f64aSSanjay Patel}
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