1285bc698SAlexey Bataev; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 2285bc698SAlexey Bataev; RUN: opt -S --passes=slp-vectorizer -mtriple=s390x-unknown-linux -mcpu=z14 < %s | FileCheck %s 3285bc698SAlexey Bataev 4285bc698SAlexey Bataevdefine void @test() { 5285bc698SAlexey Bataev; CHECK-LABEL: define void @test( 6285bc698SAlexey Bataev; CHECK-SAME: ) #[[ATTR0:[0-9]+]] { 7285bc698SAlexey Bataev; CHECK-NEXT: [[TMP1:%.*]] = zext i8 0 to i32 8285bc698SAlexey Bataev; CHECK-NEXT: [[TMP2:%.*]] = zext i8 0 to i32 9*a9888211SAlexey Bataev; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i32> <i32 poison, i32 0, i32 0, i32 0>, i32 [[TMP2]], i32 0 10285bc698SAlexey Bataev; CHECK-NEXT: [[TMP4:%.*]] = select <4 x i1> zeroinitializer, <4 x i32> zeroinitializer, <4 x i32> [[TMP3]] 11285bc698SAlexey Bataev; CHECK-NEXT: [[TMP5:%.*]] = select i1 false, i32 0, i32 0 12285bc698SAlexey Bataev; CHECK-NEXT: [[TMP6:%.*]] = select i1 false, i32 0, i32 [[TMP1]] 13285bc698SAlexey Bataev; CHECK-NEXT: [[TMP7:%.*]] = select i1 false, i32 0, i32 [[TMP2]] 14285bc698SAlexey Bataev; CHECK-NEXT: [[TMP8:%.*]] = call i32 @llvm.vector.reduce.xor.v4i32(<4 x i32> [[TMP4]]) 15285bc698SAlexey Bataev; CHECK-NEXT: [[OP_RDX:%.*]] = xor i32 [[TMP8]], [[TMP5]] 16285bc698SAlexey Bataev; CHECK-NEXT: [[OP_RDX1:%.*]] = xor i32 [[TMP6]], [[TMP7]] 17285bc698SAlexey Bataev; CHECK-NEXT: [[OP_RDX2:%.*]] = xor i32 [[OP_RDX]], [[OP_RDX1]] 18285bc698SAlexey Bataev; CHECK-NEXT: [[TMP9:%.*]] = trunc i32 [[OP_RDX2]] to i16 19285bc698SAlexey Bataev; CHECK-NEXT: store i16 [[TMP9]], ptr null, align 2 20285bc698SAlexey Bataev; CHECK-NEXT: ret void 21285bc698SAlexey Bataev; 22285bc698SAlexey Bataev %1 = zext i8 0 to i32 23285bc698SAlexey Bataev %.not = icmp sgt i32 0, %1 24285bc698SAlexey Bataev %2 = zext i8 0 to i32 25285bc698SAlexey Bataev %3 = select i1 %.not, i32 0, i32 0 26285bc698SAlexey Bataev %4 = zext i8 0 to i32 27285bc698SAlexey Bataev %.not.1 = icmp sgt i32 0, %4 28285bc698SAlexey Bataev %5 = zext i8 0 to i32 29285bc698SAlexey Bataev %6 = select i1 %.not.1, i32 0, i32 %5 30285bc698SAlexey Bataev %7 = xor i32 %6, %3 31285bc698SAlexey Bataev %8 = zext i8 0 to i32 32285bc698SAlexey Bataev %.not.2 = icmp sgt i32 0, %8 33285bc698SAlexey Bataev %9 = select i1 %.not.2, i32 0, i32 0 34285bc698SAlexey Bataev %10 = xor i32 %9, %7 35285bc698SAlexey Bataev %11 = zext i8 0 to i32 36285bc698SAlexey Bataev %.not.3 = icmp sgt i32 0, %11 37285bc698SAlexey Bataev %12 = select i1 %.not.3, i32 0, i32 0 38285bc698SAlexey Bataev %13 = xor i32 %12, %10 39285bc698SAlexey Bataev %14 = select i1 false, i32 0, i32 0 40285bc698SAlexey Bataev %15 = xor i32 %14, %13 41285bc698SAlexey Bataev %16 = select i1 false, i32 0, i32 %2 42285bc698SAlexey Bataev %17 = xor i32 %16, %15 43285bc698SAlexey Bataev %18 = select i1 false, i32 0, i32 %5 44285bc698SAlexey Bataev %19 = xor i32 %18, %17 45285bc698SAlexey Bataev %20 = trunc i32 %19 to i16 46285bc698SAlexey Bataev store i16 %20, ptr null, align 2 47285bc698SAlexey Bataev ret void 48285bc698SAlexey Bataev} 49