1552c8eb7SAlexey Bataev; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 2552c8eb7SAlexey Bataev; RUN: opt -S -mtriple=riscv64-unknown-linux-gnu -mattr="+v" --passes=slp-vectorizer < %s | FileCheck %s 3552c8eb7SAlexey Bataev 4552c8eb7SAlexey Bataevdefine i32 @test(ptr %0, ptr %1) { 5552c8eb7SAlexey Bataev; CHECK-LABEL: define i32 @test( 6552c8eb7SAlexey Bataev; CHECK-SAME: ptr [[TMP0:%.*]], ptr [[TMP1:%.*]]) #[[ATTR0:[0-9]+]] { 7552c8eb7SAlexey Bataev; CHECK-NEXT: entry: 8552c8eb7SAlexey Bataev; CHECK-NEXT: [[LOAD_5:%.*]] = load i32, ptr [[TMP1]], align 4 9*38fffa63SPaul Walker; CHECK-NEXT: [[TMP2:%.*]] = call i8 @llvm.vector.reduce.and.v4i8(<4 x i8> splat (i8 1)) 10d94dc5f0SAlexey Bataev; CHECK-NEXT: [[TMP3:%.*]] = sext i8 [[TMP2]] to i32 11552c8eb7SAlexey Bataev; CHECK-NEXT: [[OP_RDX:%.*]] = and i32 [[TMP3]], [[LOAD_5]] 12552c8eb7SAlexey Bataev; CHECK-NEXT: ret i32 [[OP_RDX]] 13552c8eb7SAlexey Bataev; 14552c8eb7SAlexey Bataeventry: 15552c8eb7SAlexey Bataev %zext.0 = zext i8 1 to i32 16552c8eb7SAlexey Bataev %zext.1 = zext i8 1 to i32 17552c8eb7SAlexey Bataev %zext.2 = zext i8 1 to i32 18552c8eb7SAlexey Bataev %zext.3 = zext i8 1 to i32 19552c8eb7SAlexey Bataev %select.zext.0 = select i1 false, i32 -1, i32 %zext.0 20552c8eb7SAlexey Bataev %select.zext.1 = select i1 false, i32 0, i32 %zext.1 21552c8eb7SAlexey Bataev %select.zext.2 = select i1 false, i32 0, i32 %zext.2 22552c8eb7SAlexey Bataev %select.zext.3 = select i1 false, i32 0, i32 %zext.3 23552c8eb7SAlexey Bataev 24552c8eb7SAlexey Bataev %load.5 = load i32, ptr %1, align 4 25552c8eb7SAlexey Bataev 26552c8eb7SAlexey Bataev %and.0 = and i32 %load.5, %select.zext.0 27552c8eb7SAlexey Bataev %and.1 = and i32 %and.0, %select.zext.1 28552c8eb7SAlexey Bataev %and.2 = and i32 %and.1, %select.zext.2 29552c8eb7SAlexey Bataev %and.3 = and i32 %and.2, %select.zext.3 30552c8eb7SAlexey Bataev 31552c8eb7SAlexey Bataev ret i32 %and.3 32552c8eb7SAlexey Bataev} 33552c8eb7SAlexey Bataev 34