1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 2; RUN: opt -passes=loop-vectorize -force-vector-width=4 -S %s | FileCheck %s 3 4target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" 5 6define void @test_versioned_with_sext_use(i32 %offset, ptr %dst) { 7; CHECK-LABEL: define void @test_versioned_with_sext_use( 8; CHECK-SAME: i32 [[OFFSET:%.*]], ptr [[DST:%.*]]) { 9; CHECK-NEXT: entry: 10; CHECK-NEXT: [[OFFSET_EXT:%.*]] = sext i32 [[OFFSET]] to i64 11; CHECK-NEXT: br label [[OUTER_HEADER:%.*]] 12; CHECK: outer.header.loopexit: 13; CHECK-NEXT: [[IV_2_NEXT_LCSSA:%.*]] = phi i64 [ [[IV_2_NEXT:%.*]], [[INNER_LOOP:%.*]] ], [ [[IND_END:%.*]], [[MIDDLE_BLOCK:%.*]] ] 14; CHECK-NEXT: br label [[OUTER_HEADER]] 15; CHECK: outer.header: 16; CHECK-NEXT: [[IV_1:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_2_NEXT_LCSSA]], [[OUTER_HEADER_LOOPEXIT:%.*]] ] 17; CHECK-NEXT: [[C:%.*]] = call i1 @cond() 18; CHECK-NEXT: br i1 [[C]], label [[INNER_LOOP_PREHEADER:%.*]], label [[EXIT:%.*]] 19; CHECK: inner.loop.preheader: 20; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]] 21; CHECK: vector.scevcheck: 22; CHECK-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i32 [[OFFSET]], 1 23; CHECK-NEXT: br i1 [[IDENT_CHECK]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] 24; CHECK: vector.ph: 25; CHECK-NEXT: [[TMP0:%.*]] = mul i64 200, [[OFFSET_EXT]] 26; CHECK-NEXT: [[IND_END]] = add i64 [[IV_1]], [[TMP0]] 27; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 28; CHECK: vector.body: 29; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 30; CHECK-NEXT: [[TMP1:%.*]] = mul i64 [[INDEX]], [[OFFSET_EXT]] 31; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i64 [[IV_1]], [[TMP1]] 32; CHECK-NEXT: [[TMP2:%.*]] = mul i64 0, [[OFFSET_EXT]] 33; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[OFFSET_IDX]], [[TMP2]] 34; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP3]] 35; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i32, ptr [[TMP4]], i32 0 36; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr [[TMP5]], align 8 37; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[TMP3]], 1 38; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 39; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], 200 40; CHECK-NEXT: br i1 [[TMP7]], label [[MIDDLE_BLOCK]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] 41; CHECK: middle.block: 42; CHECK-NEXT: br i1 false, label [[OUTER_HEADER_LOOPEXIT]], label [[SCALAR_PH]] 43; CHECK: scalar.ph: 44; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[IV_1]], [[INNER_LOOP_PREHEADER]] ], [ [[IV_1]], [[VECTOR_SCEVCHECK]] ] 45; CHECK-NEXT: [[BC_RESUME_VAL1:%.*]] = phi i32 [ 200, [[MIDDLE_BLOCK]] ], [ 0, [[INNER_LOOP_PREHEADER]] ], [ 0, [[VECTOR_SCEVCHECK]] ] 46; CHECK-NEXT: br label [[INNER_LOOP]] 47; CHECK: inner.loop: 48; CHECK-NEXT: [[IV_2:%.*]] = phi i64 [ [[IV_2_NEXT]], [[INNER_LOOP]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ] 49; CHECK-NEXT: [[IV_3:%.*]] = phi i32 [ [[IV_3_NEXT:%.*]], [[INNER_LOOP]] ], [ [[BC_RESUME_VAL1]], [[SCALAR_PH]] ] 50; CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[DST]], i64 [[IV_2]] 51; CHECK-NEXT: store i32 0, ptr [[GEP]], align 8 52; CHECK-NEXT: [[IV_2_NEXT]] = add i64 [[IV_2]], [[OFFSET_EXT]] 53; CHECK-NEXT: [[IV_3_NEXT]] = add i32 [[IV_3]], 1 54; CHECK-NEXT: [[EC:%.*]] = icmp eq i32 [[IV_3]], 200 55; CHECK-NEXT: br i1 [[EC]], label [[OUTER_HEADER_LOOPEXIT]], label [[INNER_LOOP]], !llvm.loop [[LOOP3:![0-9]+]] 56; CHECK: exit: 57; CHECK-NEXT: ret void 58; 59entry: 60 %offset.ext = sext i32 %offset to i64 61 br label %outer.header 62 63outer.header: 64 %iv.1 = phi i64 [ 0, %entry ], [ %iv.2.next, %inner.loop ] 65 %c = call i1 @cond() 66 br i1 %c, label %inner.loop, label %exit 67 68inner.loop: 69 %iv.2 = phi i64 [ %iv.1, %outer.header ], [ %iv.2.next, %inner.loop ] 70 %iv.3 = phi i32 [ 0, %outer.header ], [ %iv.3.next, %inner.loop ] 71 %gep = getelementptr i32, ptr %dst, i64 %iv.2 72 store i32 0, ptr %gep, align 8 73 %iv.2.next = add i64 %iv.2, %offset.ext 74 %iv.3.next = add i32 %iv.3, 1 75 %ec = icmp eq i32 %iv.3, 200 76 br i1 %ec, label %outer.header, label %inner.loop 77 78exit: 79 ret void 80} 81 82define void @test_versioned_with_zext_use(i32 %offset, ptr %dst) { 83; CHECK-LABEL: define void @test_versioned_with_zext_use( 84; CHECK-SAME: i32 [[OFFSET:%.*]], ptr [[DST:%.*]]) { 85; CHECK-NEXT: entry: 86; CHECK-NEXT: [[OFFSET_EXT:%.*]] = zext i32 [[OFFSET]] to i64 87; CHECK-NEXT: br label [[OUTER_HEADER:%.*]] 88; CHECK: outer.header.loopexit: 89; CHECK-NEXT: [[IV_2_NEXT_LCSSA:%.*]] = phi i64 [ [[IV_2_NEXT:%.*]], [[INNER_LOOP:%.*]] ], [ [[IND_END:%.*]], [[MIDDLE_BLOCK:%.*]] ] 90; CHECK-NEXT: br label [[OUTER_HEADER]] 91; CHECK: outer.header: 92; CHECK-NEXT: [[IV_1:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_2_NEXT_LCSSA]], [[OUTER_HEADER_LOOPEXIT:%.*]] ] 93; CHECK-NEXT: [[C:%.*]] = call i1 @cond() 94; CHECK-NEXT: br i1 [[C]], label [[INNER_LOOP_PREHEADER:%.*]], label [[EXIT:%.*]] 95; CHECK: inner.loop.preheader: 96; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]] 97; CHECK: vector.scevcheck: 98; CHECK-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i32 [[OFFSET]], 1 99; CHECK-NEXT: br i1 [[IDENT_CHECK]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] 100; CHECK: vector.ph: 101; CHECK-NEXT: [[TMP0:%.*]] = mul i64 200, [[OFFSET_EXT]] 102; CHECK-NEXT: [[IND_END]] = add i64 [[IV_1]], [[TMP0]] 103; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 104; CHECK: vector.body: 105; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 106; CHECK-NEXT: [[TMP1:%.*]] = mul i64 [[INDEX]], [[OFFSET_EXT]] 107; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i64 [[IV_1]], [[TMP1]] 108; CHECK-NEXT: [[TMP2:%.*]] = mul i64 0, [[OFFSET_EXT]] 109; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[OFFSET_IDX]], [[TMP2]] 110; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP3]] 111; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i32, ptr [[TMP4]], i32 0 112; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr [[TMP5]], align 8 113; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[TMP3]], 1 114; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 115; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], 200 116; CHECK-NEXT: br i1 [[TMP7]], label [[MIDDLE_BLOCK]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] 117; CHECK: middle.block: 118; CHECK-NEXT: br i1 false, label [[OUTER_HEADER_LOOPEXIT]], label [[SCALAR_PH]] 119; CHECK: scalar.ph: 120; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[IV_1]], [[INNER_LOOP_PREHEADER]] ], [ [[IV_1]], [[VECTOR_SCEVCHECK]] ] 121; CHECK-NEXT: [[BC_RESUME_VAL1:%.*]] = phi i32 [ 200, [[MIDDLE_BLOCK]] ], [ 0, [[INNER_LOOP_PREHEADER]] ], [ 0, [[VECTOR_SCEVCHECK]] ] 122; CHECK-NEXT: br label [[INNER_LOOP]] 123; CHECK: inner.loop: 124; CHECK-NEXT: [[IV_2:%.*]] = phi i64 [ [[IV_2_NEXT]], [[INNER_LOOP]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ] 125; CHECK-NEXT: [[IV_3:%.*]] = phi i32 [ [[IV_3_NEXT:%.*]], [[INNER_LOOP]] ], [ [[BC_RESUME_VAL1]], [[SCALAR_PH]] ] 126; CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[DST]], i64 [[IV_2]] 127; CHECK-NEXT: store i32 0, ptr [[GEP]], align 8 128; CHECK-NEXT: [[IV_2_NEXT]] = add i64 [[IV_2]], [[OFFSET_EXT]] 129; CHECK-NEXT: [[IV_3_NEXT]] = add i32 [[IV_3]], 1 130; CHECK-NEXT: [[EC:%.*]] = icmp eq i32 [[IV_3]], 200 131; CHECK-NEXT: br i1 [[EC]], label [[OUTER_HEADER_LOOPEXIT]], label [[INNER_LOOP]], !llvm.loop [[LOOP5:![0-9]+]] 132; CHECK: exit: 133; CHECK-NEXT: ret void 134; 135entry: 136 %offset.ext = zext i32 %offset to i64 137 br label %outer.header 138 139outer.header: 140 %iv.1 = phi i64 [ 0, %entry ], [ %iv.2.next, %inner.loop ] 141 %c = call i1 @cond() 142 br i1 %c, label %inner.loop, label %exit 143 144inner.loop: 145 %iv.2 = phi i64 [ %iv.1, %outer.header ], [ %iv.2.next, %inner.loop ] 146 %iv.3 = phi i32 [ 0, %outer.header ], [ %iv.3.next, %inner.loop ] 147 %gep = getelementptr i32, ptr %dst, i64 %iv.2 148 store i32 0, ptr %gep, align 8 149 %iv.2.next = add i64 %iv.2, %offset.ext 150 %iv.3.next = add i32 %iv.3, 1 151 %ec = icmp eq i32 %iv.3, 200 152 br i1 %ec, label %outer.header, label %inner.loop 153 154exit: 155 ret void 156} 157 158define void @versioned_sext_use_in_gep(i32 %scale, ptr %dst, i64 %scale.2) { 159; CHECK-LABEL: define void @versioned_sext_use_in_gep( 160; CHECK-SAME: i32 [[SCALE:%.*]], ptr [[DST:%.*]], i64 [[SCALE_2:%.*]]) { 161; CHECK-NEXT: entry: 162; CHECK-NEXT: [[SCALE_EXT:%.*]] = sext i32 [[SCALE]] to i64 163; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]] 164; CHECK: vector.scevcheck: 165; CHECK-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i32 [[SCALE]], 1 166; CHECK-NEXT: br i1 [[IDENT_CHECK]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] 167; CHECK: vector.ph: 168; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 169; CHECK: vector.body: 170; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 171; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[INDEX]], 0 172; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[INDEX]], 1 173; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[INDEX]], 2 174; CHECK-NEXT: [[TMP16:%.*]] = add i64 [[INDEX]], 3 175; CHECK-NEXT: [[TMP11:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP10]] 176; CHECK-NEXT: [[TMP13:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP12]] 177; CHECK-NEXT: [[TMP15:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP14]] 178; CHECK-NEXT: [[TMP17:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP16]] 179; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[DST]], i64 [[SCALE_2]] 180; CHECK-NEXT: store ptr [[TMP8]], ptr [[TMP11]], align 8 181; CHECK-NEXT: store ptr [[TMP8]], ptr [[TMP13]], align 8 182; CHECK-NEXT: store ptr [[TMP8]], ptr [[TMP15]], align 8 183; CHECK-NEXT: store ptr [[TMP8]], ptr [[TMP17]], align 8 184; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 185; CHECK-NEXT: [[TMP18:%.*]] = icmp eq i64 [[INDEX_NEXT]], 256 186; CHECK-NEXT: br i1 [[TMP18]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]] 187; CHECK: middle.block: 188; CHECK-NEXT: br i1 true, label [[EXIT:%.*]], label [[SCALAR_PH]] 189; CHECK: scalar.ph: 190; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 256, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ], [ 0, [[VECTOR_SCEVCHECK]] ] 191; CHECK-NEXT: br label [[LOOP:%.*]] 192; CHECK: loop: 193; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] 194; CHECK-NEXT: [[IV_MUL:%.*]] = mul i64 [[IV]], [[SCALE_EXT]] 195; CHECK-NEXT: [[GEP_1:%.*]] = getelementptr i8, ptr [[DST]], i64 [[IV_MUL]] 196; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 197; CHECK-NEXT: [[SCALE_MUL:%.*]] = mul i64 [[SCALE_EXT]], [[SCALE_2]] 198; CHECK-NEXT: [[GEP_2:%.*]] = getelementptr i8, ptr [[DST]], i64 [[SCALE_MUL]] 199; CHECK-NEXT: store ptr [[GEP_2]], ptr [[GEP_1]], align 8 200; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], 256 201; CHECK-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP7:![0-9]+]] 202; CHECK: exit: 203; CHECK-NEXT: ret void 204; 205entry: 206 %scale.ext = sext i32 %scale to i64 207 br label %loop 208 209loop: 210 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] 211 %iv.mul = mul i64 %iv, %scale.ext 212 %gep.1 = getelementptr i8, ptr %dst, i64 %iv.mul 213 %iv.next = add i64 %iv, 1 214 %scale.mul = mul i64 %scale.ext, %scale.2 215 %gep.2 = getelementptr i8, ptr %dst, i64 %scale.mul 216 store ptr %gep.2, ptr %gep.1, align 8 217 %ec = icmp eq i64 %iv.next, 256 218 br i1 %ec, label %exit, label %loop 219 220exit: 221 ret void 222} 223 224declare i1 @cond() 225 226define void @test_versioned_with_different_uses(i32 %offset, ptr noalias %dst.1, ptr %dst.2) { 227; CHECK-LABEL: define void @test_versioned_with_different_uses( 228; CHECK-SAME: i32 [[OFFSET:%.*]], ptr noalias [[DST_1:%.*]], ptr [[DST_2:%.*]]) { 229; CHECK-NEXT: entry: 230; CHECK-NEXT: [[OFFSET_EXT:%.*]] = zext i32 [[OFFSET]] to i64 231; CHECK-NEXT: br label [[OUTER_HEADER:%.*]] 232; CHECK: outer.header.loopexit: 233; CHECK-NEXT: [[IV_2_NEXT_LCSSA:%.*]] = phi i64 [ [[IV_2_NEXT:%.*]], [[INNER_LOOP:%.*]] ], [ [[IND_END:%.*]], [[MIDDLE_BLOCK:%.*]] ] 234; CHECK-NEXT: br label [[OUTER_HEADER]] 235; CHECK: outer.header: 236; CHECK-NEXT: [[IV_1:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_2_NEXT_LCSSA]], [[OUTER_HEADER_LOOPEXIT:%.*]] ] 237; CHECK-NEXT: [[C:%.*]] = call i1 @cond() 238; CHECK-NEXT: br i1 [[C]], label [[INNER_LOOP_PREHEADER:%.*]], label [[EXIT:%.*]] 239; CHECK: inner.loop.preheader: 240; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]] 241; CHECK: vector.scevcheck: 242; CHECK-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i32 [[OFFSET]], 1 243; CHECK-NEXT: br i1 [[IDENT_CHECK]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] 244; CHECK: vector.ph: 245; CHECK-NEXT: [[TMP0:%.*]] = mul i64 200, [[OFFSET_EXT]] 246; CHECK-NEXT: [[IND_END]] = add i64 [[IV_1]], [[TMP0]] 247; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 248; CHECK: vector.body: 249; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 250; CHECK-NEXT: [[TMP1:%.*]] = mul i64 [[INDEX]], [[OFFSET_EXT]] 251; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i64 [[IV_1]], [[TMP1]] 252; CHECK-NEXT: [[TMP2:%.*]] = mul i64 0, [[OFFSET_EXT]] 253; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[OFFSET_IDX]], [[TMP2]] 254; CHECK-NEXT: [[OFFSET_IDX2:%.*]] = trunc i64 [[INDEX]] to i32 255; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[OFFSET_IDX2]], 0 256; CHECK-NEXT: [[TMP5:%.*]] = add i32 [[OFFSET_IDX2]], 1 257; CHECK-NEXT: [[TMP6:%.*]] = add i32 [[OFFSET_IDX2]], 2 258; CHECK-NEXT: [[TMP7:%.*]] = add i32 [[OFFSET_IDX2]], 3 259; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[DST_1]], i32 [[TMP4]] 260; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[DST_1]], i32 [[TMP5]] 261; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[DST_1]], i32 [[TMP6]] 262; CHECK-NEXT: [[TMP11:%.*]] = getelementptr i8, ptr [[DST_1]], i32 [[TMP7]] 263; CHECK-NEXT: store i32 0, ptr [[TMP8]], align 8 264; CHECK-NEXT: store i32 0, ptr [[TMP9]], align 8 265; CHECK-NEXT: store i32 0, ptr [[TMP10]], align 8 266; CHECK-NEXT: store i32 0, ptr [[TMP11]], align 8 267; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i32, ptr [[DST_2]], i64 [[TMP3]] 268; CHECK-NEXT: [[TMP13:%.*]] = getelementptr i32, ptr [[TMP12]], i32 0 269; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr [[TMP13]], align 8 270; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[TMP3]], 1 271; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 272; CHECK-NEXT: [[TMP15:%.*]] = icmp eq i64 [[INDEX_NEXT]], 200 273; CHECK-NEXT: br i1 [[TMP15]], label [[MIDDLE_BLOCK]], label [[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]] 274; CHECK: middle.block: 275; CHECK-NEXT: br i1 false, label [[OUTER_HEADER_LOOPEXIT]], label [[SCALAR_PH]] 276; CHECK: scalar.ph: 277; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[IV_1]], [[INNER_LOOP_PREHEADER]] ], [ [[IV_1]], [[VECTOR_SCEVCHECK]] ] 278; CHECK-NEXT: [[BC_RESUME_VAL1:%.*]] = phi i32 [ 200, [[MIDDLE_BLOCK]] ], [ 0, [[INNER_LOOP_PREHEADER]] ], [ 0, [[VECTOR_SCEVCHECK]] ] 279; CHECK-NEXT: br label [[INNER_LOOP]] 280; CHECK: inner.loop: 281; CHECK-NEXT: [[IV_2:%.*]] = phi i64 [ [[IV_2_NEXT]], [[INNER_LOOP]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ] 282; CHECK-NEXT: [[IV_3:%.*]] = phi i32 [ [[IV_3_NEXT:%.*]], [[INNER_LOOP]] ], [ [[BC_RESUME_VAL1]], [[SCALAR_PH]] ] 283; CHECK-NEXT: [[IV_MUL:%.*]] = mul i32 [[IV_3]], [[OFFSET]] 284; CHECK-NEXT: [[GEP_MUL:%.*]] = getelementptr i8, ptr [[DST_1]], i32 [[IV_MUL]] 285; CHECK-NEXT: store i32 0, ptr [[GEP_MUL]], align 8 286; CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[DST_2]], i64 [[IV_2]] 287; CHECK-NEXT: store i32 0, ptr [[GEP]], align 8 288; CHECK-NEXT: [[IV_2_NEXT]] = add i64 [[IV_2]], [[OFFSET_EXT]] 289; CHECK-NEXT: [[IV_3_NEXT]] = add i32 [[IV_3]], 1 290; CHECK-NEXT: [[EC:%.*]] = icmp eq i32 [[IV_3]], 200 291; CHECK-NEXT: br i1 [[EC]], label [[OUTER_HEADER_LOOPEXIT]], label [[INNER_LOOP]], !llvm.loop [[LOOP9:![0-9]+]] 292; CHECK: exit: 293; CHECK-NEXT: ret void 294; 295entry: 296 %offset.ext = zext i32 %offset to i64 297 br label %outer.header 298 299outer.header: 300 %iv.1 = phi i64 [ 0, %entry ], [ %iv.2.next, %inner.loop ] 301 %c = call i1 @cond() 302 br i1 %c, label %inner.loop, label %exit 303 304inner.loop: 305 %iv.2 = phi i64 [ %iv.1, %outer.header ], [ %iv.2.next, %inner.loop ] 306 %iv.3 = phi i32 [ 0, %outer.header ], [ %iv.3.next, %inner.loop ] 307 %iv.mul = mul i32 %iv.3, %offset 308 %gep.mul = getelementptr i8, ptr %dst.1, i32 %iv.mul 309 store i32 0, ptr %gep.mul, align 8 310 %gep = getelementptr i32, ptr %dst.2, i64 %iv.2 311 store i32 0, ptr %gep, align 8 312 %iv.2.next = add i64 %iv.2, %offset.ext 313 %iv.3.next = add i32 %iv.3, 1 314 %ec = icmp eq i32 %iv.3, 200 315 br i1 %ec, label %outer.header, label %inner.loop 316 317exit: 318 ret void 319} 320 321define void @test_versioned_with_non_ex_use(i32 %offset, ptr noalias %dst.1, ptr %dst.2) { 322; CHECK-LABEL: define void @test_versioned_with_non_ex_use( 323; CHECK-SAME: i32 [[OFFSET:%.*]], ptr noalias [[DST_1:%.*]], ptr [[DST_2:%.*]]) { 324; CHECK-NEXT: entry: 325; CHECK-NEXT: [[OFFSET_EXT:%.*]] = zext i32 [[OFFSET]] to i64 326; CHECK-NEXT: [[ADD:%.*]] = add i32 [[OFFSET]], 3 327; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]] 328; CHECK: vector.scevcheck: 329; CHECK-NEXT: [[TMP0:%.*]] = sub i32 -3, [[OFFSET]] 330; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[ADD]], 0 331; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[TMP0]], i32 [[ADD]] 332; CHECK-NEXT: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 [[TMP2]], i32 200) 333; CHECK-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i32, i1 } [[MUL]], 0 334; CHECK-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i32, i1 } [[MUL]], 1 335; CHECK-NEXT: [[TMP3:%.*]] = sub i32 0, [[MUL_RESULT]] 336; CHECK-NEXT: [[TMP4:%.*]] = icmp slt i32 [[MUL_RESULT]], 0 337; CHECK-NEXT: [[TMP5:%.*]] = icmp sgt i32 [[TMP3]], 0 338; CHECK-NEXT: [[TMP6:%.*]] = select i1 [[TMP1]], i1 [[TMP5]], i1 [[TMP4]] 339; CHECK-NEXT: [[TMP7:%.*]] = or i1 [[TMP6]], [[MUL_OVERFLOW]] 340; CHECK-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i32 [[OFFSET]], 1 341; CHECK-NEXT: [[TMP8:%.*]] = or i1 [[TMP7]], [[IDENT_CHECK]] 342; CHECK-NEXT: br i1 [[TMP8]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] 343; CHECK: vector.ph: 344; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[ADD]], i64 0 345; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer 346; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 347; CHECK: vector.body: 348; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 349; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ] 350; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[INDEX]], 0 351; CHECK-NEXT: [[TMP10:%.*]] = mul <4 x i32> [[VEC_IND]], [[BROADCAST_SPLAT]] 352; CHECK-NEXT: [[TMP11:%.*]] = extractelement <4 x i32> [[TMP10]], i32 0 353; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[DST_1]], i32 [[TMP11]] 354; CHECK-NEXT: [[TMP13:%.*]] = extractelement <4 x i32> [[TMP10]], i32 1 355; CHECK-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[DST_1]], i32 [[TMP13]] 356; CHECK-NEXT: [[TMP15:%.*]] = extractelement <4 x i32> [[TMP10]], i32 2 357; CHECK-NEXT: [[TMP16:%.*]] = getelementptr i8, ptr [[DST_1]], i32 [[TMP15]] 358; CHECK-NEXT: [[TMP17:%.*]] = extractelement <4 x i32> [[TMP10]], i32 3 359; CHECK-NEXT: [[TMP18:%.*]] = getelementptr i8, ptr [[DST_1]], i32 [[TMP17]] 360; CHECK-NEXT: store i32 0, ptr [[TMP12]], align 8 361; CHECK-NEXT: store i32 0, ptr [[TMP14]], align 8 362; CHECK-NEXT: store i32 0, ptr [[TMP16]], align 8 363; CHECK-NEXT: store i32 0, ptr [[TMP18]], align 8 364; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i32, ptr [[DST_2]], i64 [[TMP9]] 365; CHECK-NEXT: [[TMP21:%.*]] = getelementptr i32, ptr [[TMP20]], i32 0 366; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr [[TMP21]], align 8 367; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 368; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], <i32 4, i32 4, i32 4, i32 4> 369; CHECK-NEXT: [[TMP22:%.*]] = icmp eq i64 [[INDEX_NEXT]], 200 370; CHECK-NEXT: br i1 [[TMP22]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]] 371; CHECK: middle.block: 372; CHECK-NEXT: br i1 false, label [[EXIT:%.*]], label [[SCALAR_PH]] 373; CHECK: scalar.ph: 374; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 200, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ], [ 0, [[VECTOR_SCEVCHECK]] ] 375; CHECK-NEXT: [[BC_RESUME_VAL1:%.*]] = phi i32 [ 200, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ], [ 0, [[VECTOR_SCEVCHECK]] ] 376; CHECK-NEXT: br label [[LOOP:%.*]] 377; CHECK: loop: 378; CHECK-NEXT: [[IV_2:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_2_NEXT:%.*]], [[LOOP]] ] 379; CHECK-NEXT: [[IV_3:%.*]] = phi i32 [ [[BC_RESUME_VAL1]], [[SCALAR_PH]] ], [ [[IV_3_NEXT:%.*]], [[LOOP]] ] 380; CHECK-NEXT: [[IV_MUL:%.*]] = mul i32 [[IV_3]], [[ADD]] 381; CHECK-NEXT: [[GEP_MUL:%.*]] = getelementptr i8, ptr [[DST_1]], i32 [[IV_MUL]] 382; CHECK-NEXT: store i32 0, ptr [[GEP_MUL]], align 8 383; CHECK-NEXT: [[IV_2_MUL:%.*]] = mul i64 [[IV_2]], [[OFFSET_EXT]] 384; CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[DST_2]], i64 [[IV_2_MUL]] 385; CHECK-NEXT: store i32 0, ptr [[GEP]], align 8 386; CHECK-NEXT: [[IV_2_NEXT]] = add i64 [[IV_2]], 1 387; CHECK-NEXT: [[IV_3_NEXT]] = add i32 [[IV_3]], 1 388; CHECK-NEXT: [[EC:%.*]] = icmp eq i32 [[IV_3]], 200 389; CHECK-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP11:![0-9]+]] 390; CHECK: exit: 391; CHECK-NEXT: ret void 392; 393entry: 394 %offset.ext = zext i32 %offset to i64 395 %add = add i32 %offset, 3 396 br label %loop 397 398loop: 399 %iv.2 = phi i64 [ 0, %entry ], [ %iv.2.next, %loop ] 400 %iv.3 = phi i32 [ 0, %entry ], [ %iv.3.next, %loop ] 401 %iv.mul = mul i32 %iv.3, %add 402 %gep.mul = getelementptr i8, ptr %dst.1, i32 %iv.mul 403 store i32 0, ptr %gep.mul, align 8 404 %iv.2.mul = mul i64 %iv.2, %offset.ext 405 %gep = getelementptr i32, ptr %dst.2, i64 %iv.2.mul 406 store i32 0, ptr %gep, align 8 407 %iv.2.next = add i64 %iv.2, 1 408 %iv.3.next = add i32 %iv.3, 1 409 %ec = icmp eq i32 %iv.3, 200 410 br i1 %ec, label %exit, label %loop 411 412exit: 413 ret void 414} 415 416; Test case to make sure that uses of versioned strides of type i1 are properly 417; extended. From https://github.com/llvm/llvm-project/issues/91369. 418; FIXME: Currently miscompiled. 419define void @zext_of_i1_stride(i1 %g, ptr %dst) mustprogress { 420; CHECK-LABEL: define void @zext_of_i1_stride( 421; CHECK-SAME: i1 [[G:%.*]], ptr [[DST:%.*]]) #[[ATTR0:[0-9]+]] { 422; CHECK-NEXT: entry: 423; CHECK-NEXT: [[G_16:%.*]] = zext i1 [[G]] to i16 424; CHECK-NEXT: [[G_64:%.*]] = zext i1 [[G]] to i64 425; CHECK-NEXT: [[TMP0:%.*]] = udiv i64 15, [[G_64]] 426; CHECK-NEXT: [[TMP1:%.*]] = add nuw nsw i64 [[TMP0]], 1 427; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 4 428; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]] 429; CHECK: vector.scevcheck: 430; CHECK-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i1 [[G]], true 431; CHECK-NEXT: br i1 [[IDENT_CHECK]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] 432; CHECK: vector.ph: 433; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP1]], 4 434; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP1]], [[N_MOD_VF]] 435; CHECK-NEXT: [[IND_END:%.*]] = mul i64 [[N_VEC]], [[G_64]] 436; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 437; CHECK: vector.body: 438; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 439; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], [[G_64]] 440; CHECK-NEXT: [[TMP2:%.*]] = mul i64 0, [[G_64]] 441; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[OFFSET_IDX]], [[TMP2]] 442; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i16, ptr [[DST]], i64 [[TMP3]] 443; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i16, ptr [[TMP4]], i32 0 444; CHECK-NEXT: store <4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>, ptr [[TMP5]], align 2 445; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 446; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 447; CHECK-NEXT: br i1 [[TMP6]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]] 448; CHECK: middle.block: 449; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP1]], [[N_VEC]] 450; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]] 451; CHECK: scalar.ph: 452; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ], [ 0, [[VECTOR_SCEVCHECK]] ] 453; CHECK-NEXT: br label [[LOOP:%.*]] 454; CHECK: loop: 455; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] 456; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i16, ptr [[DST]], i64 [[IV]] 457; CHECK-NEXT: store i16 [[G_16]], ptr [[GEP]], align 2 458; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], [[G_64]] 459; CHECK-NEXT: [[CMP:%.*]] = icmp ult i64 [[IV_NEXT]], 16 460; CHECK-NEXT: br i1 [[CMP]], label [[LOOP]], label [[EXIT]], !llvm.loop [[LOOP13:![0-9]+]] 461; CHECK: exit: 462; CHECK-NEXT: ret void 463; 464entry: 465 %g.16 = zext i1 %g to i16 466 %g.64 = zext i1 %g to i64 467 br label %loop 468 469loop: 470 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] 471 %gep = getelementptr inbounds i16, ptr %dst, i64 %iv 472 store i16 %g.16, ptr %gep, align 2 473 %iv.next = add nuw nsw i64 %iv, %g.64 474 %cmp = icmp ult i64 %iv.next, 16 475 br i1 %cmp, label %loop, label %exit 476 477exit: 478 ret void 479} 480 481; Test case to make sure that uses of versioned strides of type i1 are properly 482; extended. 483define void @sext_of_i1_stride(i1 %g, ptr %dst) mustprogress { 484; CHECK-LABEL: define void @sext_of_i1_stride( 485; CHECK-SAME: i1 [[G:%.*]], ptr [[DST:%.*]]) #[[ATTR0]] { 486; CHECK-NEXT: entry: 487; CHECK-NEXT: [[G_16:%.*]] = sext i1 [[G]] to i16 488; CHECK-NEXT: [[G_64:%.*]] = sext i1 [[G]] to i64 489; CHECK-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[G_64]], i64 16) 490; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[UMAX]], -1 491; CHECK-NEXT: [[TMP1:%.*]] = udiv i64 [[TMP0]], [[G_64]] 492; CHECK-NEXT: [[TMP2:%.*]] = add nuw nsw i64 [[TMP1]], 1 493; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP2]], 4 494; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]] 495; CHECK: vector.scevcheck: 496; CHECK-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i1 [[G]], true 497; CHECK-NEXT: br i1 [[IDENT_CHECK]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] 498; CHECK: vector.ph: 499; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP2]], 4 500; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP2]], [[N_MOD_VF]] 501; CHECK-NEXT: [[IND_END:%.*]] = mul i64 [[N_VEC]], [[G_64]] 502; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 503; CHECK: vector.body: 504; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 505; CHECK-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], [[G_64]] 506; CHECK-NEXT: [[TMP3:%.*]] = mul i64 0, [[G_64]] 507; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[OFFSET_IDX]], [[TMP3]] 508; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i16, ptr [[DST]], i64 [[TMP4]] 509; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i16, ptr [[TMP5]], i32 0 510; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i16, ptr [[TMP6]], i32 -3 511; CHECK-NEXT: store <4 x i16> <i16 -1, i16 -1, i16 -1, i16 -1>, ptr [[TMP7]], align 2 512; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 513; CHECK-NEXT: br i1 true, label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP14:![0-9]+]] 514; CHECK: middle.block: 515; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP2]], [[N_VEC]] 516; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]] 517; CHECK: scalar.ph: 518; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ], [ 0, [[VECTOR_SCEVCHECK]] ] 519; CHECK-NEXT: br label [[LOOP:%.*]] 520; CHECK: loop: 521; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] 522; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i16, ptr [[DST]], i64 [[IV]] 523; CHECK-NEXT: store i16 [[G_16]], ptr [[GEP]], align 2 524; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], [[G_64]] 525; CHECK-NEXT: [[CMP:%.*]] = icmp ult i64 [[IV_NEXT]], 16 526; CHECK-NEXT: br i1 [[CMP]], label [[LOOP]], label [[EXIT]], !llvm.loop [[LOOP15:![0-9]+]] 527; CHECK: exit: 528; CHECK-NEXT: ret void 529; 530entry: 531 %g.16 = sext i1 %g to i16 532 %g.64 = sext i1 %g to i64 533 br label %loop 534 535loop: 536 %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] 537 %gep = getelementptr inbounds i16, ptr %dst, i64 %iv 538 store i16 %g.16, ptr %gep, align 2 539 %iv.next = add nuw nsw i64 %iv, %g.64 540 %cmp = icmp ult i64 %iv.next, 16 541 br i1 %cmp, label %loop, label %exit 542 543exit: 544 ret void 545} 546 547 548;. 549; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]} 550; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1} 551; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"} 552; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]]} 553; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]} 554; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META1]]} 555; CHECK: [[LOOP6]] = distinct !{[[LOOP6]], [[META1]], [[META2]]} 556; CHECK: [[LOOP7]] = distinct !{[[LOOP7]], [[META1]]} 557; CHECK: [[LOOP8]] = distinct !{[[LOOP8]], [[META1]], [[META2]]} 558; CHECK: [[LOOP9]] = distinct !{[[LOOP9]], [[META1]]} 559; CHECK: [[LOOP10]] = distinct !{[[LOOP10]], [[META1]], [[META2]]} 560; CHECK: [[LOOP11]] = distinct !{[[LOOP11]], [[META1]]} 561; CHECK: [[LOOP12]] = distinct !{[[LOOP12]], [[META1]], [[META2]]} 562; CHECK: [[LOOP13]] = distinct !{[[LOOP13]], [[META1]]} 563; CHECK: [[LOOP14]] = distinct !{[[LOOP14]], [[META1]], [[META2]]} 564; CHECK: [[LOOP15]] = distinct !{[[LOOP15]], [[META1]]} 565;. 566