xref: /llvm-project/llvm/test/Transforms/LoopVectorize/version-stride-with-integer-casts.ll (revision c49b74a4e6fff813a9ca402fa6494f80f8f0e3d6) 
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
2; RUN: opt -passes=loop-vectorize -force-vector-width=4 -S %s | FileCheck %s
3
4target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
5
6define void @test_versioned_with_sext_use(i32 %offset, ptr %dst) {
7; CHECK-LABEL: define void @test_versioned_with_sext_use(
8; CHECK-SAME: i32 [[OFFSET:%.*]], ptr [[DST:%.*]]) {
9; CHECK-NEXT:  entry:
10; CHECK-NEXT:    [[OFFSET_EXT:%.*]] = sext i32 [[OFFSET]] to i64
11; CHECK-NEXT:    br label [[OUTER_HEADER:%.*]]
12; CHECK:       outer.header.loopexit:
13; CHECK-NEXT:    [[IV_2_NEXT_LCSSA:%.*]] = phi i64 [ [[IV_2_NEXT:%.*]], [[INNER_LOOP:%.*]] ], [ [[IND_END:%.*]], [[MIDDLE_BLOCK:%.*]] ]
14; CHECK-NEXT:    br label [[OUTER_HEADER]]
15; CHECK:       outer.header:
16; CHECK-NEXT:    [[IV_1:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_2_NEXT_LCSSA]], [[OUTER_HEADER_LOOPEXIT:%.*]] ]
17; CHECK-NEXT:    [[C:%.*]] = call i1 @cond()
18; CHECK-NEXT:    br i1 [[C]], label [[INNER_LOOP_PREHEADER:%.*]], label [[EXIT:%.*]]
19; CHECK:       inner.loop.preheader:
20; CHECK-NEXT:    br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]]
21; CHECK:       vector.scevcheck:
22; CHECK-NEXT:    [[IDENT_CHECK:%.*]] = icmp ne i32 [[OFFSET]], 1
23; CHECK-NEXT:    br i1 [[IDENT_CHECK]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]
24; CHECK:       vector.ph:
25; CHECK-NEXT:    [[TMP0:%.*]] = mul i64 200, [[OFFSET_EXT]]
26; CHECK-NEXT:    [[IND_END]] = add i64 [[IV_1]], [[TMP0]]
27; CHECK-NEXT:    br label [[VECTOR_BODY:%.*]]
28; CHECK:       vector.body:
29; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
30; CHECK-NEXT:    [[TMP1:%.*]] = mul i64 [[INDEX]], [[OFFSET_EXT]]
31; CHECK-NEXT:    [[OFFSET_IDX:%.*]] = add i64 [[IV_1]], [[TMP1]]
32; CHECK-NEXT:    [[TMP2:%.*]] = mul i64 0, [[OFFSET_EXT]]
33; CHECK-NEXT:    [[TMP3:%.*]] = add i64 [[OFFSET_IDX]], [[TMP2]]
34; CHECK-NEXT:    [[TMP4:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP3]]
35; CHECK-NEXT:    [[TMP5:%.*]] = getelementptr i32, ptr [[TMP4]], i32 0
36; CHECK-NEXT:    store <4 x i32> zeroinitializer, ptr [[TMP5]], align 8
37; CHECK-NEXT:    [[TMP6:%.*]] = add i64 [[TMP3]], [[OFFSET_EXT]]
38; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
39; CHECK-NEXT:    [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], 200
40; CHECK-NEXT:    br i1 [[TMP7]], label [[MIDDLE_BLOCK]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
41; CHECK:       middle.block:
42; CHECK-NEXT:    br i1 false, label [[OUTER_HEADER_LOOPEXIT]], label [[SCALAR_PH]]
43; CHECK:       scalar.ph:
44; CHECK-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i64 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[IV_1]], [[INNER_LOOP_PREHEADER]] ], [ [[IV_1]], [[VECTOR_SCEVCHECK]] ]
45; CHECK-NEXT:    [[BC_RESUME_VAL1:%.*]] = phi i32 [ 200, [[MIDDLE_BLOCK]] ], [ 0, [[INNER_LOOP_PREHEADER]] ], [ 0, [[VECTOR_SCEVCHECK]] ]
46; CHECK-NEXT:    br label [[INNER_LOOP]]
47; CHECK:       inner.loop:
48; CHECK-NEXT:    [[IV_2:%.*]] = phi i64 [ [[IV_2_NEXT]], [[INNER_LOOP]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ]
49; CHECK-NEXT:    [[IV_3:%.*]] = phi i32 [ [[IV_3_NEXT:%.*]], [[INNER_LOOP]] ], [ [[BC_RESUME_VAL1]], [[SCALAR_PH]] ]
50; CHECK-NEXT:    [[GEP:%.*]] = getelementptr i32, ptr [[DST]], i64 [[IV_2]]
51; CHECK-NEXT:    store i32 0, ptr [[GEP]], align 8
52; CHECK-NEXT:    [[IV_2_NEXT]] = add i64 [[IV_2]], [[OFFSET_EXT]]
53; CHECK-NEXT:    [[IV_3_NEXT]] = add i32 [[IV_3]], 1
54; CHECK-NEXT:    [[EC:%.*]] = icmp eq i32 [[IV_3]], 200
55; CHECK-NEXT:    br i1 [[EC]], label [[OUTER_HEADER_LOOPEXIT]], label [[INNER_LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
56; CHECK:       exit:
57; CHECK-NEXT:    ret void
58;
59entry:
60  %offset.ext = sext i32 %offset to i64
61  br label %outer.header
62
63outer.header:
64  %iv.1 = phi i64 [ 0, %entry ], [ %iv.2.next, %inner.loop ]
65  %c = call i1 @cond()
66  br i1 %c, label %inner.loop, label %exit
67
68inner.loop:
69  %iv.2 = phi i64 [ %iv.1, %outer.header ], [ %iv.2.next, %inner.loop ]
70  %iv.3 = phi i32 [ 0, %outer.header ], [ %iv.3.next, %inner.loop ]
71  %gep = getelementptr i32, ptr %dst, i64 %iv.2
72  store i32 0, ptr %gep, align 8
73  %iv.2.next = add i64 %iv.2, %offset.ext
74  %iv.3.next = add i32 %iv.3, 1
75  %ec = icmp eq i32 %iv.3, 200
76  br i1 %ec, label %outer.header, label %inner.loop
77
78exit:
79  ret void
80}
81
82define void @test_versioned_with_zext_use(i32 %offset, ptr %dst) {
83; CHECK-LABEL: define void @test_versioned_with_zext_use(
84; CHECK-SAME: i32 [[OFFSET:%.*]], ptr [[DST:%.*]]) {
85; CHECK-NEXT:  entry:
86; CHECK-NEXT:    [[OFFSET_EXT:%.*]] = zext i32 [[OFFSET]] to i64
87; CHECK-NEXT:    br label [[OUTER_HEADER:%.*]]
88; CHECK:       outer.header.loopexit:
89; CHECK-NEXT:    [[IV_2_NEXT_LCSSA:%.*]] = phi i64 [ [[IV_2_NEXT:%.*]], [[INNER_LOOP:%.*]] ], [ [[IND_END:%.*]], [[MIDDLE_BLOCK:%.*]] ]
90; CHECK-NEXT:    br label [[OUTER_HEADER]]
91; CHECK:       outer.header:
92; CHECK-NEXT:    [[IV_1:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_2_NEXT_LCSSA]], [[OUTER_HEADER_LOOPEXIT:%.*]] ]
93; CHECK-NEXT:    [[C:%.*]] = call i1 @cond()
94; CHECK-NEXT:    br i1 [[C]], label [[INNER_LOOP_PREHEADER:%.*]], label [[EXIT:%.*]]
95; CHECK:       inner.loop.preheader:
96; CHECK-NEXT:    br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]]
97; CHECK:       vector.scevcheck:
98; CHECK-NEXT:    [[IDENT_CHECK:%.*]] = icmp ne i32 [[OFFSET]], 1
99; CHECK-NEXT:    br i1 [[IDENT_CHECK]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]
100; CHECK:       vector.ph:
101; CHECK-NEXT:    [[TMP0:%.*]] = mul i64 200, [[OFFSET_EXT]]
102; CHECK-NEXT:    [[IND_END]] = add i64 [[IV_1]], [[TMP0]]
103; CHECK-NEXT:    br label [[VECTOR_BODY:%.*]]
104; CHECK:       vector.body:
105; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
106; CHECK-NEXT:    [[TMP1:%.*]] = mul i64 [[INDEX]], [[OFFSET_EXT]]
107; CHECK-NEXT:    [[OFFSET_IDX:%.*]] = add i64 [[IV_1]], [[TMP1]]
108; CHECK-NEXT:    [[TMP2:%.*]] = mul i64 0, [[OFFSET_EXT]]
109; CHECK-NEXT:    [[TMP3:%.*]] = add i64 [[OFFSET_IDX]], [[TMP2]]
110; CHECK-NEXT:    [[TMP4:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP3]]
111; CHECK-NEXT:    [[TMP5:%.*]] = getelementptr i32, ptr [[TMP4]], i32 0
112; CHECK-NEXT:    store <4 x i32> zeroinitializer, ptr [[TMP5]], align 8
113; CHECK-NEXT:    [[TMP6:%.*]] = add i64 [[TMP3]], [[OFFSET_EXT]]
114; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
115; CHECK-NEXT:    [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], 200
116; CHECK-NEXT:    br i1 [[TMP7]], label [[MIDDLE_BLOCK]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
117; CHECK:       middle.block:
118; CHECK-NEXT:    br i1 false, label [[OUTER_HEADER_LOOPEXIT]], label [[SCALAR_PH]]
119; CHECK:       scalar.ph:
120; CHECK-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i64 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[IV_1]], [[INNER_LOOP_PREHEADER]] ], [ [[IV_1]], [[VECTOR_SCEVCHECK]] ]
121; CHECK-NEXT:    [[BC_RESUME_VAL1:%.*]] = phi i32 [ 200, [[MIDDLE_BLOCK]] ], [ 0, [[INNER_LOOP_PREHEADER]] ], [ 0, [[VECTOR_SCEVCHECK]] ]
122; CHECK-NEXT:    br label [[INNER_LOOP]]
123; CHECK:       inner.loop:
124; CHECK-NEXT:    [[IV_2:%.*]] = phi i64 [ [[IV_2_NEXT]], [[INNER_LOOP]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ]
125; CHECK-NEXT:    [[IV_3:%.*]] = phi i32 [ [[IV_3_NEXT:%.*]], [[INNER_LOOP]] ], [ [[BC_RESUME_VAL1]], [[SCALAR_PH]] ]
126; CHECK-NEXT:    [[GEP:%.*]] = getelementptr i32, ptr [[DST]], i64 [[IV_2]]
127; CHECK-NEXT:    store i32 0, ptr [[GEP]], align 8
128; CHECK-NEXT:    [[IV_2_NEXT]] = add i64 [[IV_2]], [[OFFSET_EXT]]
129; CHECK-NEXT:    [[IV_3_NEXT]] = add i32 [[IV_3]], 1
130; CHECK-NEXT:    [[EC:%.*]] = icmp eq i32 [[IV_3]], 200
131; CHECK-NEXT:    br i1 [[EC]], label [[OUTER_HEADER_LOOPEXIT]], label [[INNER_LOOP]], !llvm.loop [[LOOP5:![0-9]+]]
132; CHECK:       exit:
133; CHECK-NEXT:    ret void
134;
135entry:
136  %offset.ext = zext i32 %offset to i64
137  br label %outer.header
138
139outer.header:
140  %iv.1 = phi i64 [ 0, %entry ], [ %iv.2.next, %inner.loop ]
141  %c = call i1 @cond()
142  br i1 %c, label %inner.loop, label %exit
143
144inner.loop:
145  %iv.2 = phi i64 [ %iv.1, %outer.header ], [ %iv.2.next, %inner.loop ]
146  %iv.3 = phi i32 [ 0, %outer.header ], [ %iv.3.next, %inner.loop ]
147  %gep = getelementptr i32, ptr %dst, i64 %iv.2
148  store i32 0, ptr %gep, align 8
149  %iv.2.next = add i64 %iv.2, %offset.ext
150  %iv.3.next = add i32 %iv.3, 1
151  %ec = icmp eq i32 %iv.3, 200
152  br i1 %ec, label %outer.header, label %inner.loop
153
154exit:
155  ret void
156}
157
158define void @versioned_sext_use_in_gep(i32 %scale, ptr %dst, i64 %scale.2) {
159; CHECK-LABEL: define void @versioned_sext_use_in_gep(
160; CHECK-SAME: i32 [[SCALE:%.*]], ptr [[DST:%.*]], i64 [[SCALE_2:%.*]]) {
161; CHECK-NEXT:  entry:
162; CHECK-NEXT:    [[SCALE_EXT:%.*]] = sext i32 [[SCALE]] to i64
163; CHECK-NEXT:    br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]]
164; CHECK:       vector.scevcheck:
165; CHECK-NEXT:    [[IDENT_CHECK:%.*]] = icmp ne i32 [[SCALE]], 1
166; CHECK-NEXT:    br i1 [[IDENT_CHECK]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]
167; CHECK:       vector.ph:
168; CHECK-NEXT:    [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[SCALE_EXT]], i64 0
169; CHECK-NEXT:    [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer
170; CHECK-NEXT:    [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <4 x i64> poison, i64 [[SCALE_2]], i64 0
171; CHECK-NEXT:    [[BROADCAST_SPLAT2:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT1]], <4 x i64> poison, <4 x i32> zeroinitializer
172; CHECK-NEXT:    br label [[VECTOR_BODY:%.*]]
173; CHECK:       vector.body:
174; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
175; CHECK-NEXT:    [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ]
176; CHECK-NEXT:    [[TMP0:%.*]] = mul <4 x i64> [[VEC_IND]], [[BROADCAST_SPLAT]]
177; CHECK-NEXT:    [[TMP1:%.*]] = extractelement <4 x i64> [[TMP0]], i32 0
178; CHECK-NEXT:    [[TMP2:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP1]]
179; CHECK-NEXT:    [[TMP3:%.*]] = extractelement <4 x i64> [[TMP0]], i32 1
180; CHECK-NEXT:    [[TMP4:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP3]]
181; CHECK-NEXT:    [[TMP5:%.*]] = extractelement <4 x i64> [[TMP0]], i32 2
182; CHECK-NEXT:    [[TMP6:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP5]]
183; CHECK-NEXT:    [[TMP7:%.*]] = extractelement <4 x i64> [[TMP0]], i32 3
184; CHECK-NEXT:    [[TMP8:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP7]]
185; CHECK-NEXT:    [[TMP9:%.*]] = mul <4 x i64> [[BROADCAST_SPLAT]], [[BROADCAST_SPLAT2]]
186; CHECK-NEXT:    [[TMP10:%.*]] = extractelement <4 x i64> [[TMP9]], i32 0
187; CHECK-NEXT:    [[TMP11:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP10]]
188; CHECK-NEXT:    [[TMP12:%.*]] = extractelement <4 x i64> [[TMP9]], i32 1
189; CHECK-NEXT:    [[TMP13:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP12]]
190; CHECK-NEXT:    [[TMP14:%.*]] = extractelement <4 x i64> [[TMP9]], i32 2
191; CHECK-NEXT:    [[TMP15:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP14]]
192; CHECK-NEXT:    [[TMP16:%.*]] = extractelement <4 x i64> [[TMP9]], i32 3
193; CHECK-NEXT:    [[TMP17:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP16]]
194; CHECK-NEXT:    store ptr [[TMP11]], ptr [[TMP2]], align 8
195; CHECK-NEXT:    store ptr [[TMP13]], ptr [[TMP4]], align 8
196; CHECK-NEXT:    store ptr [[TMP15]], ptr [[TMP6]], align 8
197; CHECK-NEXT:    store ptr [[TMP17]], ptr [[TMP8]], align 8
198; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
199; CHECK-NEXT:    [[VEC_IND_NEXT]] = add <4 x i64> [[VEC_IND]], <i64 4, i64 4, i64 4, i64 4>
200; CHECK-NEXT:    [[TMP18:%.*]] = icmp eq i64 [[INDEX_NEXT]], 256
201; CHECK-NEXT:    br i1 [[TMP18]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
202; CHECK:       middle.block:
203; CHECK-NEXT:    br i1 true, label [[EXIT:%.*]], label [[SCALAR_PH]]
204; CHECK:       scalar.ph:
205; CHECK-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i64 [ 256, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ], [ 0, [[VECTOR_SCEVCHECK]] ]
206; CHECK-NEXT:    br label [[LOOP:%.*]]
207; CHECK:       loop:
208; CHECK-NEXT:    [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ]
209; CHECK-NEXT:    [[IV_MUL:%.*]] = mul i64 [[IV]], [[SCALE_EXT]]
210; CHECK-NEXT:    [[GEP_1:%.*]] = getelementptr i8, ptr [[DST]], i64 [[IV_MUL]]
211; CHECK-NEXT:    [[IV_NEXT]] = add i64 [[IV]], 1
212; CHECK-NEXT:    [[SCALE_MUL:%.*]] = mul i64 [[SCALE_EXT]], [[SCALE_2]]
213; CHECK-NEXT:    [[GEP_2:%.*]] = getelementptr i8, ptr [[DST]], i64 [[SCALE_MUL]]
214; CHECK-NEXT:    store ptr [[GEP_2]], ptr [[GEP_1]], align 8
215; CHECK-NEXT:    [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], 256
216; CHECK-NEXT:    br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP7:![0-9]+]]
217; CHECK:       exit:
218; CHECK-NEXT:    ret void
219;
220entry:
221  %scale.ext = sext i32 %scale to i64
222  br label %loop
223
224loop:
225  %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
226  %iv.mul  = mul i64 %iv, %scale.ext
227  %gep.1 = getelementptr i8, ptr %dst, i64 %iv.mul
228  %iv.next = add i64 %iv, 1
229  %scale.mul = mul i64 %scale.ext, %scale.2
230  %gep.2 = getelementptr i8, ptr %dst, i64 %scale.mul
231  store ptr %gep.2, ptr %gep.1, align 8
232  %ec = icmp eq i64 %iv.next, 256
233  br i1 %ec, label %exit, label %loop
234
235exit:
236  ret void
237}
238
239declare i1 @cond()
240
241define void @test_versioned_with_different_uses(i32 %offset, ptr noalias %dst.1, ptr %dst.2) {
242; CHECK-LABEL: define void @test_versioned_with_different_uses(
243; CHECK-SAME: i32 [[OFFSET:%.*]], ptr noalias [[DST_1:%.*]], ptr [[DST_2:%.*]]) {
244; CHECK-NEXT:  entry:
245; CHECK-NEXT:    [[OFFSET_EXT:%.*]] = zext i32 [[OFFSET]] to i64
246; CHECK-NEXT:    br label [[OUTER_HEADER:%.*]]
247; CHECK:       outer.header.loopexit:
248; CHECK-NEXT:    [[IV_2_NEXT_LCSSA:%.*]] = phi i64 [ [[IV_2_NEXT:%.*]], [[INNER_LOOP:%.*]] ], [ [[IND_END:%.*]], [[MIDDLE_BLOCK:%.*]] ]
249; CHECK-NEXT:    br label [[OUTER_HEADER]]
250; CHECK:       outer.header:
251; CHECK-NEXT:    [[IV_1:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_2_NEXT_LCSSA]], [[OUTER_HEADER_LOOPEXIT:%.*]] ]
252; CHECK-NEXT:    [[C:%.*]] = call i1 @cond()
253; CHECK-NEXT:    br i1 [[C]], label [[INNER_LOOP_PREHEADER:%.*]], label [[EXIT:%.*]]
254; CHECK:       inner.loop.preheader:
255; CHECK-NEXT:    br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]]
256; CHECK:       vector.scevcheck:
257; CHECK-NEXT:    [[IDENT_CHECK:%.*]] = icmp ne i32 [[OFFSET]], 1
258; CHECK-NEXT:    br i1 [[IDENT_CHECK]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]
259; CHECK:       vector.ph:
260; CHECK-NEXT:    [[TMP0:%.*]] = mul i64 200, [[OFFSET_EXT]]
261; CHECK-NEXT:    [[IND_END]] = add i64 [[IV_1]], [[TMP0]]
262; CHECK-NEXT:    br label [[VECTOR_BODY:%.*]]
263; CHECK:       vector.body:
264; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
265; CHECK-NEXT:    [[TMP1:%.*]] = mul i64 [[INDEX]], [[OFFSET_EXT]]
266; CHECK-NEXT:    [[OFFSET_IDX:%.*]] = add i64 [[IV_1]], [[TMP1]]
267; CHECK-NEXT:    [[TMP2:%.*]] = mul i64 0, [[OFFSET_EXT]]
268; CHECK-NEXT:    [[TMP3:%.*]] = add i64 [[OFFSET_IDX]], [[TMP2]]
269; CHECK-NEXT:    [[OFFSET_IDX2:%.*]] = trunc i64 [[INDEX]] to i32
270; CHECK-NEXT:    [[TMP4:%.*]] = add i32 [[OFFSET_IDX2]], 0
271; CHECK-NEXT:    [[TMP5:%.*]] = add i32 [[OFFSET_IDX2]], 1
272; CHECK-NEXT:    [[TMP6:%.*]] = add i32 [[OFFSET_IDX2]], 2
273; CHECK-NEXT:    [[TMP7:%.*]] = add i32 [[OFFSET_IDX2]], 3
274; CHECK-NEXT:    [[TMP8:%.*]] = getelementptr i8, ptr [[DST_1]], i32 [[TMP4]]
275; CHECK-NEXT:    [[TMP9:%.*]] = getelementptr i8, ptr [[DST_1]], i32 [[TMP5]]
276; CHECK-NEXT:    [[TMP10:%.*]] = getelementptr i8, ptr [[DST_1]], i32 [[TMP6]]
277; CHECK-NEXT:    [[TMP11:%.*]] = getelementptr i8, ptr [[DST_1]], i32 [[TMP7]]
278; CHECK-NEXT:    store i32 0, ptr [[TMP8]], align 8
279; CHECK-NEXT:    store i32 0, ptr [[TMP9]], align 8
280; CHECK-NEXT:    store i32 0, ptr [[TMP10]], align 8
281; CHECK-NEXT:    store i32 0, ptr [[TMP11]], align 8
282; CHECK-NEXT:    [[TMP12:%.*]] = getelementptr i32, ptr [[DST_2]], i64 [[TMP3]]
283; CHECK-NEXT:    [[TMP13:%.*]] = getelementptr i32, ptr [[TMP12]], i32 0
284; CHECK-NEXT:    store <4 x i32> zeroinitializer, ptr [[TMP13]], align 8
285; CHECK-NEXT:    [[TMP14:%.*]] = add i64 [[TMP3]], [[OFFSET_EXT]]
286; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
287; CHECK-NEXT:    [[TMP15:%.*]] = icmp eq i64 [[INDEX_NEXT]], 200
288; CHECK-NEXT:    br i1 [[TMP15]], label [[MIDDLE_BLOCK]], label [[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]]
289; CHECK:       middle.block:
290; CHECK-NEXT:    br i1 false, label [[OUTER_HEADER_LOOPEXIT]], label [[SCALAR_PH]]
291; CHECK:       scalar.ph:
292; CHECK-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i64 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[IV_1]], [[INNER_LOOP_PREHEADER]] ], [ [[IV_1]], [[VECTOR_SCEVCHECK]] ]
293; CHECK-NEXT:    [[BC_RESUME_VAL1:%.*]] = phi i32 [ 200, [[MIDDLE_BLOCK]] ], [ 0, [[INNER_LOOP_PREHEADER]] ], [ 0, [[VECTOR_SCEVCHECK]] ]
294; CHECK-NEXT:    br label [[INNER_LOOP]]
295; CHECK:       inner.loop:
296; CHECK-NEXT:    [[IV_2:%.*]] = phi i64 [ [[IV_2_NEXT]], [[INNER_LOOP]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ]
297; CHECK-NEXT:    [[IV_3:%.*]] = phi i32 [ [[IV_3_NEXT:%.*]], [[INNER_LOOP]] ], [ [[BC_RESUME_VAL1]], [[SCALAR_PH]] ]
298; CHECK-NEXT:    [[IV_MUL:%.*]] = mul i32 [[IV_3]], [[OFFSET]]
299; CHECK-NEXT:    [[GEP_MUL:%.*]] = getelementptr i8, ptr [[DST_1]], i32 [[IV_MUL]]
300; CHECK-NEXT:    store i32 0, ptr [[GEP_MUL]], align 8
301; CHECK-NEXT:    [[GEP:%.*]] = getelementptr i32, ptr [[DST_2]], i64 [[IV_2]]
302; CHECK-NEXT:    store i32 0, ptr [[GEP]], align 8
303; CHECK-NEXT:    [[IV_2_NEXT]] = add i64 [[IV_2]], [[OFFSET_EXT]]
304; CHECK-NEXT:    [[IV_3_NEXT]] = add i32 [[IV_3]], 1
305; CHECK-NEXT:    [[EC:%.*]] = icmp eq i32 [[IV_3]], 200
306; CHECK-NEXT:    br i1 [[EC]], label [[OUTER_HEADER_LOOPEXIT]], label [[INNER_LOOP]], !llvm.loop [[LOOP9:![0-9]+]]
307; CHECK:       exit:
308; CHECK-NEXT:    ret void
309;
310entry:
311  %offset.ext = zext i32 %offset to i64
312  br label %outer.header
313
314outer.header:
315  %iv.1 = phi i64 [ 0, %entry ], [ %iv.2.next, %inner.loop ]
316  %c = call i1 @cond()
317  br i1 %c, label %inner.loop, label %exit
318
319inner.loop:
320  %iv.2 = phi i64 [ %iv.1, %outer.header ], [ %iv.2.next, %inner.loop ]
321  %iv.3 = phi i32 [ 0, %outer.header ], [ %iv.3.next, %inner.loop ]
322  %iv.mul  = mul i32 %iv.3, %offset
323  %gep.mul = getelementptr i8, ptr %dst.1, i32 %iv.mul
324  store i32 0, ptr %gep.mul, align 8
325  %gep = getelementptr i32, ptr %dst.2, i64 %iv.2
326  store i32 0, ptr %gep, align 8
327  %iv.2.next = add i64 %iv.2, %offset.ext
328  %iv.3.next = add i32 %iv.3, 1
329  %ec = icmp eq i32 %iv.3, 200
330  br i1 %ec, label %outer.header, label %inner.loop
331
332exit:
333  ret void
334}
335
336define void @test_versioned_with_non_ex_use(i32 %offset, ptr noalias %dst.1, ptr %dst.2) {
337; CHECK-LABEL: define void @test_versioned_with_non_ex_use(
338; CHECK-SAME: i32 [[OFFSET:%.*]], ptr noalias [[DST_1:%.*]], ptr [[DST_2:%.*]]) {
339; CHECK-NEXT:  entry:
340; CHECK-NEXT:    [[OFFSET_EXT:%.*]] = zext i32 [[OFFSET]] to i64
341; CHECK-NEXT:    [[ADD:%.*]] = add i32 [[OFFSET]], 3
342; CHECK-NEXT:    br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]]
343; CHECK:       vector.scevcheck:
344; CHECK-NEXT:    [[TMP0:%.*]] = sub i32 -3, [[OFFSET]]
345; CHECK-NEXT:    [[TMP1:%.*]] = icmp slt i32 [[ADD]], 0
346; CHECK-NEXT:    [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[TMP0]], i32 [[ADD]]
347; CHECK-NEXT:    [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 [[TMP2]], i32 200)
348; CHECK-NEXT:    [[MUL_RESULT:%.*]] = extractvalue { i32, i1 } [[MUL]], 0
349; CHECK-NEXT:    [[MUL_OVERFLOW:%.*]] = extractvalue { i32, i1 } [[MUL]], 1
350; CHECK-NEXT:    [[TMP3:%.*]] = sub i32 0, [[MUL_RESULT]]
351; CHECK-NEXT:    [[TMP4:%.*]] = icmp slt i32 [[MUL_RESULT]], 0
352; CHECK-NEXT:    [[TMP5:%.*]] = icmp sgt i32 [[TMP3]], 0
353; CHECK-NEXT:    [[TMP6:%.*]] = select i1 [[TMP1]], i1 [[TMP5]], i1 [[TMP4]]
354; CHECK-NEXT:    [[TMP7:%.*]] = or i1 [[TMP6]], [[MUL_OVERFLOW]]
355; CHECK-NEXT:    [[IDENT_CHECK:%.*]] = icmp ne i32 [[OFFSET]], 1
356; CHECK-NEXT:    [[TMP8:%.*]] = or i1 [[TMP7]], [[IDENT_CHECK]]
357; CHECK-NEXT:    br i1 [[TMP8]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]
358; CHECK:       vector.ph:
359; CHECK-NEXT:    [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[ADD]], i64 0
360; CHECK-NEXT:    [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer
361; CHECK-NEXT:    br label [[VECTOR_BODY:%.*]]
362; CHECK:       vector.body:
363; CHECK-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
364; CHECK-NEXT:    [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ]
365; CHECK-NEXT:    [[TMP9:%.*]] = add i64 [[INDEX]], 0
366; CHECK-NEXT:    [[TMP10:%.*]] = mul <4 x i32> [[VEC_IND]], [[BROADCAST_SPLAT]]
367; CHECK-NEXT:    [[TMP11:%.*]] = extractelement <4 x i32> [[TMP10]], i32 0
368; CHECK-NEXT:    [[TMP12:%.*]] = getelementptr i8, ptr [[DST_1]], i32 [[TMP11]]
369; CHECK-NEXT:    [[TMP13:%.*]] = extractelement <4 x i32> [[TMP10]], i32 1
370; CHECK-NEXT:    [[TMP14:%.*]] = getelementptr i8, ptr [[DST_1]], i32 [[TMP13]]
371; CHECK-NEXT:    [[TMP15:%.*]] = extractelement <4 x i32> [[TMP10]], i32 2
372; CHECK-NEXT:    [[TMP16:%.*]] = getelementptr i8, ptr [[DST_1]], i32 [[TMP15]]
373; CHECK-NEXT:    [[TMP17:%.*]] = extractelement <4 x i32> [[TMP10]], i32 3
374; CHECK-NEXT:    [[TMP18:%.*]] = getelementptr i8, ptr [[DST_1]], i32 [[TMP17]]
375; CHECK-NEXT:    store i32 0, ptr [[TMP12]], align 8
376; CHECK-NEXT:    store i32 0, ptr [[TMP14]], align 8
377; CHECK-NEXT:    store i32 0, ptr [[TMP16]], align 8
378; CHECK-NEXT:    store i32 0, ptr [[TMP18]], align 8
379; CHECK-NEXT:    [[TMP19:%.*]] = mul i64 [[TMP9]], [[OFFSET_EXT]]
380; CHECK-NEXT:    [[TMP20:%.*]] = getelementptr i32, ptr [[DST_2]], i64 [[TMP19]]
381; CHECK-NEXT:    [[TMP21:%.*]] = getelementptr i32, ptr [[TMP20]], i32 0
382; CHECK-NEXT:    store <4 x i32> zeroinitializer, ptr [[TMP21]], align 8
383; CHECK-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
384; CHECK-NEXT:    [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], <i32 4, i32 4, i32 4, i32 4>
385; CHECK-NEXT:    [[TMP22:%.*]] = icmp eq i64 [[INDEX_NEXT]], 200
386; CHECK-NEXT:    br i1 [[TMP22]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]
387; CHECK:       middle.block:
388; CHECK-NEXT:    br i1 false, label [[EXIT:%.*]], label [[SCALAR_PH]]
389; CHECK:       scalar.ph:
390; CHECK-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i64 [ 200, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ], [ 0, [[VECTOR_SCEVCHECK]] ]
391; CHECK-NEXT:    [[BC_RESUME_VAL1:%.*]] = phi i32 [ 200, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ], [ 0, [[VECTOR_SCEVCHECK]] ]
392; CHECK-NEXT:    br label [[LOOP:%.*]]
393; CHECK:       loop:
394; CHECK-NEXT:    [[IV_2:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_2_NEXT:%.*]], [[LOOP]] ]
395; CHECK-NEXT:    [[IV_3:%.*]] = phi i32 [ [[BC_RESUME_VAL1]], [[SCALAR_PH]] ], [ [[IV_3_NEXT:%.*]], [[LOOP]] ]
396; CHECK-NEXT:    [[IV_MUL:%.*]] = mul i32 [[IV_3]], [[ADD]]
397; CHECK-NEXT:    [[GEP_MUL:%.*]] = getelementptr i8, ptr [[DST_1]], i32 [[IV_MUL]]
398; CHECK-NEXT:    store i32 0, ptr [[GEP_MUL]], align 8
399; CHECK-NEXT:    [[IV_2_MUL:%.*]] = mul i64 [[IV_2]], [[OFFSET_EXT]]
400; CHECK-NEXT:    [[GEP:%.*]] = getelementptr i32, ptr [[DST_2]], i64 [[IV_2_MUL]]
401; CHECK-NEXT:    store i32 0, ptr [[GEP]], align 8
402; CHECK-NEXT:    [[IV_2_NEXT]] = add i64 [[IV_2]], 1
403; CHECK-NEXT:    [[IV_3_NEXT]] = add i32 [[IV_3]], 1
404; CHECK-NEXT:    [[EC:%.*]] = icmp eq i32 [[IV_3]], 200
405; CHECK-NEXT:    br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP11:![0-9]+]]
406; CHECK:       exit:
407; CHECK-NEXT:    ret void
408;
409entry:
410  %offset.ext = zext i32 %offset to i64
411  %add = add i32 %offset, 3
412  br label %loop
413
414loop:
415  %iv.2 = phi i64 [ 0, %entry ], [ %iv.2.next, %loop ]
416  %iv.3 = phi i32 [ 0, %entry ], [ %iv.3.next, %loop ]
417  %iv.mul  = mul i32 %iv.3, %add
418  %gep.mul = getelementptr i8, ptr %dst.1, i32 %iv.mul
419  store i32 0, ptr %gep.mul, align 8
420  %iv.2.mul  = mul i64 %iv.2, %offset.ext
421  %gep = getelementptr i32, ptr %dst.2, i64 %iv.2.mul
422  store i32 0, ptr %gep, align 8
423  %iv.2.next = add i64 %iv.2, 1
424  %iv.3.next = add i32 %iv.3, 1
425  %ec = icmp eq i32 %iv.3, 200
426  br i1 %ec, label %exit, label %loop
427
428exit:
429  ret void
430}
431;.
432; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
433; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
434; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
435; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]]}
436; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}
437; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META1]]}
438; CHECK: [[LOOP6]] = distinct !{[[LOOP6]], [[META1]], [[META2]]}
439; CHECK: [[LOOP7]] = distinct !{[[LOOP7]], [[META1]]}
440; CHECK: [[LOOP8]] = distinct !{[[LOOP8]], [[META1]], [[META2]]}
441; CHECK: [[LOOP9]] = distinct !{[[LOOP9]], [[META1]]}
442; CHECK: [[LOOP10]] = distinct !{[[LOOP10]], [[META1]], [[META2]]}
443; CHECK: [[LOOP11]] = distinct !{[[LOOP11]], [[META1]]}
444;.
445