1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt < %s -passes=loop-vectorize,instsimplify -scalable-vectorization=on -force-target-supports-scalable-vectors -S | FileCheck %s 3 4define void @trunc_minimal_bitwidth(ptr %bptr, ptr noalias %hptr, i32 %val, i64 %N) { 5; CHECK-LABEL: @trunc_minimal_bitwidth( 6; CHECK-NEXT: entry: 7; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64() 8; CHECK-NEXT: [[TMP1:%.*]] = mul i64 [[TMP0]], 4 9; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N:%.*]], [[TMP1]] 10; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 11; CHECK: vector.ph: 12; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64() 13; CHECK-NEXT: [[TMP3:%.*]] = mul i64 [[TMP2]], 4 14; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], [[TMP3]] 15; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]] 16; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[VAL:%.*]], i32 0 17; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <vscale x 4 x i32> [[BROADCAST_SPLATINSERT1]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer 18; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 19; CHECK: vector.body: 20; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 21; CHECK-NEXT: [[TMP4:%.*]] = trunc <vscale x 4 x i32> [[BROADCAST_SPLAT2]] to <vscale x 4 x i16> 22; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i16, ptr [[HPTR:%.*]], i64 [[INDEX]] 23; CHECK-NEXT: store <vscale x 4 x i16> [[TMP4]], ptr [[TMP5]], align 2 24; CHECK-NEXT: [[TMP7:%.*]] = call i64 @llvm.vscale.i64() 25; CHECK-NEXT: [[TMP8:%.*]] = mul i64 [[TMP7]], 4 26; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP8]] 27; CHECK-NEXT: [[TMP9:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 28; CHECK-NEXT: br i1 [[TMP9]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] 29; CHECK: middle.block: 30; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] 31; CHECK-NEXT: br i1 [[CMP_N]], label [[FOR_EXIT:%.*]], label [[SCALAR_PH]] 32; CHECK: scalar.ph: 33; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] 34; CHECK-NEXT: br label [[FOR_BODY:%.*]] 35; CHECK: for.body: 36; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ] 37; CHECK-NEXT: [[CONV21:%.*]] = trunc i32 [[VAL]] to i16 38; CHECK-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds i16, ptr [[HPTR]], i64 [[INDVARS_IV]] 39; CHECK-NEXT: store i16 [[CONV21]], ptr [[ARRAYIDX23]], align 2 40; CHECK-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1 41; CHECK-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], [[N]] 42; CHECK-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_EXIT]], label [[FOR_BODY]], !llvm.loop [[LOOP2:![0-9]+]] 43; CHECK: for.exit: 44; CHECK-NEXT: ret void 45; 46entry: 47 br label %for.body 48 49for.body: 50 %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] 51 %0 = load i8, ptr %bptr, align 1 52 %conv = zext i8 %0 to i32 53 %conv21 = trunc i32 %val to i16 54 %arrayidx23 = getelementptr inbounds i16, ptr %hptr, i64 %indvars.iv 55 store i16 %conv21, ptr %arrayidx23, align 2 56 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 57 %exitcond.not = icmp eq i64 %indvars.iv.next, %N 58 br i1 %exitcond.not, label %for.exit, label %for.body, !llvm.loop !0 59 60for.exit: 61 ret void 62} 63 64define void @trunc_minimal_bitwidths_shufflevector (ptr %p, i32 %arg1, i64 %len) { 65; CHECK-LABEL: @trunc_minimal_bitwidths_shufflevector( 66; CHECK-NEXT: entry: 67; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64() 68; CHECK-NEXT: [[TMP1:%.*]] = mul i64 [[TMP0]], 4 69; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[LEN:%.*]], [[TMP1]] 70; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] 71; CHECK: vector.ph: 72; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64() 73; CHECK-NEXT: [[TMP3:%.*]] = mul i64 [[TMP2]], 4 74; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[LEN]], [[TMP3]] 75; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[LEN]], [[N_MOD_VF]] 76; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 4 x i32> poison, i32 [[ARG1:%.*]], i32 0 77; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 4 x i32> [[BROADCAST_SPLATINSERT]], <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer 78; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] 79; CHECK: vector.body: 80; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] 81; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i8, ptr [[P:%.*]], i64 [[INDEX]] 82; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <vscale x 4 x i8>, ptr [[TMP4]], align 1 83; CHECK-NEXT: [[TMP6:%.*]] = trunc <vscale x 4 x i32> [[BROADCAST_SPLAT]] to <vscale x 4 x i8> 84; CHECK-NEXT: [[TMP7:%.*]] = xor <vscale x 4 x i8> [[WIDE_LOAD]], [[TMP6]] 85; CHECK-NEXT: [[TMP8:%.*]] = mul <vscale x 4 x i8> [[TMP7]], [[WIDE_LOAD]] 86; CHECK-NEXT: store <vscale x 4 x i8> [[TMP8]], ptr [[TMP4]], align 1 87; CHECK-NEXT: [[TMP10:%.*]] = call i64 @llvm.vscale.i64() 88; CHECK-NEXT: [[TMP11:%.*]] = mul i64 [[TMP10]], 4 89; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP11]] 90; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 91; CHECK-NEXT: br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] 92entry: 93 br label %for.body 94 95for.body: ; preds = %entry 96 %indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ] 97 %arrayidx = getelementptr inbounds i8, ptr %p, i64 %indvars.iv 98 %0 = load i8, ptr %arrayidx 99 %conv = zext i8 %0 to i32 100 %conv17 = xor i32 %conv, %arg1 101 %mul18 = mul nuw nsw i32 %conv17, %conv 102 %conv19 = trunc i32 %mul18 to i8 103 store i8 %conv19, ptr %arrayidx 104 %indvars.iv.next = add nuw nsw i64 %indvars.iv, 1 105 %exitcond = icmp eq i64 %indvars.iv.next, %len 106 br i1 %exitcond, label %for.exit, label %for.body, !llvm.loop !0 107 108for.exit: ; preds = %for.body 109 ret void 110} 111!0 = !{!0, !1, !2} 112!1 = !{!"llvm.loop.vectorize.width", i32 4} 113!2 = !{!"llvm.loop.vectorize.scalable.enable", i1 true} 114