190f5c8b7SMel Chen; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 2*b3cba9beSMel Chen; RUN: opt -passes=loop-vectorize -force-vector-interleave=1 -force-vector-width=4 -S < %s | FileCheck %s --check-prefix=CHECK-VF4IC1 3*b3cba9beSMel Chen; RUN: opt -passes=loop-vectorize -force-vector-interleave=4 -force-vector-width=4 -S < %s | FileCheck %s --check-prefix=CHECK-VF4IC4 4*b3cba9beSMel Chen; RUN: opt -passes=loop-vectorize -force-vector-interleave=4 -force-vector-width=1 -S < %s | FileCheck %s --check-prefix=CHECK-VF1IC4 54ddc1745SMel Chen 6707686b0SMel Chendefine i64 @select_icmp_const_1(ptr %a, i64 %n) { 7*b3cba9beSMel Chen; CHECK-VF4IC1-LABEL: define i64 @select_icmp_const_1( 8*b3cba9beSMel Chen; CHECK-VF4IC1-SAME: ptr [[A:%.*]], i64 [[N:%.*]]) { 9*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[ENTRY:.*]]: 10*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4 11*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] 12*b3cba9beSMel Chen; CHECK-VF4IC1: [[VECTOR_PH]]: 13*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 4 14*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]] 15*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br label %[[VECTOR_BODY:.*]] 16*b3cba9beSMel Chen; CHECK-VF4IC1: [[VECTOR_BODY]]: 17*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] 18*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] 19*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[VEC_PHI:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP4:%.*]], %[[VECTOR_BODY]] ] 20*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 21*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP0]] 22*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0 23*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP2]], align 8 24*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP3:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], splat (i64 3) 25*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP4]] = select <4 x i1> [[TMP3]], <4 x i64> [[VEC_IND]], <4 x i64> [[VEC_PHI]] 26*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 27*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[VEC_IND_NEXT]] = add <4 x i64> [[VEC_IND]], splat (i64 4) 28*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 29*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] 30*b3cba9beSMel Chen; CHECK-VF4IC1: [[MIDDLE_BLOCK]]: 31*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP6:%.*]] = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> [[TMP4]]) 32*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[RDX_SELECT_CMP:%.*]] = icmp ne i64 [[TMP6]], -9223372036854775808 33*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[RDX_SELECT:%.*]] = select i1 [[RDX_SELECT_CMP]], i64 [[TMP6]], i64 3 34*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] 35*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] 36*b3cba9beSMel Chen; CHECK-VF4IC1: [[SCALAR_PH]]: 37*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] 38*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ], [ 3, %[[ENTRY]] ] 39*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br label %[[FOR_BODY:.*]] 40*b3cba9beSMel Chen; CHECK-VF4IC1: [[FOR_BODY]]: 41*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[IV:%.*]] = phi i64 [ [[INC:%.*]], %[[FOR_BODY]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ] 42*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[RDX:%.*]] = phi i64 [ [[COND:%.*]], %[[FOR_BODY]] ], [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ] 43*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]] 44*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP7:%.*]] = load i64, ptr [[ARRAYIDX]], align 8 45*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[CMP2:%.*]] = icmp eq i64 [[TMP7]], 3 46*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[COND]] = select i1 [[CMP2]], i64 [[IV]], i64 [[RDX]] 47*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[INC]] = add nuw nsw i64 [[IV]], 1 48*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[N]] 49*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]] 50*b3cba9beSMel Chen; CHECK-VF4IC1: [[EXIT]]: 51*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[COND_LCSSA:%.*]] = phi i64 [ [[COND]], %[[FOR_BODY]] ], [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ] 52*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: ret i64 [[COND_LCSSA]] 53*b3cba9beSMel Chen; 54*b3cba9beSMel Chen; CHECK-VF4IC4-LABEL: define i64 @select_icmp_const_1( 55*b3cba9beSMel Chen; CHECK-VF4IC4-SAME: ptr [[A:%.*]], i64 [[N:%.*]]) { 56*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[ENTRY:.*]]: 57*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 16 58*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] 59*b3cba9beSMel Chen; CHECK-VF4IC4: [[VECTOR_PH]]: 60*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 16 61*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]] 62*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br label %[[VECTOR_BODY:.*]] 63*b3cba9beSMel Chen; CHECK-VF4IC4: [[VECTOR_BODY]]: 64*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] 65*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] 66*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[VEC_PHI:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP10:%.*]], %[[VECTOR_BODY]] ] 67*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP11:%.*]], %[[VECTOR_BODY]] ] 68*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP12:%.*]], %[[VECTOR_BODY]] ] 69*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP13:%.*]], %[[VECTOR_BODY]] ] 70*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[STEP_ADD:%.*]] = add <4 x i64> [[VEC_IND]], splat (i64 4) 71*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[STEP_ADD_2:%.*]] = add <4 x i64> [[STEP_ADD]], splat (i64 4) 72*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[STEP_ADD_3:%.*]] = add <4 x i64> [[STEP_ADD_2]], splat (i64 4) 73*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 74*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP0]] 75*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0 76*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 4 77*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 8 78*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 12 79*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP2]], align 8 80*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x i64>, ptr [[TMP3]], align 8 81*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x i64>, ptr [[TMP4]], align 8 82*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x i64>, ptr [[TMP5]], align 8 83*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP6:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], splat (i64 3) 84*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP7:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD4]], splat (i64 3) 85*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP8:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD5]], splat (i64 3) 86*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP9:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD6]], splat (i64 3) 87*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP10]] = select <4 x i1> [[TMP6]], <4 x i64> [[VEC_IND]], <4 x i64> [[VEC_PHI]] 88*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP11]] = select <4 x i1> [[TMP7]], <4 x i64> [[STEP_ADD]], <4 x i64> [[VEC_PHI1]] 89*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP12]] = select <4 x i1> [[TMP8]], <4 x i64> [[STEP_ADD_2]], <4 x i64> [[VEC_PHI2]] 90*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP13]] = select <4 x i1> [[TMP9]], <4 x i64> [[STEP_ADD_3]], <4 x i64> [[VEC_PHI3]] 91*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 92*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[VEC_IND_NEXT]] = add <4 x i64> [[STEP_ADD_3]], splat (i64 4) 93*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP14:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 94*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br i1 [[TMP14]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] 95*b3cba9beSMel Chen; CHECK-VF4IC4: [[MIDDLE_BLOCK]]: 96*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX_MINMAX:%.*]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[TMP10]], <4 x i64> [[TMP11]]) 97*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX_MINMAX7:%.*]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[RDX_MINMAX]], <4 x i64> [[TMP12]]) 98*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX_MINMAX8:%.*]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[RDX_MINMAX7]], <4 x i64> [[TMP13]]) 99*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP15:%.*]] = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> [[RDX_MINMAX8]]) 100*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX_SELECT_CMP:%.*]] = icmp ne i64 [[TMP15]], -9223372036854775808 101*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX_SELECT:%.*]] = select i1 [[RDX_SELECT_CMP]], i64 [[TMP15]], i64 3 102*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] 103*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] 104*b3cba9beSMel Chen; CHECK-VF4IC4: [[SCALAR_PH]]: 105*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] 106*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ], [ 3, %[[ENTRY]] ] 107*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br label %[[FOR_BODY:.*]] 108*b3cba9beSMel Chen; CHECK-VF4IC4: [[FOR_BODY]]: 109*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[IV:%.*]] = phi i64 [ [[INC:%.*]], %[[FOR_BODY]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ] 110*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX:%.*]] = phi i64 [ [[COND:%.*]], %[[FOR_BODY]] ], [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ] 111*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]] 112*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP16:%.*]] = load i64, ptr [[ARRAYIDX]], align 8 113*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[CMP2:%.*]] = icmp eq i64 [[TMP16]], 3 114*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[COND]] = select i1 [[CMP2]], i64 [[IV]], i64 [[RDX]] 115*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[INC]] = add nuw nsw i64 [[IV]], 1 116*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[N]] 117*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]] 118*b3cba9beSMel Chen; CHECK-VF4IC4: [[EXIT]]: 119*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[COND_LCSSA:%.*]] = phi i64 [ [[COND]], %[[FOR_BODY]] ], [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ] 120*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: ret i64 [[COND_LCSSA]] 121*b3cba9beSMel Chen; 122*b3cba9beSMel Chen; CHECK-VF1IC4-LABEL: define i64 @select_icmp_const_1( 123*b3cba9beSMel Chen; CHECK-VF1IC4-SAME: ptr [[A:%.*]], i64 [[N:%.*]]) { 124*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[ENTRY:.*]]: 125*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4 126*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] 127*b3cba9beSMel Chen; CHECK-VF1IC4: [[VECTOR_PH]]: 128*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 4 129*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]] 130*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br label %[[VECTOR_BODY:.*]] 131*b3cba9beSMel Chen; CHECK-VF1IC4: [[VECTOR_BODY]]: 132*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] 133*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[VEC_PHI:%.*]] = phi i64 [ -9223372036854775808, %[[VECTOR_PH]] ], [ [[TMP16:%.*]], %[[VECTOR_BODY]] ] 134*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[VEC_PHI1:%.*]] = phi i64 [ -9223372036854775808, %[[VECTOR_PH]] ], [ [[TMP17:%.*]], %[[VECTOR_BODY]] ] 135*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[VEC_PHI2:%.*]] = phi i64 [ -9223372036854775808, %[[VECTOR_PH]] ], [ [[TMP18:%.*]], %[[VECTOR_BODY]] ] 136*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[VEC_PHI3:%.*]] = phi i64 [ -9223372036854775808, %[[VECTOR_PH]] ], [ [[TMP19:%.*]], %[[VECTOR_BODY]] ] 137*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 138*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1 139*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 2 140*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 3 141*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP0]] 142*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP1]] 143*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP2]] 144*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP3]] 145*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP8:%.*]] = load i64, ptr [[TMP4]], align 8 146*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP9:%.*]] = load i64, ptr [[TMP5]], align 8 147*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP6]], align 8 148*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP7]], align 8 149*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP12:%.*]] = icmp eq i64 [[TMP8]], 3 150*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP13:%.*]] = icmp eq i64 [[TMP9]], 3 151*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP14:%.*]] = icmp eq i64 [[TMP10]], 3 152*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP15:%.*]] = icmp eq i64 [[TMP11]], 3 153*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP16]] = select i1 [[TMP12]], i64 [[TMP0]], i64 [[VEC_PHI]] 154*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP17]] = select i1 [[TMP13]], i64 [[TMP1]], i64 [[VEC_PHI1]] 155*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP18]] = select i1 [[TMP14]], i64 [[TMP2]], i64 [[VEC_PHI2]] 156*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP19]] = select i1 [[TMP15]], i64 [[TMP3]], i64 [[VEC_PHI3]] 157*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 158*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 159*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br i1 [[TMP20]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] 160*b3cba9beSMel Chen; CHECK-VF1IC4: [[MIDDLE_BLOCK]]: 161*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX_MINMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[TMP16]], i64 [[TMP17]]) 162*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX_MINMAX4:%.*]] = call i64 @llvm.smax.i64(i64 [[RDX_MINMAX]], i64 [[TMP18]]) 163*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX_MINMAX5:%.*]] = call i64 @llvm.smax.i64(i64 [[RDX_MINMAX4]], i64 [[TMP19]]) 164*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX_SELECT_CMP:%.*]] = icmp ne i64 [[RDX_MINMAX5]], -9223372036854775808 165*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX_SELECT:%.*]] = select i1 [[RDX_SELECT_CMP]], i64 [[RDX_MINMAX5]], i64 3 166*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] 167*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] 168*b3cba9beSMel Chen; CHECK-VF1IC4: [[SCALAR_PH]]: 169*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] 170*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ], [ 3, %[[ENTRY]] ] 171*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br label %[[FOR_BODY:.*]] 172*b3cba9beSMel Chen; CHECK-VF1IC4: [[FOR_BODY]]: 173*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[IV:%.*]] = phi i64 [ [[INC:%.*]], %[[FOR_BODY]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ] 174*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX:%.*]] = phi i64 [ [[COND:%.*]], %[[FOR_BODY]] ], [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ] 175*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]] 176*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP21:%.*]] = load i64, ptr [[ARRAYIDX]], align 8 177*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[CMP2:%.*]] = icmp eq i64 [[TMP21]], 3 178*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[COND]] = select i1 [[CMP2]], i64 [[IV]], i64 [[RDX]] 179*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[INC]] = add nuw nsw i64 [[IV]], 1 180*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[N]] 181*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]] 182*b3cba9beSMel Chen; CHECK-VF1IC4: [[EXIT]]: 183*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[COND_LCSSA:%.*]] = phi i64 [ [[COND]], %[[FOR_BODY]] ], [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ] 184*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: ret i64 [[COND_LCSSA]] 1854ddc1745SMel Chen; 1864ddc1745SMel Chenentry: 1874ddc1745SMel Chen br label %for.body 1884ddc1745SMel Chen 1894ddc1745SMel Chenfor.body: ; preds = %entry, %for.body 1904ddc1745SMel Chen %iv = phi i64 [ %inc, %for.body ], [ 0, %entry ] 1914ddc1745SMel Chen %rdx = phi i64 [ %cond, %for.body ], [ 3, %entry ] 1924ddc1745SMel Chen %arrayidx = getelementptr inbounds i64, ptr %a, i64 %iv 1934ddc1745SMel Chen %0 = load i64, ptr %arrayidx, align 8 1944ddc1745SMel Chen %cmp2 = icmp eq i64 %0, 3 1954ddc1745SMel Chen %cond = select i1 %cmp2, i64 %iv, i64 %rdx 1964ddc1745SMel Chen %inc = add nuw nsw i64 %iv, 1 1974ddc1745SMel Chen %exitcond.not = icmp eq i64 %inc, %n 1984ddc1745SMel Chen br i1 %exitcond.not, label %exit, label %for.body 1994ddc1745SMel Chen 2004ddc1745SMel Chenexit: ; preds = %for.body 2014ddc1745SMel Chen ret i64 %cond 2024ddc1745SMel Chen} 2034ddc1745SMel Chen 204707686b0SMel Chendefine i64 @select_icmp_const_2(ptr %a, i64 %n) { 205*b3cba9beSMel Chen; CHECK-VF4IC1-LABEL: define i64 @select_icmp_const_2( 206*b3cba9beSMel Chen; CHECK-VF4IC1-SAME: ptr [[A:%.*]], i64 [[N:%.*]]) { 207*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[ENTRY:.*]]: 208*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4 209*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] 210*b3cba9beSMel Chen; CHECK-VF4IC1: [[VECTOR_PH]]: 211*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 4 212*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]] 213*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br label %[[VECTOR_BODY:.*]] 214*b3cba9beSMel Chen; CHECK-VF4IC1: [[VECTOR_BODY]]: 215*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] 216*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] 217*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[VEC_PHI:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP4:%.*]], %[[VECTOR_BODY]] ] 218*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 219*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP0]] 220*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0 221*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP2]], align 8 222*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP3:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], splat (i64 3) 223*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP4]] = select <4 x i1> [[TMP3]], <4 x i64> [[VEC_PHI]], <4 x i64> [[VEC_IND]] 224*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 225*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[VEC_IND_NEXT]] = add <4 x i64> [[VEC_IND]], splat (i64 4) 226*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 227*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] 228*b3cba9beSMel Chen; CHECK-VF4IC1: [[MIDDLE_BLOCK]]: 229*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP6:%.*]] = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> [[TMP4]]) 230*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[RDX_SELECT_CMP:%.*]] = icmp ne i64 [[TMP6]], -9223372036854775808 231*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[RDX_SELECT:%.*]] = select i1 [[RDX_SELECT_CMP]], i64 [[TMP6]], i64 3 232*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] 233*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] 234*b3cba9beSMel Chen; CHECK-VF4IC1: [[SCALAR_PH]]: 235*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] 236*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ], [ 3, %[[ENTRY]] ] 237*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br label %[[FOR_BODY:.*]] 238*b3cba9beSMel Chen; CHECK-VF4IC1: [[FOR_BODY]]: 239*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[IV:%.*]] = phi i64 [ [[INC:%.*]], %[[FOR_BODY]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ] 240*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[RDX:%.*]] = phi i64 [ [[COND:%.*]], %[[FOR_BODY]] ], [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ] 241*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]] 242*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP7:%.*]] = load i64, ptr [[ARRAYIDX]], align 8 243*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[CMP2:%.*]] = icmp eq i64 [[TMP7]], 3 244*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[COND]] = select i1 [[CMP2]], i64 [[RDX]], i64 [[IV]] 245*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[INC]] = add nuw nsw i64 [[IV]], 1 246*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[N]] 247*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]] 248*b3cba9beSMel Chen; CHECK-VF4IC1: [[EXIT]]: 249*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[COND_LCSSA:%.*]] = phi i64 [ [[COND]], %[[FOR_BODY]] ], [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ] 250*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: ret i64 [[COND_LCSSA]] 251*b3cba9beSMel Chen; 252*b3cba9beSMel Chen; CHECK-VF4IC4-LABEL: define i64 @select_icmp_const_2( 253*b3cba9beSMel Chen; CHECK-VF4IC4-SAME: ptr [[A:%.*]], i64 [[N:%.*]]) { 254*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[ENTRY:.*]]: 255*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 16 256*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] 257*b3cba9beSMel Chen; CHECK-VF4IC4: [[VECTOR_PH]]: 258*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 16 259*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]] 260*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br label %[[VECTOR_BODY:.*]] 261*b3cba9beSMel Chen; CHECK-VF4IC4: [[VECTOR_BODY]]: 262*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] 263*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] 264*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[VEC_PHI:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP10:%.*]], %[[VECTOR_BODY]] ] 265*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP11:%.*]], %[[VECTOR_BODY]] ] 266*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP12:%.*]], %[[VECTOR_BODY]] ] 267*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP13:%.*]], %[[VECTOR_BODY]] ] 268*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[STEP_ADD:%.*]] = add <4 x i64> [[VEC_IND]], splat (i64 4) 269*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[STEP_ADD_2:%.*]] = add <4 x i64> [[STEP_ADD]], splat (i64 4) 270*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[STEP_ADD_3:%.*]] = add <4 x i64> [[STEP_ADD_2]], splat (i64 4) 271*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 272*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP0]] 273*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0 274*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 4 275*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 8 276*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 12 277*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP2]], align 8 278*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x i64>, ptr [[TMP3]], align 8 279*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x i64>, ptr [[TMP4]], align 8 280*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x i64>, ptr [[TMP5]], align 8 281*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP6:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], splat (i64 3) 282*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP7:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD4]], splat (i64 3) 283*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP8:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD5]], splat (i64 3) 284*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP9:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD6]], splat (i64 3) 285*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP10]] = select <4 x i1> [[TMP6]], <4 x i64> [[VEC_PHI]], <4 x i64> [[VEC_IND]] 286*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP11]] = select <4 x i1> [[TMP7]], <4 x i64> [[VEC_PHI1]], <4 x i64> [[STEP_ADD]] 287*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP12]] = select <4 x i1> [[TMP8]], <4 x i64> [[VEC_PHI2]], <4 x i64> [[STEP_ADD_2]] 288*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP13]] = select <4 x i1> [[TMP9]], <4 x i64> [[VEC_PHI3]], <4 x i64> [[STEP_ADD_3]] 289*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 290*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[VEC_IND_NEXT]] = add <4 x i64> [[STEP_ADD_3]], splat (i64 4) 291*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP14:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 292*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br i1 [[TMP14]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] 293*b3cba9beSMel Chen; CHECK-VF4IC4: [[MIDDLE_BLOCK]]: 294*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX_MINMAX:%.*]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[TMP10]], <4 x i64> [[TMP11]]) 295*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX_MINMAX7:%.*]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[RDX_MINMAX]], <4 x i64> [[TMP12]]) 296*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX_MINMAX8:%.*]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[RDX_MINMAX7]], <4 x i64> [[TMP13]]) 297*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP15:%.*]] = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> [[RDX_MINMAX8]]) 298*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX_SELECT_CMP:%.*]] = icmp ne i64 [[TMP15]], -9223372036854775808 299*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX_SELECT:%.*]] = select i1 [[RDX_SELECT_CMP]], i64 [[TMP15]], i64 3 300*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] 301*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] 302*b3cba9beSMel Chen; CHECK-VF4IC4: [[SCALAR_PH]]: 303*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] 304*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ], [ 3, %[[ENTRY]] ] 305*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br label %[[FOR_BODY:.*]] 306*b3cba9beSMel Chen; CHECK-VF4IC4: [[FOR_BODY]]: 307*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[IV:%.*]] = phi i64 [ [[INC:%.*]], %[[FOR_BODY]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ] 308*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX:%.*]] = phi i64 [ [[COND:%.*]], %[[FOR_BODY]] ], [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ] 309*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]] 310*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP16:%.*]] = load i64, ptr [[ARRAYIDX]], align 8 311*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[CMP2:%.*]] = icmp eq i64 [[TMP16]], 3 312*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[COND]] = select i1 [[CMP2]], i64 [[RDX]], i64 [[IV]] 313*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[INC]] = add nuw nsw i64 [[IV]], 1 314*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[N]] 315*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]] 316*b3cba9beSMel Chen; CHECK-VF4IC4: [[EXIT]]: 317*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[COND_LCSSA:%.*]] = phi i64 [ [[COND]], %[[FOR_BODY]] ], [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ] 318*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: ret i64 [[COND_LCSSA]] 319*b3cba9beSMel Chen; 320*b3cba9beSMel Chen; CHECK-VF1IC4-LABEL: define i64 @select_icmp_const_2( 321*b3cba9beSMel Chen; CHECK-VF1IC4-SAME: ptr [[A:%.*]], i64 [[N:%.*]]) { 322*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[ENTRY:.*]]: 323*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4 324*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] 325*b3cba9beSMel Chen; CHECK-VF1IC4: [[VECTOR_PH]]: 326*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 4 327*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]] 328*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br label %[[VECTOR_BODY:.*]] 329*b3cba9beSMel Chen; CHECK-VF1IC4: [[VECTOR_BODY]]: 330*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] 331*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[VEC_PHI:%.*]] = phi i64 [ -9223372036854775808, %[[VECTOR_PH]] ], [ [[TMP16:%.*]], %[[VECTOR_BODY]] ] 332*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[VEC_PHI1:%.*]] = phi i64 [ -9223372036854775808, %[[VECTOR_PH]] ], [ [[TMP17:%.*]], %[[VECTOR_BODY]] ] 333*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[VEC_PHI2:%.*]] = phi i64 [ -9223372036854775808, %[[VECTOR_PH]] ], [ [[TMP18:%.*]], %[[VECTOR_BODY]] ] 334*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[VEC_PHI3:%.*]] = phi i64 [ -9223372036854775808, %[[VECTOR_PH]] ], [ [[TMP19:%.*]], %[[VECTOR_BODY]] ] 335*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 336*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1 337*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 2 338*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 3 339*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP0]] 340*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP1]] 341*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP2]] 342*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP3]] 343*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP8:%.*]] = load i64, ptr [[TMP4]], align 8 344*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP9:%.*]] = load i64, ptr [[TMP5]], align 8 345*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP6]], align 8 346*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP7]], align 8 347*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP12:%.*]] = icmp eq i64 [[TMP8]], 3 348*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP13:%.*]] = icmp eq i64 [[TMP9]], 3 349*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP14:%.*]] = icmp eq i64 [[TMP10]], 3 350*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP15:%.*]] = icmp eq i64 [[TMP11]], 3 351*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP16]] = select i1 [[TMP12]], i64 [[VEC_PHI]], i64 [[TMP0]] 352*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP17]] = select i1 [[TMP13]], i64 [[VEC_PHI1]], i64 [[TMP1]] 353*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP18]] = select i1 [[TMP14]], i64 [[VEC_PHI2]], i64 [[TMP2]] 354*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP19]] = select i1 [[TMP15]], i64 [[VEC_PHI3]], i64 [[TMP3]] 355*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 356*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 357*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br i1 [[TMP20]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] 358*b3cba9beSMel Chen; CHECK-VF1IC4: [[MIDDLE_BLOCK]]: 359*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX_MINMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[TMP16]], i64 [[TMP17]]) 360*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX_MINMAX4:%.*]] = call i64 @llvm.smax.i64(i64 [[RDX_MINMAX]], i64 [[TMP18]]) 361*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX_MINMAX5:%.*]] = call i64 @llvm.smax.i64(i64 [[RDX_MINMAX4]], i64 [[TMP19]]) 362*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX_SELECT_CMP:%.*]] = icmp ne i64 [[RDX_MINMAX5]], -9223372036854775808 363*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX_SELECT:%.*]] = select i1 [[RDX_SELECT_CMP]], i64 [[RDX_MINMAX5]], i64 3 364*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] 365*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] 366*b3cba9beSMel Chen; CHECK-VF1IC4: [[SCALAR_PH]]: 367*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] 368*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ], [ 3, %[[ENTRY]] ] 369*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br label %[[FOR_BODY:.*]] 370*b3cba9beSMel Chen; CHECK-VF1IC4: [[FOR_BODY]]: 371*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[IV:%.*]] = phi i64 [ [[INC:%.*]], %[[FOR_BODY]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ] 372*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX:%.*]] = phi i64 [ [[COND:%.*]], %[[FOR_BODY]] ], [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ] 373*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]] 374*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP21:%.*]] = load i64, ptr [[ARRAYIDX]], align 8 375*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[CMP2:%.*]] = icmp eq i64 [[TMP21]], 3 376*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[COND]] = select i1 [[CMP2]], i64 [[RDX]], i64 [[IV]] 377*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[INC]] = add nuw nsw i64 [[IV]], 1 378*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[N]] 379*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]] 380*b3cba9beSMel Chen; CHECK-VF1IC4: [[EXIT]]: 381*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[COND_LCSSA:%.*]] = phi i64 [ [[COND]], %[[FOR_BODY]] ], [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ] 382*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: ret i64 [[COND_LCSSA]] 3834ddc1745SMel Chen; 3844ddc1745SMel Chenentry: 3854ddc1745SMel Chen br label %for.body 3864ddc1745SMel Chen 3874ddc1745SMel Chenfor.body: ; preds = %entry, %for.body 3884ddc1745SMel Chen %iv = phi i64 [ %inc, %for.body ], [ 0, %entry ] 3894ddc1745SMel Chen %rdx = phi i64 [ %cond, %for.body ], [ 3, %entry ] 3904ddc1745SMel Chen %arrayidx = getelementptr inbounds i64, ptr %a, i64 %iv 3914ddc1745SMel Chen %0 = load i64, ptr %arrayidx, align 8 3924ddc1745SMel Chen %cmp2 = icmp eq i64 %0, 3 3934ddc1745SMel Chen %cond = select i1 %cmp2, i64 %rdx, i64 %iv 3944ddc1745SMel Chen %inc = add nuw nsw i64 %iv, 1 3954ddc1745SMel Chen %exitcond.not = icmp eq i64 %inc, %n 3964ddc1745SMel Chen br i1 %exitcond.not, label %exit, label %for.body 3974ddc1745SMel Chen 3984ddc1745SMel Chenexit: ; preds = %for.body 3994ddc1745SMel Chen ret i64 %cond 4004ddc1745SMel Chen} 4014ddc1745SMel Chen 402707686b0SMel Chendefine i64 @select_icmp_const_3_variable_rdx_start(ptr %a, i64 %rdx.start, i64 %n) { 403*b3cba9beSMel Chen; CHECK-VF4IC1-LABEL: define i64 @select_icmp_const_3_variable_rdx_start( 404*b3cba9beSMel Chen; CHECK-VF4IC1-SAME: ptr [[A:%.*]], i64 [[RDX_START:%.*]], i64 [[N:%.*]]) { 405*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[ENTRY:.*]]: 406*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4 407*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] 408*b3cba9beSMel Chen; CHECK-VF4IC1: [[VECTOR_PH]]: 409*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 4 410*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]] 411*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br label %[[VECTOR_BODY:.*]] 412*b3cba9beSMel Chen; CHECK-VF4IC1: [[VECTOR_BODY]]: 413*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] 414*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] 415*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[VEC_PHI:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP4:%.*]], %[[VECTOR_BODY]] ] 416*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 417*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP0]] 418*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0 419*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP2]], align 8 420*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP3:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], splat (i64 3) 421*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP4]] = select <4 x i1> [[TMP3]], <4 x i64> [[VEC_IND]], <4 x i64> [[VEC_PHI]] 422*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 423*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[VEC_IND_NEXT]] = add <4 x i64> [[VEC_IND]], splat (i64 4) 424*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 425*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]] 426*b3cba9beSMel Chen; CHECK-VF4IC1: [[MIDDLE_BLOCK]]: 427*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP6:%.*]] = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> [[TMP4]]) 428*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[RDX_SELECT_CMP:%.*]] = icmp ne i64 [[TMP6]], -9223372036854775808 429*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[RDX_SELECT:%.*]] = select i1 [[RDX_SELECT_CMP]], i64 [[TMP6]], i64 [[RDX_START]] 430*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] 431*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] 432*b3cba9beSMel Chen; CHECK-VF4IC1: [[SCALAR_PH]]: 433*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] 434*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ], [ [[RDX_START]], %[[ENTRY]] ] 435*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br label %[[FOR_BODY:.*]] 436*b3cba9beSMel Chen; CHECK-VF4IC1: [[FOR_BODY]]: 437*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[IV:%.*]] = phi i64 [ [[INC:%.*]], %[[FOR_BODY]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ] 438*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[RDX:%.*]] = phi i64 [ [[COND:%.*]], %[[FOR_BODY]] ], [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ] 439*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]] 440*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP7:%.*]] = load i64, ptr [[ARRAYIDX]], align 8 441*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[CMP2:%.*]] = icmp eq i64 [[TMP7]], 3 442*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[COND]] = select i1 [[CMP2]], i64 [[IV]], i64 [[RDX]] 443*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[INC]] = add nuw nsw i64 [[IV]], 1 444*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[N]] 445*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]] 446*b3cba9beSMel Chen; CHECK-VF4IC1: [[EXIT]]: 447*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[COND_LCSSA:%.*]] = phi i64 [ [[COND]], %[[FOR_BODY]] ], [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ] 448*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: ret i64 [[COND_LCSSA]] 449*b3cba9beSMel Chen; 450*b3cba9beSMel Chen; CHECK-VF4IC4-LABEL: define i64 @select_icmp_const_3_variable_rdx_start( 451*b3cba9beSMel Chen; CHECK-VF4IC4-SAME: ptr [[A:%.*]], i64 [[RDX_START:%.*]], i64 [[N:%.*]]) { 452*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[ENTRY:.*]]: 453*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 16 454*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] 455*b3cba9beSMel Chen; CHECK-VF4IC4: [[VECTOR_PH]]: 456*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 16 457*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]] 458*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br label %[[VECTOR_BODY:.*]] 459*b3cba9beSMel Chen; CHECK-VF4IC4: [[VECTOR_BODY]]: 460*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] 461*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] 462*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[VEC_PHI:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP10:%.*]], %[[VECTOR_BODY]] ] 463*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP11:%.*]], %[[VECTOR_BODY]] ] 464*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP12:%.*]], %[[VECTOR_BODY]] ] 465*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP13:%.*]], %[[VECTOR_BODY]] ] 466*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[STEP_ADD:%.*]] = add <4 x i64> [[VEC_IND]], splat (i64 4) 467*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[STEP_ADD_2:%.*]] = add <4 x i64> [[STEP_ADD]], splat (i64 4) 468*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[STEP_ADD_3:%.*]] = add <4 x i64> [[STEP_ADD_2]], splat (i64 4) 469*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 470*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP0]] 471*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0 472*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 4 473*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 8 474*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 12 475*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP2]], align 8 476*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x i64>, ptr [[TMP3]], align 8 477*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x i64>, ptr [[TMP4]], align 8 478*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x i64>, ptr [[TMP5]], align 8 479*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP6:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], splat (i64 3) 480*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP7:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD4]], splat (i64 3) 481*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP8:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD5]], splat (i64 3) 482*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP9:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD6]], splat (i64 3) 483*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP10]] = select <4 x i1> [[TMP6]], <4 x i64> [[VEC_IND]], <4 x i64> [[VEC_PHI]] 484*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP11]] = select <4 x i1> [[TMP7]], <4 x i64> [[STEP_ADD]], <4 x i64> [[VEC_PHI1]] 485*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP12]] = select <4 x i1> [[TMP8]], <4 x i64> [[STEP_ADD_2]], <4 x i64> [[VEC_PHI2]] 486*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP13]] = select <4 x i1> [[TMP9]], <4 x i64> [[STEP_ADD_3]], <4 x i64> [[VEC_PHI3]] 487*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 488*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[VEC_IND_NEXT]] = add <4 x i64> [[STEP_ADD_3]], splat (i64 4) 489*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP14:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 490*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br i1 [[TMP14]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]] 491*b3cba9beSMel Chen; CHECK-VF4IC4: [[MIDDLE_BLOCK]]: 492*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX_MINMAX:%.*]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[TMP10]], <4 x i64> [[TMP11]]) 493*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX_MINMAX7:%.*]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[RDX_MINMAX]], <4 x i64> [[TMP12]]) 494*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX_MINMAX8:%.*]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[RDX_MINMAX7]], <4 x i64> [[TMP13]]) 495*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP15:%.*]] = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> [[RDX_MINMAX8]]) 496*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX_SELECT_CMP:%.*]] = icmp ne i64 [[TMP15]], -9223372036854775808 497*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX_SELECT:%.*]] = select i1 [[RDX_SELECT_CMP]], i64 [[TMP15]], i64 [[RDX_START]] 498*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] 499*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] 500*b3cba9beSMel Chen; CHECK-VF4IC4: [[SCALAR_PH]]: 501*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] 502*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ], [ [[RDX_START]], %[[ENTRY]] ] 503*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br label %[[FOR_BODY:.*]] 504*b3cba9beSMel Chen; CHECK-VF4IC4: [[FOR_BODY]]: 505*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[IV:%.*]] = phi i64 [ [[INC:%.*]], %[[FOR_BODY]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ] 506*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX:%.*]] = phi i64 [ [[COND:%.*]], %[[FOR_BODY]] ], [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ] 507*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]] 508*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP16:%.*]] = load i64, ptr [[ARRAYIDX]], align 8 509*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[CMP2:%.*]] = icmp eq i64 [[TMP16]], 3 510*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[COND]] = select i1 [[CMP2]], i64 [[IV]], i64 [[RDX]] 511*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[INC]] = add nuw nsw i64 [[IV]], 1 512*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[N]] 513*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]] 514*b3cba9beSMel Chen; CHECK-VF4IC4: [[EXIT]]: 515*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[COND_LCSSA:%.*]] = phi i64 [ [[COND]], %[[FOR_BODY]] ], [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ] 516*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: ret i64 [[COND_LCSSA]] 517*b3cba9beSMel Chen; 518*b3cba9beSMel Chen; CHECK-VF1IC4-LABEL: define i64 @select_icmp_const_3_variable_rdx_start( 519*b3cba9beSMel Chen; CHECK-VF1IC4-SAME: ptr [[A:%.*]], i64 [[RDX_START:%.*]], i64 [[N:%.*]]) { 520*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[ENTRY:.*]]: 521*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4 522*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] 523*b3cba9beSMel Chen; CHECK-VF1IC4: [[VECTOR_PH]]: 524*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 4 525*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]] 526*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br label %[[VECTOR_BODY:.*]] 527*b3cba9beSMel Chen; CHECK-VF1IC4: [[VECTOR_BODY]]: 528*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] 529*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[VEC_PHI:%.*]] = phi i64 [ -9223372036854775808, %[[VECTOR_PH]] ], [ [[TMP16:%.*]], %[[VECTOR_BODY]] ] 530*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[VEC_PHI1:%.*]] = phi i64 [ -9223372036854775808, %[[VECTOR_PH]] ], [ [[TMP17:%.*]], %[[VECTOR_BODY]] ] 531*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[VEC_PHI2:%.*]] = phi i64 [ -9223372036854775808, %[[VECTOR_PH]] ], [ [[TMP18:%.*]], %[[VECTOR_BODY]] ] 532*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[VEC_PHI3:%.*]] = phi i64 [ -9223372036854775808, %[[VECTOR_PH]] ], [ [[TMP19:%.*]], %[[VECTOR_BODY]] ] 533*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 534*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1 535*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 2 536*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 3 537*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP0]] 538*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP1]] 539*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP2]] 540*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP3]] 541*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP8:%.*]] = load i64, ptr [[TMP4]], align 8 542*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP9:%.*]] = load i64, ptr [[TMP5]], align 8 543*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP6]], align 8 544*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP7]], align 8 545*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP12:%.*]] = icmp eq i64 [[TMP8]], 3 546*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP13:%.*]] = icmp eq i64 [[TMP9]], 3 547*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP14:%.*]] = icmp eq i64 [[TMP10]], 3 548*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP15:%.*]] = icmp eq i64 [[TMP11]], 3 549*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP16]] = select i1 [[TMP12]], i64 [[TMP0]], i64 [[VEC_PHI]] 550*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP17]] = select i1 [[TMP13]], i64 [[TMP1]], i64 [[VEC_PHI1]] 551*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP18]] = select i1 [[TMP14]], i64 [[TMP2]], i64 [[VEC_PHI2]] 552*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP19]] = select i1 [[TMP15]], i64 [[TMP3]], i64 [[VEC_PHI3]] 553*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 554*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 555*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br i1 [[TMP20]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]] 556*b3cba9beSMel Chen; CHECK-VF1IC4: [[MIDDLE_BLOCK]]: 557*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX_MINMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[TMP16]], i64 [[TMP17]]) 558*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX_MINMAX4:%.*]] = call i64 @llvm.smax.i64(i64 [[RDX_MINMAX]], i64 [[TMP18]]) 559*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX_MINMAX5:%.*]] = call i64 @llvm.smax.i64(i64 [[RDX_MINMAX4]], i64 [[TMP19]]) 560*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX_SELECT_CMP:%.*]] = icmp ne i64 [[RDX_MINMAX5]], -9223372036854775808 561*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX_SELECT:%.*]] = select i1 [[RDX_SELECT_CMP]], i64 [[RDX_MINMAX5]], i64 [[RDX_START]] 562*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] 563*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] 564*b3cba9beSMel Chen; CHECK-VF1IC4: [[SCALAR_PH]]: 565*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] 566*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ], [ [[RDX_START]], %[[ENTRY]] ] 567*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br label %[[FOR_BODY:.*]] 568*b3cba9beSMel Chen; CHECK-VF1IC4: [[FOR_BODY]]: 569*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[IV:%.*]] = phi i64 [ [[INC:%.*]], %[[FOR_BODY]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ] 570*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX:%.*]] = phi i64 [ [[COND:%.*]], %[[FOR_BODY]] ], [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ] 571*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]] 572*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP21:%.*]] = load i64, ptr [[ARRAYIDX]], align 8 573*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[CMP2:%.*]] = icmp eq i64 [[TMP21]], 3 574*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[COND]] = select i1 [[CMP2]], i64 [[IV]], i64 [[RDX]] 575*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[INC]] = add nuw nsw i64 [[IV]], 1 576*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[N]] 577*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]] 578*b3cba9beSMel Chen; CHECK-VF1IC4: [[EXIT]]: 579*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[COND_LCSSA:%.*]] = phi i64 [ [[COND]], %[[FOR_BODY]] ], [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ] 580*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: ret i64 [[COND_LCSSA]] 5814ddc1745SMel Chen; 5824ddc1745SMel Chenentry: 5834ddc1745SMel Chen br label %for.body 5844ddc1745SMel Chen 5854ddc1745SMel Chenfor.body: ; preds = %entry, %for.body 5864ddc1745SMel Chen %iv = phi i64 [ %inc, %for.body ], [ 0, %entry ] 5874ddc1745SMel Chen %rdx = phi i64 [ %cond, %for.body ], [ %rdx.start, %entry ] 5884ddc1745SMel Chen %arrayidx = getelementptr inbounds i64, ptr %a, i64 %iv 5894ddc1745SMel Chen %0 = load i64, ptr %arrayidx, align 8 5904ddc1745SMel Chen %cmp2 = icmp eq i64 %0, 3 5914ddc1745SMel Chen %cond = select i1 %cmp2, i64 %iv, i64 %rdx 5924ddc1745SMel Chen %inc = add nuw nsw i64 %iv, 1 5934ddc1745SMel Chen %exitcond.not = icmp eq i64 %inc, %n 5944ddc1745SMel Chen br i1 %exitcond.not, label %exit, label %for.body 5954ddc1745SMel Chen 5964ddc1745SMel Chenexit: ; preds = %for.body 5974ddc1745SMel Chen ret i64 %cond 5984ddc1745SMel Chen} 5994ddc1745SMel Chen 600707686b0SMel Chendefine i64 @select_fcmp_const_fast(ptr %a, i64 %n) { 601*b3cba9beSMel Chen; CHECK-VF4IC1-LABEL: define i64 @select_fcmp_const_fast( 602*b3cba9beSMel Chen; CHECK-VF4IC1-SAME: ptr [[A:%.*]], i64 [[N:%.*]]) { 603*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[ENTRY:.*]]: 604*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4 605*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] 606*b3cba9beSMel Chen; CHECK-VF4IC1: [[VECTOR_PH]]: 607*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 4 608*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]] 609*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br label %[[VECTOR_BODY:.*]] 610*b3cba9beSMel Chen; CHECK-VF4IC1: [[VECTOR_BODY]]: 611*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] 612*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] 613*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[VEC_PHI:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP4:%.*]], %[[VECTOR_BODY]] ] 614*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 615*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP1:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP0]] 616*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP2:%.*]] = getelementptr inbounds float, ptr [[TMP1]], i32 0 617*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[TMP2]], align 4 618*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP3:%.*]] = fcmp fast ueq <4 x float> [[WIDE_LOAD]], splat (float 3.000000e+00) 619*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP4]] = select <4 x i1> [[TMP3]], <4 x i64> [[VEC_IND]], <4 x i64> [[VEC_PHI]] 620*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 621*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[VEC_IND_NEXT]] = add <4 x i64> [[VEC_IND]], splat (i64 4) 622*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 623*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]] 624*b3cba9beSMel Chen; CHECK-VF4IC1: [[MIDDLE_BLOCK]]: 625*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP6:%.*]] = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> [[TMP4]]) 626*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[RDX_SELECT_CMP:%.*]] = icmp ne i64 [[TMP6]], -9223372036854775808 627*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[RDX_SELECT:%.*]] = select i1 [[RDX_SELECT_CMP]], i64 [[TMP6]], i64 2 628*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] 629*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] 630*b3cba9beSMel Chen; CHECK-VF4IC1: [[SCALAR_PH]]: 631*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] 632*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ], [ 2, %[[ENTRY]] ] 633*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br label %[[FOR_BODY:.*]] 634*b3cba9beSMel Chen; CHECK-VF4IC1: [[FOR_BODY]]: 635*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[IV:%.*]] = phi i64 [ [[INC:%.*]], %[[FOR_BODY]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ] 636*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[RDX:%.*]] = phi i64 [ [[COND:%.*]], %[[FOR_BODY]] ], [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ] 637*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[IV]] 638*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP7:%.*]] = load float, ptr [[ARRAYIDX]], align 4 639*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[CMP2:%.*]] = fcmp fast ueq float [[TMP7]], 3.000000e+00 640*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[COND]] = select i1 [[CMP2]], i64 [[IV]], i64 [[RDX]] 641*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[INC]] = add nuw nsw i64 [[IV]], 1 642*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[N]] 643*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]] 644*b3cba9beSMel Chen; CHECK-VF4IC1: [[EXIT]]: 645*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[COND_LCSSA:%.*]] = phi i64 [ [[COND]], %[[FOR_BODY]] ], [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ] 646*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: ret i64 [[COND_LCSSA]] 647*b3cba9beSMel Chen; 648*b3cba9beSMel Chen; CHECK-VF4IC4-LABEL: define i64 @select_fcmp_const_fast( 649*b3cba9beSMel Chen; CHECK-VF4IC4-SAME: ptr [[A:%.*]], i64 [[N:%.*]]) { 650*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[ENTRY:.*]]: 651*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 16 652*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] 653*b3cba9beSMel Chen; CHECK-VF4IC4: [[VECTOR_PH]]: 654*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 16 655*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]] 656*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br label %[[VECTOR_BODY:.*]] 657*b3cba9beSMel Chen; CHECK-VF4IC4: [[VECTOR_BODY]]: 658*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] 659*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] 660*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[VEC_PHI:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP10:%.*]], %[[VECTOR_BODY]] ] 661*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP11:%.*]], %[[VECTOR_BODY]] ] 662*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP12:%.*]], %[[VECTOR_BODY]] ] 663*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP13:%.*]], %[[VECTOR_BODY]] ] 664*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[STEP_ADD:%.*]] = add <4 x i64> [[VEC_IND]], splat (i64 4) 665*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[STEP_ADD_2:%.*]] = add <4 x i64> [[STEP_ADD]], splat (i64 4) 666*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[STEP_ADD_3:%.*]] = add <4 x i64> [[STEP_ADD_2]], splat (i64 4) 667*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 668*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP1:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP0]] 669*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP2:%.*]] = getelementptr inbounds float, ptr [[TMP1]], i32 0 670*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP3:%.*]] = getelementptr inbounds float, ptr [[TMP1]], i32 4 671*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP4:%.*]] = getelementptr inbounds float, ptr [[TMP1]], i32 8 672*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP5:%.*]] = getelementptr inbounds float, ptr [[TMP1]], i32 12 673*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[TMP2]], align 4 674*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x float>, ptr [[TMP3]], align 4 675*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x float>, ptr [[TMP4]], align 4 676*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x float>, ptr [[TMP5]], align 4 677*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP6:%.*]] = fcmp fast ueq <4 x float> [[WIDE_LOAD]], splat (float 3.000000e+00) 678*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP7:%.*]] = fcmp fast ueq <4 x float> [[WIDE_LOAD4]], splat (float 3.000000e+00) 679*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP8:%.*]] = fcmp fast ueq <4 x float> [[WIDE_LOAD5]], splat (float 3.000000e+00) 680*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP9:%.*]] = fcmp fast ueq <4 x float> [[WIDE_LOAD6]], splat (float 3.000000e+00) 681*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP10]] = select <4 x i1> [[TMP6]], <4 x i64> [[VEC_IND]], <4 x i64> [[VEC_PHI]] 682*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP11]] = select <4 x i1> [[TMP7]], <4 x i64> [[STEP_ADD]], <4 x i64> [[VEC_PHI1]] 683*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP12]] = select <4 x i1> [[TMP8]], <4 x i64> [[STEP_ADD_2]], <4 x i64> [[VEC_PHI2]] 684*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP13]] = select <4 x i1> [[TMP9]], <4 x i64> [[STEP_ADD_3]], <4 x i64> [[VEC_PHI3]] 685*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 686*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[VEC_IND_NEXT]] = add <4 x i64> [[STEP_ADD_3]], splat (i64 4) 687*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP14:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 688*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br i1 [[TMP14]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]] 689*b3cba9beSMel Chen; CHECK-VF4IC4: [[MIDDLE_BLOCK]]: 690*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX_MINMAX:%.*]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[TMP10]], <4 x i64> [[TMP11]]) 691*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX_MINMAX7:%.*]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[RDX_MINMAX]], <4 x i64> [[TMP12]]) 692*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX_MINMAX8:%.*]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[RDX_MINMAX7]], <4 x i64> [[TMP13]]) 693*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP15:%.*]] = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> [[RDX_MINMAX8]]) 694*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX_SELECT_CMP:%.*]] = icmp ne i64 [[TMP15]], -9223372036854775808 695*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX_SELECT:%.*]] = select i1 [[RDX_SELECT_CMP]], i64 [[TMP15]], i64 2 696*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] 697*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] 698*b3cba9beSMel Chen; CHECK-VF4IC4: [[SCALAR_PH]]: 699*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] 700*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ], [ 2, %[[ENTRY]] ] 701*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br label %[[FOR_BODY:.*]] 702*b3cba9beSMel Chen; CHECK-VF4IC4: [[FOR_BODY]]: 703*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[IV:%.*]] = phi i64 [ [[INC:%.*]], %[[FOR_BODY]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ] 704*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX:%.*]] = phi i64 [ [[COND:%.*]], %[[FOR_BODY]] ], [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ] 705*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[IV]] 706*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 4 707*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[CMP2:%.*]] = fcmp fast ueq float [[TMP16]], 3.000000e+00 708*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[COND]] = select i1 [[CMP2]], i64 [[IV]], i64 [[RDX]] 709*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[INC]] = add nuw nsw i64 [[IV]], 1 710*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[N]] 711*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]] 712*b3cba9beSMel Chen; CHECK-VF4IC4: [[EXIT]]: 713*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[COND_LCSSA:%.*]] = phi i64 [ [[COND]], %[[FOR_BODY]] ], [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ] 714*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: ret i64 [[COND_LCSSA]] 715*b3cba9beSMel Chen; 716*b3cba9beSMel Chen; CHECK-VF1IC4-LABEL: define i64 @select_fcmp_const_fast( 717*b3cba9beSMel Chen; CHECK-VF1IC4-SAME: ptr [[A:%.*]], i64 [[N:%.*]]) { 718*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[ENTRY:.*]]: 719*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4 720*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] 721*b3cba9beSMel Chen; CHECK-VF1IC4: [[VECTOR_PH]]: 722*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 4 723*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]] 724*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br label %[[VECTOR_BODY:.*]] 725*b3cba9beSMel Chen; CHECK-VF1IC4: [[VECTOR_BODY]]: 726*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] 727*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[VEC_PHI:%.*]] = phi i64 [ -9223372036854775808, %[[VECTOR_PH]] ], [ [[TMP16:%.*]], %[[VECTOR_BODY]] ] 728*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[VEC_PHI1:%.*]] = phi i64 [ -9223372036854775808, %[[VECTOR_PH]] ], [ [[TMP17:%.*]], %[[VECTOR_BODY]] ] 729*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[VEC_PHI2:%.*]] = phi i64 [ -9223372036854775808, %[[VECTOR_PH]] ], [ [[TMP18:%.*]], %[[VECTOR_BODY]] ] 730*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[VEC_PHI3:%.*]] = phi i64 [ -9223372036854775808, %[[VECTOR_PH]] ], [ [[TMP19:%.*]], %[[VECTOR_BODY]] ] 731*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 732*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1 733*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 2 734*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 3 735*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP4:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP0]] 736*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP5:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP1]] 737*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP6:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP2]] 738*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP7:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP3]] 739*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP8:%.*]] = load float, ptr [[TMP4]], align 4 740*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP9:%.*]] = load float, ptr [[TMP5]], align 4 741*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP10:%.*]] = load float, ptr [[TMP6]], align 4 742*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP11:%.*]] = load float, ptr [[TMP7]], align 4 743*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP12:%.*]] = fcmp fast ueq float [[TMP8]], 3.000000e+00 744*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP13:%.*]] = fcmp fast ueq float [[TMP9]], 3.000000e+00 745*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP14:%.*]] = fcmp fast ueq float [[TMP10]], 3.000000e+00 746*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP15:%.*]] = fcmp fast ueq float [[TMP11]], 3.000000e+00 747*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP16]] = select i1 [[TMP12]], i64 [[TMP0]], i64 [[VEC_PHI]] 748*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP17]] = select i1 [[TMP13]], i64 [[TMP1]], i64 [[VEC_PHI1]] 749*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP18]] = select i1 [[TMP14]], i64 [[TMP2]], i64 [[VEC_PHI2]] 750*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP19]] = select i1 [[TMP15]], i64 [[TMP3]], i64 [[VEC_PHI3]] 751*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 752*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 753*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br i1 [[TMP20]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]] 754*b3cba9beSMel Chen; CHECK-VF1IC4: [[MIDDLE_BLOCK]]: 755*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX_MINMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[TMP16]], i64 [[TMP17]]) 756*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX_MINMAX4:%.*]] = call i64 @llvm.smax.i64(i64 [[RDX_MINMAX]], i64 [[TMP18]]) 757*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX_MINMAX5:%.*]] = call i64 @llvm.smax.i64(i64 [[RDX_MINMAX4]], i64 [[TMP19]]) 758*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX_SELECT_CMP:%.*]] = icmp ne i64 [[RDX_MINMAX5]], -9223372036854775808 759*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX_SELECT:%.*]] = select i1 [[RDX_SELECT_CMP]], i64 [[RDX_MINMAX5]], i64 2 760*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] 761*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] 762*b3cba9beSMel Chen; CHECK-VF1IC4: [[SCALAR_PH]]: 763*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] 764*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ], [ 2, %[[ENTRY]] ] 765*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br label %[[FOR_BODY:.*]] 766*b3cba9beSMel Chen; CHECK-VF1IC4: [[FOR_BODY]]: 767*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[IV:%.*]] = phi i64 [ [[INC:%.*]], %[[FOR_BODY]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ] 768*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX:%.*]] = phi i64 [ [[COND:%.*]], %[[FOR_BODY]] ], [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ] 769*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[IV]] 770*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX]], align 4 771*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[CMP2:%.*]] = fcmp fast ueq float [[TMP21]], 3.000000e+00 772*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[COND]] = select i1 [[CMP2]], i64 [[IV]], i64 [[RDX]] 773*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[INC]] = add nuw nsw i64 [[IV]], 1 774*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[N]] 775*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]] 776*b3cba9beSMel Chen; CHECK-VF1IC4: [[EXIT]]: 777*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[COND_LCSSA:%.*]] = phi i64 [ [[COND]], %[[FOR_BODY]] ], [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ] 778*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: ret i64 [[COND_LCSSA]] 7794ddc1745SMel Chen; 7804ddc1745SMel Chenentry: 7814ddc1745SMel Chen br label %for.body 7824ddc1745SMel Chen 7834ddc1745SMel Chenfor.body: ; preds = %entry, %for.body 7844ddc1745SMel Chen %iv = phi i64 [ %inc, %for.body ], [ 0, %entry ] 7854ddc1745SMel Chen %rdx = phi i64 [ %cond, %for.body ], [ 2, %entry ] 7864ddc1745SMel Chen %arrayidx = getelementptr inbounds float, ptr %a, i64 %iv 7874ddc1745SMel Chen %0 = load float, ptr %arrayidx, align 4 7884ddc1745SMel Chen %cmp2 = fcmp fast ueq float %0, 3.0 7894ddc1745SMel Chen %cond = select i1 %cmp2, i64 %iv, i64 %rdx 7904ddc1745SMel Chen %inc = add nuw nsw i64 %iv, 1 7914ddc1745SMel Chen %exitcond.not = icmp eq i64 %inc, %n 7924ddc1745SMel Chen br i1 %exitcond.not, label %exit, label %for.body 7934ddc1745SMel Chen 7944ddc1745SMel Chenexit: ; preds = %for.body 7954ddc1745SMel Chen ret i64 %cond 7964ddc1745SMel Chen} 7974ddc1745SMel Chen 798707686b0SMel Chendefine i64 @select_fcmp_const(ptr %a, i64 %n) { 799*b3cba9beSMel Chen; CHECK-VF4IC1-LABEL: define i64 @select_fcmp_const( 800*b3cba9beSMel Chen; CHECK-VF4IC1-SAME: ptr [[A:%.*]], i64 [[N:%.*]]) { 801*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[ENTRY:.*]]: 802*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4 803*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] 804*b3cba9beSMel Chen; CHECK-VF4IC1: [[VECTOR_PH]]: 805*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 4 806*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]] 807*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br label %[[VECTOR_BODY:.*]] 808*b3cba9beSMel Chen; CHECK-VF4IC1: [[VECTOR_BODY]]: 809*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] 810*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] 811*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[VEC_PHI:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP4:%.*]], %[[VECTOR_BODY]] ] 812*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 813*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP1:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP0]] 814*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP2:%.*]] = getelementptr inbounds float, ptr [[TMP1]], i32 0 815*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[TMP2]], align 4 816*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP3:%.*]] = fcmp ueq <4 x float> [[WIDE_LOAD]], splat (float 3.000000e+00) 817*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP4]] = select <4 x i1> [[TMP3]], <4 x i64> [[VEC_IND]], <4 x i64> [[VEC_PHI]] 818*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 819*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[VEC_IND_NEXT]] = add <4 x i64> [[VEC_IND]], splat (i64 4) 820*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 821*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]] 822*b3cba9beSMel Chen; CHECK-VF4IC1: [[MIDDLE_BLOCK]]: 823*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP6:%.*]] = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> [[TMP4]]) 824*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[RDX_SELECT_CMP:%.*]] = icmp ne i64 [[TMP6]], -9223372036854775808 825*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[RDX_SELECT:%.*]] = select i1 [[RDX_SELECT_CMP]], i64 [[TMP6]], i64 2 826*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] 827*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] 828*b3cba9beSMel Chen; CHECK-VF4IC1: [[SCALAR_PH]]: 829*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] 830*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ], [ 2, %[[ENTRY]] ] 831*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br label %[[FOR_BODY:.*]] 832*b3cba9beSMel Chen; CHECK-VF4IC1: [[FOR_BODY]]: 833*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[IV:%.*]] = phi i64 [ [[INC:%.*]], %[[FOR_BODY]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ] 834*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[RDX:%.*]] = phi i64 [ [[COND:%.*]], %[[FOR_BODY]] ], [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ] 835*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[IV]] 836*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP7:%.*]] = load float, ptr [[ARRAYIDX]], align 4 837*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[CMP2:%.*]] = fcmp ueq float [[TMP7]], 3.000000e+00 838*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[COND]] = select i1 [[CMP2]], i64 [[IV]], i64 [[RDX]] 839*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[INC]] = add nuw nsw i64 [[IV]], 1 840*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[N]] 841*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]] 842*b3cba9beSMel Chen; CHECK-VF4IC1: [[EXIT]]: 843*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[COND_LCSSA:%.*]] = phi i64 [ [[COND]], %[[FOR_BODY]] ], [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ] 844*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: ret i64 [[COND_LCSSA]] 845*b3cba9beSMel Chen; 846*b3cba9beSMel Chen; CHECK-VF4IC4-LABEL: define i64 @select_fcmp_const( 847*b3cba9beSMel Chen; CHECK-VF4IC4-SAME: ptr [[A:%.*]], i64 [[N:%.*]]) { 848*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[ENTRY:.*]]: 849*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 16 850*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] 851*b3cba9beSMel Chen; CHECK-VF4IC4: [[VECTOR_PH]]: 852*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 16 853*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]] 854*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br label %[[VECTOR_BODY:.*]] 855*b3cba9beSMel Chen; CHECK-VF4IC4: [[VECTOR_BODY]]: 856*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] 857*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] 858*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[VEC_PHI:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP10:%.*]], %[[VECTOR_BODY]] ] 859*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP11:%.*]], %[[VECTOR_BODY]] ] 860*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP12:%.*]], %[[VECTOR_BODY]] ] 861*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP13:%.*]], %[[VECTOR_BODY]] ] 862*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[STEP_ADD:%.*]] = add <4 x i64> [[VEC_IND]], splat (i64 4) 863*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[STEP_ADD_2:%.*]] = add <4 x i64> [[STEP_ADD]], splat (i64 4) 864*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[STEP_ADD_3:%.*]] = add <4 x i64> [[STEP_ADD_2]], splat (i64 4) 865*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 866*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP1:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP0]] 867*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP2:%.*]] = getelementptr inbounds float, ptr [[TMP1]], i32 0 868*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP3:%.*]] = getelementptr inbounds float, ptr [[TMP1]], i32 4 869*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP4:%.*]] = getelementptr inbounds float, ptr [[TMP1]], i32 8 870*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP5:%.*]] = getelementptr inbounds float, ptr [[TMP1]], i32 12 871*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[TMP2]], align 4 872*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x float>, ptr [[TMP3]], align 4 873*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x float>, ptr [[TMP4]], align 4 874*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x float>, ptr [[TMP5]], align 4 875*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP6:%.*]] = fcmp ueq <4 x float> [[WIDE_LOAD]], splat (float 3.000000e+00) 876*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP7:%.*]] = fcmp ueq <4 x float> [[WIDE_LOAD4]], splat (float 3.000000e+00) 877*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP8:%.*]] = fcmp ueq <4 x float> [[WIDE_LOAD5]], splat (float 3.000000e+00) 878*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP9:%.*]] = fcmp ueq <4 x float> [[WIDE_LOAD6]], splat (float 3.000000e+00) 879*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP10]] = select <4 x i1> [[TMP6]], <4 x i64> [[VEC_IND]], <4 x i64> [[VEC_PHI]] 880*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP11]] = select <4 x i1> [[TMP7]], <4 x i64> [[STEP_ADD]], <4 x i64> [[VEC_PHI1]] 881*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP12]] = select <4 x i1> [[TMP8]], <4 x i64> [[STEP_ADD_2]], <4 x i64> [[VEC_PHI2]] 882*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP13]] = select <4 x i1> [[TMP9]], <4 x i64> [[STEP_ADD_3]], <4 x i64> [[VEC_PHI3]] 883*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 884*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[VEC_IND_NEXT]] = add <4 x i64> [[STEP_ADD_3]], splat (i64 4) 885*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP14:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 886*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br i1 [[TMP14]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]] 887*b3cba9beSMel Chen; CHECK-VF4IC4: [[MIDDLE_BLOCK]]: 888*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX_MINMAX:%.*]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[TMP10]], <4 x i64> [[TMP11]]) 889*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX_MINMAX7:%.*]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[RDX_MINMAX]], <4 x i64> [[TMP12]]) 890*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX_MINMAX8:%.*]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[RDX_MINMAX7]], <4 x i64> [[TMP13]]) 891*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP15:%.*]] = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> [[RDX_MINMAX8]]) 892*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX_SELECT_CMP:%.*]] = icmp ne i64 [[TMP15]], -9223372036854775808 893*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX_SELECT:%.*]] = select i1 [[RDX_SELECT_CMP]], i64 [[TMP15]], i64 2 894*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] 895*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] 896*b3cba9beSMel Chen; CHECK-VF4IC4: [[SCALAR_PH]]: 897*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] 898*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ], [ 2, %[[ENTRY]] ] 899*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br label %[[FOR_BODY:.*]] 900*b3cba9beSMel Chen; CHECK-VF4IC4: [[FOR_BODY]]: 901*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[IV:%.*]] = phi i64 [ [[INC:%.*]], %[[FOR_BODY]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ] 902*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX:%.*]] = phi i64 [ [[COND:%.*]], %[[FOR_BODY]] ], [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ] 903*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[IV]] 904*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP16:%.*]] = load float, ptr [[ARRAYIDX]], align 4 905*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[CMP2:%.*]] = fcmp ueq float [[TMP16]], 3.000000e+00 906*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[COND]] = select i1 [[CMP2]], i64 [[IV]], i64 [[RDX]] 907*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[INC]] = add nuw nsw i64 [[IV]], 1 908*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[N]] 909*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]] 910*b3cba9beSMel Chen; CHECK-VF4IC4: [[EXIT]]: 911*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[COND_LCSSA:%.*]] = phi i64 [ [[COND]], %[[FOR_BODY]] ], [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ] 912*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: ret i64 [[COND_LCSSA]] 913*b3cba9beSMel Chen; 914*b3cba9beSMel Chen; CHECK-VF1IC4-LABEL: define i64 @select_fcmp_const( 915*b3cba9beSMel Chen; CHECK-VF1IC4-SAME: ptr [[A:%.*]], i64 [[N:%.*]]) { 916*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[ENTRY:.*]]: 917*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4 918*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] 919*b3cba9beSMel Chen; CHECK-VF1IC4: [[VECTOR_PH]]: 920*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 4 921*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]] 922*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br label %[[VECTOR_BODY:.*]] 923*b3cba9beSMel Chen; CHECK-VF1IC4: [[VECTOR_BODY]]: 924*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] 925*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[VEC_PHI:%.*]] = phi i64 [ -9223372036854775808, %[[VECTOR_PH]] ], [ [[TMP16:%.*]], %[[VECTOR_BODY]] ] 926*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[VEC_PHI1:%.*]] = phi i64 [ -9223372036854775808, %[[VECTOR_PH]] ], [ [[TMP17:%.*]], %[[VECTOR_BODY]] ] 927*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[VEC_PHI2:%.*]] = phi i64 [ -9223372036854775808, %[[VECTOR_PH]] ], [ [[TMP18:%.*]], %[[VECTOR_BODY]] ] 928*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[VEC_PHI3:%.*]] = phi i64 [ -9223372036854775808, %[[VECTOR_PH]] ], [ [[TMP19:%.*]], %[[VECTOR_BODY]] ] 929*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 930*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1 931*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 2 932*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 3 933*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP4:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP0]] 934*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP5:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP1]] 935*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP6:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP2]] 936*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP7:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP3]] 937*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP8:%.*]] = load float, ptr [[TMP4]], align 4 938*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP9:%.*]] = load float, ptr [[TMP5]], align 4 939*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP10:%.*]] = load float, ptr [[TMP6]], align 4 940*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP11:%.*]] = load float, ptr [[TMP7]], align 4 941*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP12:%.*]] = fcmp ueq float [[TMP8]], 3.000000e+00 942*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP13:%.*]] = fcmp ueq float [[TMP9]], 3.000000e+00 943*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP14:%.*]] = fcmp ueq float [[TMP10]], 3.000000e+00 944*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP15:%.*]] = fcmp ueq float [[TMP11]], 3.000000e+00 945*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP16]] = select i1 [[TMP12]], i64 [[TMP0]], i64 [[VEC_PHI]] 946*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP17]] = select i1 [[TMP13]], i64 [[TMP1]], i64 [[VEC_PHI1]] 947*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP18]] = select i1 [[TMP14]], i64 [[TMP2]], i64 [[VEC_PHI2]] 948*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP19]] = select i1 [[TMP15]], i64 [[TMP3]], i64 [[VEC_PHI3]] 949*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 950*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP20:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 951*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br i1 [[TMP20]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]] 952*b3cba9beSMel Chen; CHECK-VF1IC4: [[MIDDLE_BLOCK]]: 953*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX_MINMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[TMP16]], i64 [[TMP17]]) 954*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX_MINMAX4:%.*]] = call i64 @llvm.smax.i64(i64 [[RDX_MINMAX]], i64 [[TMP18]]) 955*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX_MINMAX5:%.*]] = call i64 @llvm.smax.i64(i64 [[RDX_MINMAX4]], i64 [[TMP19]]) 956*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX_SELECT_CMP:%.*]] = icmp ne i64 [[RDX_MINMAX5]], -9223372036854775808 957*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX_SELECT:%.*]] = select i1 [[RDX_SELECT_CMP]], i64 [[RDX_MINMAX5]], i64 2 958*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] 959*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] 960*b3cba9beSMel Chen; CHECK-VF1IC4: [[SCALAR_PH]]: 961*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] 962*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ], [ 2, %[[ENTRY]] ] 963*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br label %[[FOR_BODY:.*]] 964*b3cba9beSMel Chen; CHECK-VF1IC4: [[FOR_BODY]]: 965*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[IV:%.*]] = phi i64 [ [[INC:%.*]], %[[FOR_BODY]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ] 966*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX:%.*]] = phi i64 [ [[COND:%.*]], %[[FOR_BODY]] ], [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ] 967*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[IV]] 968*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX]], align 4 969*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[CMP2:%.*]] = fcmp ueq float [[TMP21]], 3.000000e+00 970*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[COND]] = select i1 [[CMP2]], i64 [[IV]], i64 [[RDX]] 971*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[INC]] = add nuw nsw i64 [[IV]], 1 972*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[N]] 973*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]] 974*b3cba9beSMel Chen; CHECK-VF1IC4: [[EXIT]]: 975*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[COND_LCSSA:%.*]] = phi i64 [ [[COND]], %[[FOR_BODY]] ], [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ] 976*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: ret i64 [[COND_LCSSA]] 9774ddc1745SMel Chen; 9784ddc1745SMel Chenentry: 9794ddc1745SMel Chen br label %for.body 9804ddc1745SMel Chen 9814ddc1745SMel Chenfor.body: ; preds = %entry, %for.body 9824ddc1745SMel Chen %iv = phi i64 [ %inc, %for.body ], [ 0, %entry ] 9834ddc1745SMel Chen %rdx = phi i64 [ %cond, %for.body ], [ 2, %entry ] 9844ddc1745SMel Chen %arrayidx = getelementptr inbounds float, ptr %a, i64 %iv 9854ddc1745SMel Chen %0 = load float, ptr %arrayidx, align 4 9864ddc1745SMel Chen %cmp2 = fcmp ueq float %0, 3.0 9874ddc1745SMel Chen %cond = select i1 %cmp2, i64 %iv, i64 %rdx 9884ddc1745SMel Chen %inc = add nuw nsw i64 %iv, 1 9894ddc1745SMel Chen %exitcond.not = icmp eq i64 %inc, %n 9904ddc1745SMel Chen br i1 %exitcond.not, label %exit, label %for.body 9914ddc1745SMel Chen 9924ddc1745SMel Chenexit: ; preds = %for.body 9934ddc1745SMel Chen ret i64 %cond 9944ddc1745SMel Chen} 9954ddc1745SMel Chen 996707686b0SMel Chendefine i64 @select_icmp(ptr %a, ptr %b, i64 %rdx.start, i64 %n) { 997*b3cba9beSMel Chen; CHECK-VF4IC1-LABEL: define i64 @select_icmp( 998*b3cba9beSMel Chen; CHECK-VF4IC1-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[RDX_START:%.*]], i64 [[N:%.*]]) { 999*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[ENTRY:.*]]: 1000*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4 1001*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] 1002*b3cba9beSMel Chen; CHECK-VF4IC1: [[VECTOR_PH]]: 1003*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 4 1004*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]] 1005*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br label %[[VECTOR_BODY:.*]] 1006*b3cba9beSMel Chen; CHECK-VF4IC1: [[VECTOR_BODY]]: 1007*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] 1008*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] 1009*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[VEC_PHI:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP6:%.*]], %[[VECTOR_BODY]] ] 1010*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 1011*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP0]] 1012*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0 1013*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP2]], align 8 1014*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[TMP0]] 1015*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP3]], i32 0 1016*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x i64>, ptr [[TMP4]], align 8 1017*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP5:%.*]] = icmp sgt <4 x i64> [[WIDE_LOAD]], [[WIDE_LOAD1]] 1018*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP6]] = select <4 x i1> [[TMP5]], <4 x i64> [[VEC_IND]], <4 x i64> [[VEC_PHI]] 1019*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 1020*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[VEC_IND_NEXT]] = add <4 x i64> [[VEC_IND]], splat (i64 4) 1021*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 1022*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]] 1023*b3cba9beSMel Chen; CHECK-VF4IC1: [[MIDDLE_BLOCK]]: 1024*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP8:%.*]] = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> [[TMP6]]) 1025*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[RDX_SELECT_CMP:%.*]] = icmp ne i64 [[TMP8]], -9223372036854775808 1026*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[RDX_SELECT:%.*]] = select i1 [[RDX_SELECT_CMP]], i64 [[TMP8]], i64 [[RDX_START]] 1027*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] 1028*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] 1029*b3cba9beSMel Chen; CHECK-VF4IC1: [[SCALAR_PH]]: 1030*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] 1031*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ], [ [[RDX_START]], %[[ENTRY]] ] 1032*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br label %[[FOR_BODY:.*]] 1033*b3cba9beSMel Chen; CHECK-VF4IC1: [[FOR_BODY]]: 1034*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[IV:%.*]] = phi i64 [ [[INC:%.*]], %[[FOR_BODY]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ] 1035*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[RDX:%.*]] = phi i64 [ [[COND:%.*]], %[[FOR_BODY]] ], [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ] 1036*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]] 1037*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP9:%.*]] = load i64, ptr [[ARRAYIDX]], align 8 1038*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[IV]] 1039*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP10:%.*]] = load i64, ptr [[ARRAYIDX1]], align 8 1040*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[CMP2:%.*]] = icmp sgt i64 [[TMP9]], [[TMP10]] 1041*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[COND]] = select i1 [[CMP2]], i64 [[IV]], i64 [[RDX]] 1042*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[INC]] = add nuw nsw i64 [[IV]], 1 1043*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[N]] 1044*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]] 1045*b3cba9beSMel Chen; CHECK-VF4IC1: [[EXIT]]: 1046*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[COND_LCSSA:%.*]] = phi i64 [ [[COND]], %[[FOR_BODY]] ], [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ] 1047*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: ret i64 [[COND_LCSSA]] 1048*b3cba9beSMel Chen; 1049*b3cba9beSMel Chen; CHECK-VF4IC4-LABEL: define i64 @select_icmp( 1050*b3cba9beSMel Chen; CHECK-VF4IC4-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[RDX_START:%.*]], i64 [[N:%.*]]) { 1051*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[ENTRY:.*]]: 1052*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 16 1053*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] 1054*b3cba9beSMel Chen; CHECK-VF4IC4: [[VECTOR_PH]]: 1055*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 16 1056*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]] 1057*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br label %[[VECTOR_BODY:.*]] 1058*b3cba9beSMel Chen; CHECK-VF4IC4: [[VECTOR_BODY]]: 1059*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] 1060*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] 1061*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[VEC_PHI:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP15:%.*]], %[[VECTOR_BODY]] ] 1062*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP16:%.*]], %[[VECTOR_BODY]] ] 1063*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP17:%.*]], %[[VECTOR_BODY]] ] 1064*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP18:%.*]], %[[VECTOR_BODY]] ] 1065*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[STEP_ADD:%.*]] = add <4 x i64> [[VEC_IND]], splat (i64 4) 1066*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[STEP_ADD_2:%.*]] = add <4 x i64> [[STEP_ADD]], splat (i64 4) 1067*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[STEP_ADD_3:%.*]] = add <4 x i64> [[STEP_ADD_2]], splat (i64 4) 1068*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 1069*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP0]] 1070*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0 1071*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 4 1072*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 8 1073*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 12 1074*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP2]], align 8 1075*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x i64>, ptr [[TMP3]], align 8 1076*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x i64>, ptr [[TMP4]], align 8 1077*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x i64>, ptr [[TMP5]], align 8 1078*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[TMP0]] 1079*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[TMP6]], i32 0 1080*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP8:%.*]] = getelementptr inbounds i64, ptr [[TMP6]], i32 4 1081*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP9:%.*]] = getelementptr inbounds i64, ptr [[TMP6]], i32 8 1082*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP10:%.*]] = getelementptr inbounds i64, ptr [[TMP6]], i32 12 1083*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[WIDE_LOAD7:%.*]] = load <4 x i64>, ptr [[TMP7]], align 8 1084*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[WIDE_LOAD8:%.*]] = load <4 x i64>, ptr [[TMP8]], align 8 1085*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[WIDE_LOAD9:%.*]] = load <4 x i64>, ptr [[TMP9]], align 8 1086*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[WIDE_LOAD10:%.*]] = load <4 x i64>, ptr [[TMP10]], align 8 1087*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP11:%.*]] = icmp sgt <4 x i64> [[WIDE_LOAD]], [[WIDE_LOAD7]] 1088*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP12:%.*]] = icmp sgt <4 x i64> [[WIDE_LOAD4]], [[WIDE_LOAD8]] 1089*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP13:%.*]] = icmp sgt <4 x i64> [[WIDE_LOAD5]], [[WIDE_LOAD9]] 1090*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP14:%.*]] = icmp sgt <4 x i64> [[WIDE_LOAD6]], [[WIDE_LOAD10]] 1091*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP15]] = select <4 x i1> [[TMP11]], <4 x i64> [[VEC_IND]], <4 x i64> [[VEC_PHI]] 1092*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP16]] = select <4 x i1> [[TMP12]], <4 x i64> [[STEP_ADD]], <4 x i64> [[VEC_PHI1]] 1093*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP17]] = select <4 x i1> [[TMP13]], <4 x i64> [[STEP_ADD_2]], <4 x i64> [[VEC_PHI2]] 1094*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP18]] = select <4 x i1> [[TMP14]], <4 x i64> [[STEP_ADD_3]], <4 x i64> [[VEC_PHI3]] 1095*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 1096*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[VEC_IND_NEXT]] = add <4 x i64> [[STEP_ADD_3]], splat (i64 4) 1097*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP19:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 1098*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br i1 [[TMP19]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]] 1099*b3cba9beSMel Chen; CHECK-VF4IC4: [[MIDDLE_BLOCK]]: 1100*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX_MINMAX:%.*]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[TMP15]], <4 x i64> [[TMP16]]) 1101*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX_MINMAX11:%.*]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[RDX_MINMAX]], <4 x i64> [[TMP17]]) 1102*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX_MINMAX12:%.*]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[RDX_MINMAX11]], <4 x i64> [[TMP18]]) 1103*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP20:%.*]] = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> [[RDX_MINMAX12]]) 1104*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX_SELECT_CMP:%.*]] = icmp ne i64 [[TMP20]], -9223372036854775808 1105*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX_SELECT:%.*]] = select i1 [[RDX_SELECT_CMP]], i64 [[TMP20]], i64 [[RDX_START]] 1106*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] 1107*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] 1108*b3cba9beSMel Chen; CHECK-VF4IC4: [[SCALAR_PH]]: 1109*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] 1110*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ], [ [[RDX_START]], %[[ENTRY]] ] 1111*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br label %[[FOR_BODY:.*]] 1112*b3cba9beSMel Chen; CHECK-VF4IC4: [[FOR_BODY]]: 1113*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[IV:%.*]] = phi i64 [ [[INC:%.*]], %[[FOR_BODY]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ] 1114*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX:%.*]] = phi i64 [ [[COND:%.*]], %[[FOR_BODY]] ], [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ] 1115*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]] 1116*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP21:%.*]] = load i64, ptr [[ARRAYIDX]], align 8 1117*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[IV]] 1118*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP22:%.*]] = load i64, ptr [[ARRAYIDX1]], align 8 1119*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[CMP2:%.*]] = icmp sgt i64 [[TMP21]], [[TMP22]] 1120*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[COND]] = select i1 [[CMP2]], i64 [[IV]], i64 [[RDX]] 1121*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[INC]] = add nuw nsw i64 [[IV]], 1 1122*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[N]] 1123*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]] 1124*b3cba9beSMel Chen; CHECK-VF4IC4: [[EXIT]]: 1125*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[COND_LCSSA:%.*]] = phi i64 [ [[COND]], %[[FOR_BODY]] ], [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ] 1126*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: ret i64 [[COND_LCSSA]] 1127*b3cba9beSMel Chen; 1128*b3cba9beSMel Chen; CHECK-VF1IC4-LABEL: define i64 @select_icmp( 1129*b3cba9beSMel Chen; CHECK-VF1IC4-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[RDX_START:%.*]], i64 [[N:%.*]]) { 1130*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[ENTRY:.*]]: 1131*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4 1132*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] 1133*b3cba9beSMel Chen; CHECK-VF1IC4: [[VECTOR_PH]]: 1134*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 4 1135*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]] 1136*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br label %[[VECTOR_BODY:.*]] 1137*b3cba9beSMel Chen; CHECK-VF1IC4: [[VECTOR_BODY]]: 1138*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] 1139*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[VEC_PHI:%.*]] = phi i64 [ -9223372036854775808, %[[VECTOR_PH]] ], [ [[TMP24:%.*]], %[[VECTOR_BODY]] ] 1140*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[VEC_PHI1:%.*]] = phi i64 [ -9223372036854775808, %[[VECTOR_PH]] ], [ [[TMP25:%.*]], %[[VECTOR_BODY]] ] 1141*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[VEC_PHI2:%.*]] = phi i64 [ -9223372036854775808, %[[VECTOR_PH]] ], [ [[TMP26:%.*]], %[[VECTOR_BODY]] ] 1142*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[VEC_PHI3:%.*]] = phi i64 [ -9223372036854775808, %[[VECTOR_PH]] ], [ [[TMP27:%.*]], %[[VECTOR_BODY]] ] 1143*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 1144*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1 1145*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 2 1146*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 3 1147*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP0]] 1148*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP1]] 1149*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP2]] 1150*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP3]] 1151*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP8:%.*]] = load i64, ptr [[TMP4]], align 8 1152*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP9:%.*]] = load i64, ptr [[TMP5]], align 8 1153*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP10:%.*]] = load i64, ptr [[TMP6]], align 8 1154*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP11:%.*]] = load i64, ptr [[TMP7]], align 8 1155*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP12:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[TMP0]] 1156*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP13:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[TMP1]] 1157*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP14:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[TMP2]] 1158*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP15:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[TMP3]] 1159*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP16:%.*]] = load i64, ptr [[TMP12]], align 8 1160*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP17:%.*]] = load i64, ptr [[TMP13]], align 8 1161*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP18:%.*]] = load i64, ptr [[TMP14]], align 8 1162*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP19:%.*]] = load i64, ptr [[TMP15]], align 8 1163*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP20:%.*]] = icmp sgt i64 [[TMP8]], [[TMP16]] 1164*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP21:%.*]] = icmp sgt i64 [[TMP9]], [[TMP17]] 1165*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP22:%.*]] = icmp sgt i64 [[TMP10]], [[TMP18]] 1166*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP23:%.*]] = icmp sgt i64 [[TMP11]], [[TMP19]] 1167*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP24]] = select i1 [[TMP20]], i64 [[TMP0]], i64 [[VEC_PHI]] 1168*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP25]] = select i1 [[TMP21]], i64 [[TMP1]], i64 [[VEC_PHI1]] 1169*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP26]] = select i1 [[TMP22]], i64 [[TMP2]], i64 [[VEC_PHI2]] 1170*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP27]] = select i1 [[TMP23]], i64 [[TMP3]], i64 [[VEC_PHI3]] 1171*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 1172*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP28:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 1173*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br i1 [[TMP28]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]] 1174*b3cba9beSMel Chen; CHECK-VF1IC4: [[MIDDLE_BLOCK]]: 1175*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX_MINMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[TMP24]], i64 [[TMP25]]) 1176*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX_MINMAX4:%.*]] = call i64 @llvm.smax.i64(i64 [[RDX_MINMAX]], i64 [[TMP26]]) 1177*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX_MINMAX5:%.*]] = call i64 @llvm.smax.i64(i64 [[RDX_MINMAX4]], i64 [[TMP27]]) 1178*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX_SELECT_CMP:%.*]] = icmp ne i64 [[RDX_MINMAX5]], -9223372036854775808 1179*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX_SELECT:%.*]] = select i1 [[RDX_SELECT_CMP]], i64 [[RDX_MINMAX5]], i64 [[RDX_START]] 1180*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] 1181*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] 1182*b3cba9beSMel Chen; CHECK-VF1IC4: [[SCALAR_PH]]: 1183*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] 1184*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ], [ [[RDX_START]], %[[ENTRY]] ] 1185*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br label %[[FOR_BODY:.*]] 1186*b3cba9beSMel Chen; CHECK-VF1IC4: [[FOR_BODY]]: 1187*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[IV:%.*]] = phi i64 [ [[INC:%.*]], %[[FOR_BODY]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ] 1188*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX:%.*]] = phi i64 [ [[COND:%.*]], %[[FOR_BODY]] ], [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ] 1189*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]] 1190*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP29:%.*]] = load i64, ptr [[ARRAYIDX]], align 8 1191*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[IV]] 1192*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP30:%.*]] = load i64, ptr [[ARRAYIDX1]], align 8 1193*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[CMP2:%.*]] = icmp sgt i64 [[TMP29]], [[TMP30]] 1194*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[COND]] = select i1 [[CMP2]], i64 [[IV]], i64 [[RDX]] 1195*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[INC]] = add nuw nsw i64 [[IV]], 1 1196*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[N]] 1197*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]] 1198*b3cba9beSMel Chen; CHECK-VF1IC4: [[EXIT]]: 1199*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[COND_LCSSA:%.*]] = phi i64 [ [[COND]], %[[FOR_BODY]] ], [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ] 1200*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: ret i64 [[COND_LCSSA]] 12014ddc1745SMel Chen; 12024ddc1745SMel Chenentry: 12034ddc1745SMel Chen br label %for.body 12044ddc1745SMel Chen 12054ddc1745SMel Chenfor.body: ; preds = %entry, %for.body 12064ddc1745SMel Chen %iv = phi i64 [ %inc, %for.body ], [ 0, %entry ] 12074ddc1745SMel Chen %rdx = phi i64 [ %cond, %for.body ], [ %rdx.start, %entry ] 12084ddc1745SMel Chen %arrayidx = getelementptr inbounds i64, ptr %a, i64 %iv 12094ddc1745SMel Chen %0 = load i64, ptr %arrayidx, align 8 12104ddc1745SMel Chen %arrayidx1 = getelementptr inbounds i64, ptr %b, i64 %iv 12114ddc1745SMel Chen %1 = load i64, ptr %arrayidx1, align 8 12124ddc1745SMel Chen %cmp2 = icmp sgt i64 %0, %1 12134ddc1745SMel Chen %cond = select i1 %cmp2, i64 %iv, i64 %rdx 12144ddc1745SMel Chen %inc = add nuw nsw i64 %iv, 1 12154ddc1745SMel Chen %exitcond.not = icmp eq i64 %inc, %n 12164ddc1745SMel Chen br i1 %exitcond.not, label %exit, label %for.body 12174ddc1745SMel Chen 12184ddc1745SMel Chenexit: ; preds = %for.body 12194ddc1745SMel Chen ret i64 %cond 12204ddc1745SMel Chen} 12214ddc1745SMel Chen 1222707686b0SMel Chendefine i64 @select_fcmp(ptr %a, ptr %b, i64 %rdx.start, i64 %n) { 1223*b3cba9beSMel Chen; CHECK-VF4IC1-LABEL: define i64 @select_fcmp( 1224*b3cba9beSMel Chen; CHECK-VF4IC1-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[RDX_START:%.*]], i64 [[N:%.*]]) { 1225*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[ENTRY:.*]]: 1226*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4 1227*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] 1228*b3cba9beSMel Chen; CHECK-VF4IC1: [[VECTOR_PH]]: 1229*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 4 1230*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]] 1231*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br label %[[VECTOR_BODY:.*]] 1232*b3cba9beSMel Chen; CHECK-VF4IC1: [[VECTOR_BODY]]: 1233*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] 1234*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] 1235*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[VEC_PHI:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP6:%.*]], %[[VECTOR_BODY]] ] 1236*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 1237*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP1:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP0]] 1238*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP2:%.*]] = getelementptr inbounds float, ptr [[TMP1]], i32 0 1239*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[TMP2]], align 4 1240*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP3:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP0]] 1241*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP4:%.*]] = getelementptr inbounds float, ptr [[TMP3]], i32 0 1242*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x float>, ptr [[TMP4]], align 4 1243*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP5:%.*]] = fcmp ogt <4 x float> [[WIDE_LOAD]], [[WIDE_LOAD1]] 1244*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP6]] = select <4 x i1> [[TMP5]], <4 x i64> [[VEC_IND]], <4 x i64> [[VEC_PHI]] 1245*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 1246*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[VEC_IND_NEXT]] = add <4 x i64> [[VEC_IND]], splat (i64 4) 1247*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 1248*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP14:![0-9]+]] 1249*b3cba9beSMel Chen; CHECK-VF4IC1: [[MIDDLE_BLOCK]]: 1250*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP8:%.*]] = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> [[TMP6]]) 1251*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[RDX_SELECT_CMP:%.*]] = icmp ne i64 [[TMP8]], -9223372036854775808 1252*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[RDX_SELECT:%.*]] = select i1 [[RDX_SELECT_CMP]], i64 [[TMP8]], i64 [[RDX_START]] 1253*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] 1254*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] 1255*b3cba9beSMel Chen; CHECK-VF4IC1: [[SCALAR_PH]]: 1256*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] 1257*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ], [ [[RDX_START]], %[[ENTRY]] ] 1258*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br label %[[FOR_BODY:.*]] 1259*b3cba9beSMel Chen; CHECK-VF4IC1: [[FOR_BODY]]: 1260*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[IV:%.*]] = phi i64 [ [[INC:%.*]], %[[FOR_BODY]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ] 1261*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[RDX:%.*]] = phi i64 [ [[COND:%.*]], %[[FOR_BODY]] ], [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ] 1262*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[IV]] 1263*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP9:%.*]] = load float, ptr [[ARRAYIDX]], align 4 1264*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[IV]] 1265*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP10:%.*]] = load float, ptr [[ARRAYIDX1]], align 4 1266*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[CMP2:%.*]] = fcmp ogt float [[TMP9]], [[TMP10]] 1267*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[COND]] = select i1 [[CMP2]], i64 [[IV]], i64 [[RDX]] 1268*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[INC]] = add nuw nsw i64 [[IV]], 1 1269*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[N]] 1270*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP15:![0-9]+]] 1271*b3cba9beSMel Chen; CHECK-VF4IC1: [[EXIT]]: 1272*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[COND_LCSSA:%.*]] = phi i64 [ [[COND]], %[[FOR_BODY]] ], [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ] 1273*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: ret i64 [[COND_LCSSA]] 1274*b3cba9beSMel Chen; 1275*b3cba9beSMel Chen; CHECK-VF4IC4-LABEL: define i64 @select_fcmp( 1276*b3cba9beSMel Chen; CHECK-VF4IC4-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[RDX_START:%.*]], i64 [[N:%.*]]) { 1277*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[ENTRY:.*]]: 1278*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 16 1279*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] 1280*b3cba9beSMel Chen; CHECK-VF4IC4: [[VECTOR_PH]]: 1281*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 16 1282*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]] 1283*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br label %[[VECTOR_BODY:.*]] 1284*b3cba9beSMel Chen; CHECK-VF4IC4: [[VECTOR_BODY]]: 1285*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] 1286*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] 1287*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[VEC_PHI:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP15:%.*]], %[[VECTOR_BODY]] ] 1288*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP16:%.*]], %[[VECTOR_BODY]] ] 1289*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP17:%.*]], %[[VECTOR_BODY]] ] 1290*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP18:%.*]], %[[VECTOR_BODY]] ] 1291*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[STEP_ADD:%.*]] = add <4 x i64> [[VEC_IND]], splat (i64 4) 1292*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[STEP_ADD_2:%.*]] = add <4 x i64> [[STEP_ADD]], splat (i64 4) 1293*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[STEP_ADD_3:%.*]] = add <4 x i64> [[STEP_ADD_2]], splat (i64 4) 1294*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 1295*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP1:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP0]] 1296*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP2:%.*]] = getelementptr inbounds float, ptr [[TMP1]], i32 0 1297*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP3:%.*]] = getelementptr inbounds float, ptr [[TMP1]], i32 4 1298*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP4:%.*]] = getelementptr inbounds float, ptr [[TMP1]], i32 8 1299*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP5:%.*]] = getelementptr inbounds float, ptr [[TMP1]], i32 12 1300*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[TMP2]], align 4 1301*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x float>, ptr [[TMP3]], align 4 1302*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x float>, ptr [[TMP4]], align 4 1303*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x float>, ptr [[TMP5]], align 4 1304*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP6:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP0]] 1305*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP7:%.*]] = getelementptr inbounds float, ptr [[TMP6]], i32 0 1306*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP8:%.*]] = getelementptr inbounds float, ptr [[TMP6]], i32 4 1307*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP9:%.*]] = getelementptr inbounds float, ptr [[TMP6]], i32 8 1308*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP10:%.*]] = getelementptr inbounds float, ptr [[TMP6]], i32 12 1309*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[WIDE_LOAD7:%.*]] = load <4 x float>, ptr [[TMP7]], align 4 1310*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[WIDE_LOAD8:%.*]] = load <4 x float>, ptr [[TMP8]], align 4 1311*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[WIDE_LOAD9:%.*]] = load <4 x float>, ptr [[TMP9]], align 4 1312*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[WIDE_LOAD10:%.*]] = load <4 x float>, ptr [[TMP10]], align 4 1313*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP11:%.*]] = fcmp ogt <4 x float> [[WIDE_LOAD]], [[WIDE_LOAD7]] 1314*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP12:%.*]] = fcmp ogt <4 x float> [[WIDE_LOAD4]], [[WIDE_LOAD8]] 1315*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP13:%.*]] = fcmp ogt <4 x float> [[WIDE_LOAD5]], [[WIDE_LOAD9]] 1316*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP14:%.*]] = fcmp ogt <4 x float> [[WIDE_LOAD6]], [[WIDE_LOAD10]] 1317*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP15]] = select <4 x i1> [[TMP11]], <4 x i64> [[VEC_IND]], <4 x i64> [[VEC_PHI]] 1318*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP16]] = select <4 x i1> [[TMP12]], <4 x i64> [[STEP_ADD]], <4 x i64> [[VEC_PHI1]] 1319*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP17]] = select <4 x i1> [[TMP13]], <4 x i64> [[STEP_ADD_2]], <4 x i64> [[VEC_PHI2]] 1320*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP18]] = select <4 x i1> [[TMP14]], <4 x i64> [[STEP_ADD_3]], <4 x i64> [[VEC_PHI3]] 1321*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 1322*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[VEC_IND_NEXT]] = add <4 x i64> [[STEP_ADD_3]], splat (i64 4) 1323*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP19:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 1324*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br i1 [[TMP19]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP14:![0-9]+]] 1325*b3cba9beSMel Chen; CHECK-VF4IC4: [[MIDDLE_BLOCK]]: 1326*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX_MINMAX:%.*]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[TMP15]], <4 x i64> [[TMP16]]) 1327*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX_MINMAX11:%.*]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[RDX_MINMAX]], <4 x i64> [[TMP17]]) 1328*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX_MINMAX12:%.*]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[RDX_MINMAX11]], <4 x i64> [[TMP18]]) 1329*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP20:%.*]] = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> [[RDX_MINMAX12]]) 1330*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX_SELECT_CMP:%.*]] = icmp ne i64 [[TMP20]], -9223372036854775808 1331*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX_SELECT:%.*]] = select i1 [[RDX_SELECT_CMP]], i64 [[TMP20]], i64 [[RDX_START]] 1332*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] 1333*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] 1334*b3cba9beSMel Chen; CHECK-VF4IC4: [[SCALAR_PH]]: 1335*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] 1336*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ], [ [[RDX_START]], %[[ENTRY]] ] 1337*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br label %[[FOR_BODY:.*]] 1338*b3cba9beSMel Chen; CHECK-VF4IC4: [[FOR_BODY]]: 1339*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[IV:%.*]] = phi i64 [ [[INC:%.*]], %[[FOR_BODY]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ] 1340*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX:%.*]] = phi i64 [ [[COND:%.*]], %[[FOR_BODY]] ], [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ] 1341*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[IV]] 1342*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP21:%.*]] = load float, ptr [[ARRAYIDX]], align 4 1343*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[IV]] 1344*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP22:%.*]] = load float, ptr [[ARRAYIDX1]], align 4 1345*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[CMP2:%.*]] = fcmp ogt float [[TMP21]], [[TMP22]] 1346*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[COND]] = select i1 [[CMP2]], i64 [[IV]], i64 [[RDX]] 1347*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[INC]] = add nuw nsw i64 [[IV]], 1 1348*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[N]] 1349*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP15:![0-9]+]] 1350*b3cba9beSMel Chen; CHECK-VF4IC4: [[EXIT]]: 1351*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[COND_LCSSA:%.*]] = phi i64 [ [[COND]], %[[FOR_BODY]] ], [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ] 1352*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: ret i64 [[COND_LCSSA]] 1353*b3cba9beSMel Chen; 1354*b3cba9beSMel Chen; CHECK-VF1IC4-LABEL: define i64 @select_fcmp( 1355*b3cba9beSMel Chen; CHECK-VF1IC4-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[RDX_START:%.*]], i64 [[N:%.*]]) { 1356*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[ENTRY:.*]]: 1357*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4 1358*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] 1359*b3cba9beSMel Chen; CHECK-VF1IC4: [[VECTOR_PH]]: 1360*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 4 1361*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]] 1362*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br label %[[VECTOR_BODY:.*]] 1363*b3cba9beSMel Chen; CHECK-VF1IC4: [[VECTOR_BODY]]: 1364*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] 1365*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[VEC_PHI:%.*]] = phi i64 [ -9223372036854775808, %[[VECTOR_PH]] ], [ [[TMP24:%.*]], %[[VECTOR_BODY]] ] 1366*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[VEC_PHI1:%.*]] = phi i64 [ -9223372036854775808, %[[VECTOR_PH]] ], [ [[TMP25:%.*]], %[[VECTOR_BODY]] ] 1367*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[VEC_PHI2:%.*]] = phi i64 [ -9223372036854775808, %[[VECTOR_PH]] ], [ [[TMP26:%.*]], %[[VECTOR_BODY]] ] 1368*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[VEC_PHI3:%.*]] = phi i64 [ -9223372036854775808, %[[VECTOR_PH]] ], [ [[TMP27:%.*]], %[[VECTOR_BODY]] ] 1369*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 1370*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1 1371*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 2 1372*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 3 1373*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP4:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP0]] 1374*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP5:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP1]] 1375*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP6:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP2]] 1376*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP7:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP3]] 1377*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP8:%.*]] = load float, ptr [[TMP4]], align 4 1378*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP9:%.*]] = load float, ptr [[TMP5]], align 4 1379*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP10:%.*]] = load float, ptr [[TMP6]], align 4 1380*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP11:%.*]] = load float, ptr [[TMP7]], align 4 1381*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP12:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP0]] 1382*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP13:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP1]] 1383*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP14:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP2]] 1384*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP15:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP3]] 1385*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP16:%.*]] = load float, ptr [[TMP12]], align 4 1386*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP17:%.*]] = load float, ptr [[TMP13]], align 4 1387*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP18:%.*]] = load float, ptr [[TMP14]], align 4 1388*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP19:%.*]] = load float, ptr [[TMP15]], align 4 1389*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP20:%.*]] = fcmp ogt float [[TMP8]], [[TMP16]] 1390*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP21:%.*]] = fcmp ogt float [[TMP9]], [[TMP17]] 1391*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP22:%.*]] = fcmp ogt float [[TMP10]], [[TMP18]] 1392*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP23:%.*]] = fcmp ogt float [[TMP11]], [[TMP19]] 1393*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP24]] = select i1 [[TMP20]], i64 [[TMP0]], i64 [[VEC_PHI]] 1394*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP25]] = select i1 [[TMP21]], i64 [[TMP1]], i64 [[VEC_PHI1]] 1395*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP26]] = select i1 [[TMP22]], i64 [[TMP2]], i64 [[VEC_PHI2]] 1396*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP27]] = select i1 [[TMP23]], i64 [[TMP3]], i64 [[VEC_PHI3]] 1397*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 1398*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP28:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 1399*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br i1 [[TMP28]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP14:![0-9]+]] 1400*b3cba9beSMel Chen; CHECK-VF1IC4: [[MIDDLE_BLOCK]]: 1401*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX_MINMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[TMP24]], i64 [[TMP25]]) 1402*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX_MINMAX4:%.*]] = call i64 @llvm.smax.i64(i64 [[RDX_MINMAX]], i64 [[TMP26]]) 1403*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX_MINMAX5:%.*]] = call i64 @llvm.smax.i64(i64 [[RDX_MINMAX4]], i64 [[TMP27]]) 1404*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX_SELECT_CMP:%.*]] = icmp ne i64 [[RDX_MINMAX5]], -9223372036854775808 1405*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX_SELECT:%.*]] = select i1 [[RDX_SELECT_CMP]], i64 [[RDX_MINMAX5]], i64 [[RDX_START]] 1406*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] 1407*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] 1408*b3cba9beSMel Chen; CHECK-VF1IC4: [[SCALAR_PH]]: 1409*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] 1410*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ], [ [[RDX_START]], %[[ENTRY]] ] 1411*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br label %[[FOR_BODY:.*]] 1412*b3cba9beSMel Chen; CHECK-VF1IC4: [[FOR_BODY]]: 1413*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[IV:%.*]] = phi i64 [ [[INC:%.*]], %[[FOR_BODY]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ] 1414*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX:%.*]] = phi i64 [ [[COND:%.*]], %[[FOR_BODY]] ], [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ] 1415*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[IV]] 1416*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP29:%.*]] = load float, ptr [[ARRAYIDX]], align 4 1417*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[IV]] 1418*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP30:%.*]] = load float, ptr [[ARRAYIDX1]], align 4 1419*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[CMP2:%.*]] = fcmp ogt float [[TMP29]], [[TMP30]] 1420*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[COND]] = select i1 [[CMP2]], i64 [[IV]], i64 [[RDX]] 1421*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[INC]] = add nuw nsw i64 [[IV]], 1 1422*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[N]] 1423*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP15:![0-9]+]] 1424*b3cba9beSMel Chen; CHECK-VF1IC4: [[EXIT]]: 1425*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[COND_LCSSA:%.*]] = phi i64 [ [[COND]], %[[FOR_BODY]] ], [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ] 1426*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: ret i64 [[COND_LCSSA]] 14274ddc1745SMel Chen; 14284ddc1745SMel Chenentry: 14294ddc1745SMel Chen br label %for.body 14304ddc1745SMel Chen 14314ddc1745SMel Chenfor.body: ; preds = %entry, %for.body 14324ddc1745SMel Chen %iv = phi i64 [ %inc, %for.body ], [ 0, %entry ] 14334ddc1745SMel Chen %rdx = phi i64 [ %cond, %for.body ], [ %rdx.start, %entry ] 14344ddc1745SMel Chen %arrayidx = getelementptr inbounds float, ptr %a, i64 %iv 14354ddc1745SMel Chen %0 = load float, ptr %arrayidx, align 4 14364ddc1745SMel Chen %arrayidx1 = getelementptr inbounds float, ptr %b, i64 %iv 14374ddc1745SMel Chen %1 = load float, ptr %arrayidx1, align 4 14384ddc1745SMel Chen %cmp2 = fcmp ogt float %0, %1 14394ddc1745SMel Chen %cond = select i1 %cmp2, i64 %iv, i64 %rdx 14404ddc1745SMel Chen %inc = add nuw nsw i64 %iv, 1 14414ddc1745SMel Chen %exitcond.not = icmp eq i64 %inc, %n 14424ddc1745SMel Chen br i1 %exitcond.not, label %exit, label %for.body 14434ddc1745SMel Chen 14444ddc1745SMel Chenexit: ; preds = %for.body 14454ddc1745SMel Chen ret i64 %cond 14464ddc1745SMel Chen} 14474ddc1745SMel Chen 1448707686b0SMel Chendefine i64 @select_icmp_min_valid_iv_start(ptr %a, ptr %b, i64 %rdx.start, i64 %n) { 1449*b3cba9beSMel Chen; CHECK-VF4IC1-LABEL: define i64 @select_icmp_min_valid_iv_start( 1450*b3cba9beSMel Chen; CHECK-VF4IC1-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[RDX_START:%.*]], i64 [[N:%.*]]) { 1451*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[ENTRY:.*]]: 1452*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4 1453*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] 1454*b3cba9beSMel Chen; CHECK-VF4IC1: [[VECTOR_PH]]: 1455*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 4 1456*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]] 1457*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[IND_END:%.*]] = add i64 -9223372036854775807, [[N_VEC]] 1458*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br label %[[VECTOR_BODY:.*]] 1459*b3cba9beSMel Chen; CHECK-VF4IC1: [[VECTOR_BODY]]: 1460*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] 1461*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 -9223372036854775807, i64 -9223372036854775806, i64 -9223372036854775805, i64 -9223372036854775804>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] 1462*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[VEC_PHI:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP6:%.*]], %[[VECTOR_BODY]] ] 1463*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 1464*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP0]] 1465*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0 1466*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP2]], align 8 1467*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[TMP0]] 1468*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP3]], i32 0 1469*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[WIDE_LOAD2:%.*]] = load <4 x i64>, ptr [[TMP4]], align 8 1470*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP5:%.*]] = icmp sgt <4 x i64> [[WIDE_LOAD]], [[WIDE_LOAD2]] 1471*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP6]] = select <4 x i1> [[TMP5]], <4 x i64> [[VEC_IND]], <4 x i64> [[VEC_PHI]] 1472*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 1473*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[VEC_IND_NEXT]] = add <4 x i64> [[VEC_IND]], splat (i64 4) 1474*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 1475*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP16:![0-9]+]] 1476*b3cba9beSMel Chen; CHECK-VF4IC1: [[MIDDLE_BLOCK]]: 1477*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP8:%.*]] = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> [[TMP6]]) 1478*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[RDX_SELECT_CMP:%.*]] = icmp ne i64 [[TMP8]], -9223372036854775808 1479*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[RDX_SELECT:%.*]] = select i1 [[RDX_SELECT_CMP]], i64 [[TMP8]], i64 [[RDX_START]] 1480*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] 1481*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] 1482*b3cba9beSMel Chen; CHECK-VF4IC1: [[SCALAR_PH]]: 1483*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[IND_END]], %[[MIDDLE_BLOCK]] ], [ -9223372036854775807, %[[ENTRY]] ] 1484*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[BC_RESUME_VAL1:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] 1485*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ], [ [[RDX_START]], %[[ENTRY]] ] 1486*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br label %[[FOR_BODY:.*]] 1487*b3cba9beSMel Chen; CHECK-VF4IC1: [[FOR_BODY]]: 1488*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[IV_J:%.*]] = phi i64 [ [[INC3:%.*]], %[[FOR_BODY]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ] 1489*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[IV_I:%.*]] = phi i64 [ [[INC:%.*]], %[[FOR_BODY]] ], [ [[BC_RESUME_VAL1]], %[[SCALAR_PH]] ] 1490*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[RDX:%.*]] = phi i64 [ [[COND:%.*]], %[[FOR_BODY]] ], [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ] 1491*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV_I]] 1492*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP9:%.*]] = load i64, ptr [[ARRAYIDX]], align 8 1493*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[IV_I]] 1494*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP10:%.*]] = load i64, ptr [[ARRAYIDX1]], align 8 1495*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[CMP2:%.*]] = icmp sgt i64 [[TMP9]], [[TMP10]] 1496*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[COND]] = select i1 [[CMP2]], i64 [[IV_J]], i64 [[RDX]] 1497*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[INC]] = add nuw nsw i64 [[IV_I]], 1 1498*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[INC3]] = add nsw i64 [[IV_J]], 1 1499*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[N]] 1500*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP17:![0-9]+]] 1501*b3cba9beSMel Chen; CHECK-VF4IC1: [[EXIT]]: 1502*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[COND_LCSSA:%.*]] = phi i64 [ [[COND]], %[[FOR_BODY]] ], [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ] 1503*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: ret i64 [[COND_LCSSA]] 1504*b3cba9beSMel Chen; 1505*b3cba9beSMel Chen; CHECK-VF4IC4-LABEL: define i64 @select_icmp_min_valid_iv_start( 1506*b3cba9beSMel Chen; CHECK-VF4IC4-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[RDX_START:%.*]], i64 [[N:%.*]]) { 1507*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[ENTRY:.*]]: 1508*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 16 1509*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] 1510*b3cba9beSMel Chen; CHECK-VF4IC4: [[VECTOR_PH]]: 1511*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 16 1512*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]] 1513*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[IND_END:%.*]] = add i64 -9223372036854775807, [[N_VEC]] 1514*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br label %[[VECTOR_BODY:.*]] 1515*b3cba9beSMel Chen; CHECK-VF4IC4: [[VECTOR_BODY]]: 1516*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] 1517*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 -9223372036854775807, i64 -9223372036854775806, i64 -9223372036854775805, i64 -9223372036854775804>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] 1518*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[VEC_PHI:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP15:%.*]], %[[VECTOR_BODY]] ] 1519*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP16:%.*]], %[[VECTOR_BODY]] ] 1520*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP17:%.*]], %[[VECTOR_BODY]] ] 1521*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[VEC_PHI4:%.*]] = phi <4 x i64> [ splat (i64 -9223372036854775808), %[[VECTOR_PH]] ], [ [[TMP18:%.*]], %[[VECTOR_BODY]] ] 1522*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[STEP_ADD:%.*]] = add <4 x i64> [[VEC_IND]], splat (i64 4) 1523*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[STEP_ADD_2:%.*]] = add <4 x i64> [[STEP_ADD]], splat (i64 4) 1524*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[STEP_ADD_3:%.*]] = add <4 x i64> [[STEP_ADD_2]], splat (i64 4) 1525*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 1526*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP0]] 1527*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 0 1528*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 4 1529*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 8 1530*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i32 12 1531*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP2]], align 8 1532*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x i64>, ptr [[TMP3]], align 8 1533*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x i64>, ptr [[TMP4]], align 8 1534*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[WIDE_LOAD7:%.*]] = load <4 x i64>, ptr [[TMP5]], align 8 1535*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[TMP0]] 1536*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[TMP6]], i32 0 1537*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP8:%.*]] = getelementptr inbounds i64, ptr [[TMP6]], i32 4 1538*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP9:%.*]] = getelementptr inbounds i64, ptr [[TMP6]], i32 8 1539*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP10:%.*]] = getelementptr inbounds i64, ptr [[TMP6]], i32 12 1540*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[WIDE_LOAD8:%.*]] = load <4 x i64>, ptr [[TMP7]], align 8 1541*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[WIDE_LOAD9:%.*]] = load <4 x i64>, ptr [[TMP8]], align 8 1542*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[WIDE_LOAD10:%.*]] = load <4 x i64>, ptr [[TMP9]], align 8 1543*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[WIDE_LOAD11:%.*]] = load <4 x i64>, ptr [[TMP10]], align 8 1544*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP11:%.*]] = icmp sgt <4 x i64> [[WIDE_LOAD]], [[WIDE_LOAD8]] 1545*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP12:%.*]] = icmp sgt <4 x i64> [[WIDE_LOAD5]], [[WIDE_LOAD9]] 1546*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP13:%.*]] = icmp sgt <4 x i64> [[WIDE_LOAD6]], [[WIDE_LOAD10]] 1547*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP14:%.*]] = icmp sgt <4 x i64> [[WIDE_LOAD7]], [[WIDE_LOAD11]] 1548*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP15]] = select <4 x i1> [[TMP11]], <4 x i64> [[VEC_IND]], <4 x i64> [[VEC_PHI]] 1549*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP16]] = select <4 x i1> [[TMP12]], <4 x i64> [[STEP_ADD]], <4 x i64> [[VEC_PHI2]] 1550*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP17]] = select <4 x i1> [[TMP13]], <4 x i64> [[STEP_ADD_2]], <4 x i64> [[VEC_PHI3]] 1551*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP18]] = select <4 x i1> [[TMP14]], <4 x i64> [[STEP_ADD_3]], <4 x i64> [[VEC_PHI4]] 1552*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 1553*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[VEC_IND_NEXT]] = add <4 x i64> [[STEP_ADD_3]], splat (i64 4) 1554*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP19:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 1555*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br i1 [[TMP19]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP16:![0-9]+]] 1556*b3cba9beSMel Chen; CHECK-VF4IC4: [[MIDDLE_BLOCK]]: 1557*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX_MINMAX:%.*]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[TMP15]], <4 x i64> [[TMP16]]) 1558*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX_MINMAX12:%.*]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[RDX_MINMAX]], <4 x i64> [[TMP17]]) 1559*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX_MINMAX13:%.*]] = call <4 x i64> @llvm.smax.v4i64(<4 x i64> [[RDX_MINMAX12]], <4 x i64> [[TMP18]]) 1560*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP20:%.*]] = call i64 @llvm.vector.reduce.smax.v4i64(<4 x i64> [[RDX_MINMAX13]]) 1561*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX_SELECT_CMP:%.*]] = icmp ne i64 [[TMP20]], -9223372036854775808 1562*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX_SELECT:%.*]] = select i1 [[RDX_SELECT_CMP]], i64 [[TMP20]], i64 [[RDX_START]] 1563*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] 1564*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] 1565*b3cba9beSMel Chen; CHECK-VF4IC4: [[SCALAR_PH]]: 1566*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[IND_END]], %[[MIDDLE_BLOCK]] ], [ -9223372036854775807, %[[ENTRY]] ] 1567*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[BC_RESUME_VAL1:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] 1568*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ], [ [[RDX_START]], %[[ENTRY]] ] 1569*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br label %[[FOR_BODY:.*]] 1570*b3cba9beSMel Chen; CHECK-VF4IC4: [[FOR_BODY]]: 1571*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[IV_J:%.*]] = phi i64 [ [[INC3:%.*]], %[[FOR_BODY]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ] 1572*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[IV_I:%.*]] = phi i64 [ [[INC:%.*]], %[[FOR_BODY]] ], [ [[BC_RESUME_VAL1]], %[[SCALAR_PH]] ] 1573*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX:%.*]] = phi i64 [ [[COND:%.*]], %[[FOR_BODY]] ], [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ] 1574*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV_I]] 1575*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP21:%.*]] = load i64, ptr [[ARRAYIDX]], align 8 1576*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[IV_I]] 1577*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP22:%.*]] = load i64, ptr [[ARRAYIDX1]], align 8 1578*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[CMP2:%.*]] = icmp sgt i64 [[TMP21]], [[TMP22]] 1579*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[COND]] = select i1 [[CMP2]], i64 [[IV_J]], i64 [[RDX]] 1580*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[INC]] = add nuw nsw i64 [[IV_I]], 1 1581*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[INC3]] = add nsw i64 [[IV_J]], 1 1582*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[N]] 1583*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP17:![0-9]+]] 1584*b3cba9beSMel Chen; CHECK-VF4IC4: [[EXIT]]: 1585*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[COND_LCSSA:%.*]] = phi i64 [ [[COND]], %[[FOR_BODY]] ], [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ] 1586*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: ret i64 [[COND_LCSSA]] 1587*b3cba9beSMel Chen; 1588*b3cba9beSMel Chen; CHECK-VF1IC4-LABEL: define i64 @select_icmp_min_valid_iv_start( 1589*b3cba9beSMel Chen; CHECK-VF1IC4-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[RDX_START:%.*]], i64 [[N:%.*]]) { 1590*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[ENTRY:.*]]: 1591*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4 1592*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] 1593*b3cba9beSMel Chen; CHECK-VF1IC4: [[VECTOR_PH]]: 1594*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], 4 1595*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]] 1596*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[IND_END:%.*]] = add i64 -9223372036854775807, [[N_VEC]] 1597*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br label %[[VECTOR_BODY:.*]] 1598*b3cba9beSMel Chen; CHECK-VF1IC4: [[VECTOR_BODY]]: 1599*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] 1600*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[VEC_PHI:%.*]] = phi i64 [ -9223372036854775808, %[[VECTOR_PH]] ], [ [[TMP28:%.*]], %[[VECTOR_BODY]] ] 1601*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[VEC_PHI2:%.*]] = phi i64 [ -9223372036854775808, %[[VECTOR_PH]] ], [ [[TMP29:%.*]], %[[VECTOR_BODY]] ] 1602*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[VEC_PHI3:%.*]] = phi i64 [ -9223372036854775808, %[[VECTOR_PH]] ], [ [[TMP30:%.*]], %[[VECTOR_BODY]] ] 1603*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[VEC_PHI4:%.*]] = phi i64 [ -9223372036854775808, %[[VECTOR_PH]] ], [ [[TMP31:%.*]], %[[VECTOR_BODY]] ] 1604*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[OFFSET_IDX:%.*]] = add i64 -9223372036854775807, [[INDEX]] 1605*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP0:%.*]] = add i64 [[OFFSET_IDX]], 0 1606*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP1:%.*]] = add i64 [[OFFSET_IDX]], 1 1607*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP2:%.*]] = add i64 [[OFFSET_IDX]], 2 1608*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP3:%.*]] = add i64 [[OFFSET_IDX]], 3 1609*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP4:%.*]] = add i64 [[INDEX]], 0 1610*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP5:%.*]] = add i64 [[INDEX]], 1 1611*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP6:%.*]] = add i64 [[INDEX]], 2 1612*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP7:%.*]] = add i64 [[INDEX]], 3 1613*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP8:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP4]] 1614*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP9:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP5]] 1615*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP10:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP6]] 1616*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP11:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP7]] 1617*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP12:%.*]] = load i64, ptr [[TMP8]], align 8 1618*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP13:%.*]] = load i64, ptr [[TMP9]], align 8 1619*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP14:%.*]] = load i64, ptr [[TMP10]], align 8 1620*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP15:%.*]] = load i64, ptr [[TMP11]], align 8 1621*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP16:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[TMP4]] 1622*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP17:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[TMP5]] 1623*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP18:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[TMP6]] 1624*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP19:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[TMP7]] 1625*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP20:%.*]] = load i64, ptr [[TMP16]], align 8 1626*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP21:%.*]] = load i64, ptr [[TMP17]], align 8 1627*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP22:%.*]] = load i64, ptr [[TMP18]], align 8 1628*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP23:%.*]] = load i64, ptr [[TMP19]], align 8 1629*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP24:%.*]] = icmp sgt i64 [[TMP12]], [[TMP20]] 1630*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP25:%.*]] = icmp sgt i64 [[TMP13]], [[TMP21]] 1631*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP26:%.*]] = icmp sgt i64 [[TMP14]], [[TMP22]] 1632*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP27:%.*]] = icmp sgt i64 [[TMP15]], [[TMP23]] 1633*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP28]] = select i1 [[TMP24]], i64 [[TMP0]], i64 [[VEC_PHI]] 1634*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP29]] = select i1 [[TMP25]], i64 [[TMP1]], i64 [[VEC_PHI2]] 1635*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP30]] = select i1 [[TMP26]], i64 [[TMP2]], i64 [[VEC_PHI3]] 1636*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP31]] = select i1 [[TMP27]], i64 [[TMP3]], i64 [[VEC_PHI4]] 1637*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 1638*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP32:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] 1639*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br i1 [[TMP32]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP16:![0-9]+]] 1640*b3cba9beSMel Chen; CHECK-VF1IC4: [[MIDDLE_BLOCK]]: 1641*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX_MINMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[TMP28]], i64 [[TMP29]]) 1642*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX_MINMAX5:%.*]] = call i64 @llvm.smax.i64(i64 [[RDX_MINMAX]], i64 [[TMP30]]) 1643*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX_MINMAX6:%.*]] = call i64 @llvm.smax.i64(i64 [[RDX_MINMAX5]], i64 [[TMP31]]) 1644*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX_SELECT_CMP:%.*]] = icmp ne i64 [[RDX_MINMAX6]], -9223372036854775808 1645*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX_SELECT:%.*]] = select i1 [[RDX_SELECT_CMP]], i64 [[RDX_MINMAX6]], i64 [[RDX_START]] 1646*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] 1647*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] 1648*b3cba9beSMel Chen; CHECK-VF1IC4: [[SCALAR_PH]]: 1649*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[IND_END]], %[[MIDDLE_BLOCK]] ], [ -9223372036854775807, %[[ENTRY]] ] 1650*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[BC_RESUME_VAL1:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] 1651*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i64 [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ], [ [[RDX_START]], %[[ENTRY]] ] 1652*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br label %[[FOR_BODY:.*]] 1653*b3cba9beSMel Chen; CHECK-VF1IC4: [[FOR_BODY]]: 1654*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[IV_J:%.*]] = phi i64 [ [[INC3:%.*]], %[[FOR_BODY]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ] 1655*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[IV_I:%.*]] = phi i64 [ [[INC:%.*]], %[[FOR_BODY]] ], [ [[BC_RESUME_VAL1]], %[[SCALAR_PH]] ] 1656*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX:%.*]] = phi i64 [ [[COND:%.*]], %[[FOR_BODY]] ], [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ] 1657*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV_I]] 1658*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP33:%.*]] = load i64, ptr [[ARRAYIDX]], align 8 1659*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[IV_I]] 1660*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP34:%.*]] = load i64, ptr [[ARRAYIDX1]], align 8 1661*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[CMP2:%.*]] = icmp sgt i64 [[TMP33]], [[TMP34]] 1662*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[COND]] = select i1 [[CMP2]], i64 [[IV_J]], i64 [[RDX]] 1663*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[INC]] = add nuw nsw i64 [[IV_I]], 1 1664*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[INC3]] = add nsw i64 [[IV_J]], 1 1665*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[N]] 1666*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP17:![0-9]+]] 1667*b3cba9beSMel Chen; CHECK-VF1IC4: [[EXIT]]: 1668*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[COND_LCSSA:%.*]] = phi i64 [ [[COND]], %[[FOR_BODY]] ], [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ] 1669*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: ret i64 [[COND_LCSSA]] 16704ddc1745SMel Chen; 16714ddc1745SMel Chenentry: 16724ddc1745SMel Chen br label %for.body 16734ddc1745SMel Chen 16744ddc1745SMel Chenfor.body: ; preds = %entry, %for.body 16754ddc1745SMel Chen %iv.j = phi i64 [ %inc3, %for.body ], [ -9223372036854775807, %entry] 16764ddc1745SMel Chen %iv.i = phi i64 [ %inc, %for.body ], [ 0, %entry ] 16774ddc1745SMel Chen %rdx = phi i64 [ %cond, %for.body ], [ %rdx.start, %entry ] 16784ddc1745SMel Chen %arrayidx = getelementptr inbounds i64, ptr %a, i64 %iv.i 16794ddc1745SMel Chen %0 = load i64, ptr %arrayidx, align 8 16804ddc1745SMel Chen %arrayidx1 = getelementptr inbounds i64, ptr %b, i64 %iv.i 16814ddc1745SMel Chen %1 = load i64, ptr %arrayidx1, align 8 16824ddc1745SMel Chen %cmp2 = icmp sgt i64 %0, %1 16834ddc1745SMel Chen %cond = select i1 %cmp2, i64 %iv.j, i64 %rdx 16844ddc1745SMel Chen %inc = add nuw nsw i64 %iv.i, 1 16854ddc1745SMel Chen %inc3 = add nsw i64 %iv.j, 1 16864ddc1745SMel Chen %exitcond.not = icmp eq i64 %inc, %n 16874ddc1745SMel Chen br i1 %exitcond.not, label %exit, label %for.body 16884ddc1745SMel Chen 16894ddc1745SMel Chenexit: ; preds = %for.body 16904ddc1745SMel Chen ret i64 %cond 16914ddc1745SMel Chen} 16924ddc1745SMel Chen 16934ddc1745SMel Chen; Negative tests 16944ddc1745SMel Chen 1695707686b0SMel Chendefine float @not_vectorized_select_float_induction_icmp(ptr %a, ptr %b, float %rdx.start, i64 %n) { 1696*b3cba9beSMel Chen; CHECK-VF4IC1-LABEL: define float @not_vectorized_select_float_induction_icmp( 1697*b3cba9beSMel Chen; CHECK-VF4IC1-SAME: ptr [[A:%.*]], ptr [[B:%.*]], float [[RDX_START:%.*]], i64 [[N:%.*]]) { 1698*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[ENTRY:.*]]: 1699*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br label %[[FOR_BODY:.*]] 1700*b3cba9beSMel Chen; CHECK-VF4IC1: [[FOR_BODY]]: 1701*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[IV:%.*]] = phi i64 [ [[INC:%.*]], %[[FOR_BODY]] ], [ 0, %[[ENTRY]] ] 1702*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[FIV:%.*]] = phi float [ [[CONV3:%.*]], %[[FOR_BODY]] ], [ 0.000000e+00, %[[ENTRY]] ] 1703*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[RDX:%.*]] = phi float [ [[COND:%.*]], %[[FOR_BODY]] ], [ [[RDX_START]], %[[ENTRY]] ] 1704*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]] 1705*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP0:%.*]] = load i64, ptr [[ARRAYIDX]], align 8 1706*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[IV]] 1707*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP1:%.*]] = load i64, ptr [[ARRAYIDX1]], align 8 1708*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[CMP2:%.*]] = icmp sgt i64 [[TMP0]], [[TMP1]] 1709*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[COND]] = select i1 [[CMP2]], float [[FIV]], float [[RDX]] 1710*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[CONV3]] = fadd float [[FIV]], 1.000000e+00 1711*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[INC]] = add nuw nsw i64 [[IV]], 1 1712*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[N]] 1713*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT:.*]], label %[[FOR_BODY]] 1714*b3cba9beSMel Chen; CHECK-VF4IC1: [[EXIT]]: 1715*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[COND_LCSSA:%.*]] = phi float [ [[COND]], %[[FOR_BODY]] ] 1716*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: ret float [[COND_LCSSA]] 1717*b3cba9beSMel Chen; 1718*b3cba9beSMel Chen; CHECK-VF4IC4-LABEL: define float @not_vectorized_select_float_induction_icmp( 1719*b3cba9beSMel Chen; CHECK-VF4IC4-SAME: ptr [[A:%.*]], ptr [[B:%.*]], float [[RDX_START:%.*]], i64 [[N:%.*]]) { 1720*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[ENTRY:.*]]: 1721*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br label %[[FOR_BODY:.*]] 1722*b3cba9beSMel Chen; CHECK-VF4IC4: [[FOR_BODY]]: 1723*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[IV:%.*]] = phi i64 [ [[INC:%.*]], %[[FOR_BODY]] ], [ 0, %[[ENTRY]] ] 1724*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[FIV:%.*]] = phi float [ [[CONV3:%.*]], %[[FOR_BODY]] ], [ 0.000000e+00, %[[ENTRY]] ] 1725*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX:%.*]] = phi float [ [[COND:%.*]], %[[FOR_BODY]] ], [ [[RDX_START]], %[[ENTRY]] ] 1726*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]] 1727*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP0:%.*]] = load i64, ptr [[ARRAYIDX]], align 8 1728*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[IV]] 1729*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP1:%.*]] = load i64, ptr [[ARRAYIDX1]], align 8 1730*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[CMP2:%.*]] = icmp sgt i64 [[TMP0]], [[TMP1]] 1731*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[COND]] = select i1 [[CMP2]], float [[FIV]], float [[RDX]] 1732*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[CONV3]] = fadd float [[FIV]], 1.000000e+00 1733*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[INC]] = add nuw nsw i64 [[IV]], 1 1734*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[N]] 1735*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT:.*]], label %[[FOR_BODY]] 1736*b3cba9beSMel Chen; CHECK-VF4IC4: [[EXIT]]: 1737*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[COND_LCSSA:%.*]] = phi float [ [[COND]], %[[FOR_BODY]] ] 1738*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: ret float [[COND_LCSSA]] 1739*b3cba9beSMel Chen; 1740*b3cba9beSMel Chen; CHECK-VF1IC4-LABEL: define float @not_vectorized_select_float_induction_icmp( 1741*b3cba9beSMel Chen; CHECK-VF1IC4-SAME: ptr [[A:%.*]], ptr [[B:%.*]], float [[RDX_START:%.*]], i64 [[N:%.*]]) { 1742*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[ENTRY:.*]]: 1743*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br label %[[FOR_BODY:.*]] 1744*b3cba9beSMel Chen; CHECK-VF1IC4: [[FOR_BODY]]: 1745*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[IV:%.*]] = phi i64 [ [[INC:%.*]], %[[FOR_BODY]] ], [ 0, %[[ENTRY]] ] 1746*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[FIV:%.*]] = phi float [ [[CONV3:%.*]], %[[FOR_BODY]] ], [ 0.000000e+00, %[[ENTRY]] ] 1747*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX:%.*]] = phi float [ [[COND:%.*]], %[[FOR_BODY]] ], [ [[RDX_START]], %[[ENTRY]] ] 1748*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]] 1749*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP0:%.*]] = load i64, ptr [[ARRAYIDX]], align 8 1750*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[IV]] 1751*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP1:%.*]] = load i64, ptr [[ARRAYIDX1]], align 8 1752*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[CMP2:%.*]] = icmp sgt i64 [[TMP0]], [[TMP1]] 1753*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[COND]] = select i1 [[CMP2]], float [[FIV]], float [[RDX]] 1754*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[CONV3]] = fadd float [[FIV]], 1.000000e+00 1755*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[INC]] = add nuw nsw i64 [[IV]], 1 1756*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[N]] 1757*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT:.*]], label %[[FOR_BODY]] 1758*b3cba9beSMel Chen; CHECK-VF1IC4: [[EXIT]]: 1759*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[COND_LCSSA:%.*]] = phi float [ [[COND]], %[[FOR_BODY]] ] 1760*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: ret float [[COND_LCSSA]] 17614ddc1745SMel Chen; 17624ddc1745SMel Chenentry: 17634ddc1745SMel Chen br label %for.body 17644ddc1745SMel Chen 17654ddc1745SMel Chenfor.body: ; preds = %entry, %for.body 17664ddc1745SMel Chen %iv = phi i64 [ %inc, %for.body ], [ 0, %entry ] 17674ddc1745SMel Chen %fiv = phi float [ %conv3, %for.body ], [ 0.000000e+00, %entry ] 17684ddc1745SMel Chen %rdx = phi float [ %cond, %for.body ], [ %rdx.start, %entry ] 17694ddc1745SMel Chen %arrayidx = getelementptr inbounds i64, ptr %a, i64 %iv 17704ddc1745SMel Chen %0 = load i64, ptr %arrayidx, align 8 17714ddc1745SMel Chen %arrayidx1 = getelementptr inbounds i64, ptr %b, i64 %iv 17724ddc1745SMel Chen %1 = load i64, ptr %arrayidx1, align 8 17734ddc1745SMel Chen %cmp2 = icmp sgt i64 %0, %1 17744ddc1745SMel Chen %cond = select i1 %cmp2, float %fiv, float %rdx 17754ddc1745SMel Chen %conv3 = fadd float %fiv, 1.000000e+00 17764ddc1745SMel Chen %inc = add nuw nsw i64 %iv, 1 17774ddc1745SMel Chen %exitcond.not = icmp eq i64 %inc, %n 17784ddc1745SMel Chen br i1 %exitcond.not, label %exit, label %for.body 17794ddc1745SMel Chen 17804ddc1745SMel Chenexit: ; preds = %for.body 17814ddc1745SMel Chen ret float %cond 17824ddc1745SMel Chen} 17834ddc1745SMel Chen 1784707686b0SMel Chendefine i64 @not_vectorized_select_decreasing_induction_icmp_const_start(ptr %a) { 1785*b3cba9beSMel Chen; CHECK-VF4IC1-LABEL: define i64 @not_vectorized_select_decreasing_induction_icmp_const_start( 1786*b3cba9beSMel Chen; CHECK-VF4IC1-SAME: ptr [[A:%.*]]) { 1787*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[ENTRY:.*]]: 1788*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br label %[[FOR_BODY:.*]] 1789*b3cba9beSMel Chen; CHECK-VF4IC1: [[FOR_BODY]]: 1790*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[IV:%.*]] = phi i64 [ 19999, %[[ENTRY]] ], [ [[DEC:%.*]], %[[FOR_BODY]] ] 1791*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[RDX:%.*]] = phi i64 [ 331, %[[ENTRY]] ], [ [[SPEC_SELECT:%.*]], %[[FOR_BODY]] ] 1792*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]] 1793*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP0:%.*]] = load i64, ptr [[ARRAYIDX]], align 8 1794*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP0]], 3 1795*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[SPEC_SELECT]] = select i1 [[CMP]], i64 [[IV]], i64 [[RDX]] 1796*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[DEC]] = add nsw i64 [[IV]], -1 1797*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[CMP_NOT:%.*]] = icmp eq i64 [[IV]], 0 1798*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br i1 [[CMP_NOT]], label %[[EXIT:.*]], label %[[FOR_BODY]] 1799*b3cba9beSMel Chen; CHECK-VF4IC1: [[EXIT]]: 1800*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[SPEC_SELECT_LCSSA:%.*]] = phi i64 [ [[SPEC_SELECT]], %[[FOR_BODY]] ] 1801*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: ret i64 [[SPEC_SELECT_LCSSA]] 1802*b3cba9beSMel Chen; 1803*b3cba9beSMel Chen; CHECK-VF4IC4-LABEL: define i64 @not_vectorized_select_decreasing_induction_icmp_const_start( 1804*b3cba9beSMel Chen; CHECK-VF4IC4-SAME: ptr [[A:%.*]]) { 1805*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[ENTRY:.*]]: 1806*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br label %[[FOR_BODY:.*]] 1807*b3cba9beSMel Chen; CHECK-VF4IC4: [[FOR_BODY]]: 1808*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[IV:%.*]] = phi i64 [ 19999, %[[ENTRY]] ], [ [[DEC:%.*]], %[[FOR_BODY]] ] 1809*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX:%.*]] = phi i64 [ 331, %[[ENTRY]] ], [ [[SPEC_SELECT:%.*]], %[[FOR_BODY]] ] 1810*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]] 1811*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP0:%.*]] = load i64, ptr [[ARRAYIDX]], align 8 1812*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP0]], 3 1813*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[SPEC_SELECT]] = select i1 [[CMP]], i64 [[IV]], i64 [[RDX]] 1814*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[DEC]] = add nsw i64 [[IV]], -1 1815*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[CMP_NOT:%.*]] = icmp eq i64 [[IV]], 0 1816*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br i1 [[CMP_NOT]], label %[[EXIT:.*]], label %[[FOR_BODY]] 1817*b3cba9beSMel Chen; CHECK-VF4IC4: [[EXIT]]: 1818*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[SPEC_SELECT_LCSSA:%.*]] = phi i64 [ [[SPEC_SELECT]], %[[FOR_BODY]] ] 1819*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: ret i64 [[SPEC_SELECT_LCSSA]] 1820*b3cba9beSMel Chen; 1821*b3cba9beSMel Chen; CHECK-VF1IC4-LABEL: define i64 @not_vectorized_select_decreasing_induction_icmp_const_start( 1822*b3cba9beSMel Chen; CHECK-VF1IC4-SAME: ptr [[A:%.*]]) { 1823*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[ENTRY:.*]]: 1824*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br label %[[FOR_BODY:.*]] 1825*b3cba9beSMel Chen; CHECK-VF1IC4: [[FOR_BODY]]: 1826*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[IV:%.*]] = phi i64 [ 19999, %[[ENTRY]] ], [ [[DEC:%.*]], %[[FOR_BODY]] ] 1827*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX:%.*]] = phi i64 [ 331, %[[ENTRY]] ], [ [[SPEC_SELECT:%.*]], %[[FOR_BODY]] ] 1828*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]] 1829*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP0:%.*]] = load i64, ptr [[ARRAYIDX]], align 8 1830*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP0]], 3 1831*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[SPEC_SELECT]] = select i1 [[CMP]], i64 [[IV]], i64 [[RDX]] 1832*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[DEC]] = add nsw i64 [[IV]], -1 1833*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[CMP_NOT:%.*]] = icmp eq i64 [[IV]], 0 1834*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br i1 [[CMP_NOT]], label %[[EXIT:.*]], label %[[FOR_BODY]] 1835*b3cba9beSMel Chen; CHECK-VF1IC4: [[EXIT]]: 1836*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[SPEC_SELECT_LCSSA:%.*]] = phi i64 [ [[SPEC_SELECT]], %[[FOR_BODY]] ] 1837*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: ret i64 [[SPEC_SELECT_LCSSA]] 1838110ec186SRamkumar Ramachandra; 1839110ec186SRamkumar Ramachandraentry: 1840110ec186SRamkumar Ramachandra br label %for.body 1841110ec186SRamkumar Ramachandra 1842110ec186SRamkumar Ramachandrafor.body: ; preds = %entry, %for.body 1843110ec186SRamkumar Ramachandra %iv = phi i64 [ 19999, %entry ], [ %dec, %for.body ] 1844110ec186SRamkumar Ramachandra %rdx = phi i64 [ 331, %entry ], [ %spec.select, %for.body ] 1845110ec186SRamkumar Ramachandra %arrayidx = getelementptr inbounds i64, ptr %a, i64 %iv 1846110ec186SRamkumar Ramachandra %0 = load i64, ptr %arrayidx, align 8 1847110ec186SRamkumar Ramachandra %cmp = icmp sgt i64 %0, 3 1848110ec186SRamkumar Ramachandra %spec.select = select i1 %cmp, i64 %iv, i64 %rdx 1849110ec186SRamkumar Ramachandra %dec = add nsw i64 %iv, -1 1850110ec186SRamkumar Ramachandra %cmp.not = icmp eq i64 %iv, 0 1851110ec186SRamkumar Ramachandra br i1 %cmp.not, label %exit, label %for.body 1852110ec186SRamkumar Ramachandra 1853110ec186SRamkumar Ramachandraexit: ; preds = %for.body 1854110ec186SRamkumar Ramachandra ret i64 %spec.select 1855110ec186SRamkumar Ramachandra} 1856110ec186SRamkumar Ramachandra 1857707686b0SMel Chendefine i64 @not_vectorized_select_decreasing_induction_icmp_non_const_start(ptr %a, ptr %b, i64 %rdx.start, i64 %n) { 1858*b3cba9beSMel Chen; CHECK-VF4IC1-LABEL: define i64 @not_vectorized_select_decreasing_induction_icmp_non_const_start( 1859*b3cba9beSMel Chen; CHECK-VF4IC1-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[RDX_START:%.*]], i64 [[N:%.*]]) { 1860*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[ENTRY:.*]]: 1861*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br label %[[FOR_BODY:.*]] 1862*b3cba9beSMel Chen; CHECK-VF4IC1: [[FOR_BODY]]: 1863*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[I_0_IN10:%.*]] = phi i64 [ [[IV:%.*]], %[[FOR_BODY]] ], [ [[N]], %[[ENTRY]] ] 1864*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[RDX:%.*]] = phi i64 [ [[COND:%.*]], %[[FOR_BODY]] ], [ [[RDX_START]], %[[ENTRY]] ] 1865*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[IV]] = add nsw i64 [[I_0_IN10]], -1 1866*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]] 1867*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP0:%.*]] = load i64, ptr [[ARRAYIDX]], align 8 1868*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[IV]] 1869*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP1:%.*]] = load i64, ptr [[ARRAYIDX1]], align 8 1870*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[CMP2:%.*]] = icmp sgt i64 [[TMP0]], [[TMP1]] 1871*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[COND]] = select i1 [[CMP2]], i64 [[IV]], i64 [[RDX]] 1872*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[CMP:%.*]] = icmp ugt i64 [[I_0_IN10]], 1 1873*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br i1 [[CMP]], label %[[FOR_BODY]], label %[[EXIT:.*]] 1874*b3cba9beSMel Chen; CHECK-VF4IC1: [[EXIT]]: 1875*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[COND_LCSSA:%.*]] = phi i64 [ [[COND]], %[[FOR_BODY]] ] 1876*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: ret i64 [[COND_LCSSA]] 1877*b3cba9beSMel Chen; 1878*b3cba9beSMel Chen; CHECK-VF4IC4-LABEL: define i64 @not_vectorized_select_decreasing_induction_icmp_non_const_start( 1879*b3cba9beSMel Chen; CHECK-VF4IC4-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[RDX_START:%.*]], i64 [[N:%.*]]) { 1880*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[ENTRY:.*]]: 1881*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br label %[[FOR_BODY:.*]] 1882*b3cba9beSMel Chen; CHECK-VF4IC4: [[FOR_BODY]]: 1883*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[I_0_IN10:%.*]] = phi i64 [ [[IV:%.*]], %[[FOR_BODY]] ], [ [[N]], %[[ENTRY]] ] 1884*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX:%.*]] = phi i64 [ [[COND:%.*]], %[[FOR_BODY]] ], [ [[RDX_START]], %[[ENTRY]] ] 1885*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[IV]] = add nsw i64 [[I_0_IN10]], -1 1886*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]] 1887*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP0:%.*]] = load i64, ptr [[ARRAYIDX]], align 8 1888*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[IV]] 1889*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP1:%.*]] = load i64, ptr [[ARRAYIDX1]], align 8 1890*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[CMP2:%.*]] = icmp sgt i64 [[TMP0]], [[TMP1]] 1891*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[COND]] = select i1 [[CMP2]], i64 [[IV]], i64 [[RDX]] 1892*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[CMP:%.*]] = icmp ugt i64 [[I_0_IN10]], 1 1893*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br i1 [[CMP]], label %[[FOR_BODY]], label %[[EXIT:.*]] 1894*b3cba9beSMel Chen; CHECK-VF4IC4: [[EXIT]]: 1895*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[COND_LCSSA:%.*]] = phi i64 [ [[COND]], %[[FOR_BODY]] ] 1896*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: ret i64 [[COND_LCSSA]] 1897*b3cba9beSMel Chen; 1898*b3cba9beSMel Chen; CHECK-VF1IC4-LABEL: define i64 @not_vectorized_select_decreasing_induction_icmp_non_const_start( 1899*b3cba9beSMel Chen; CHECK-VF1IC4-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[RDX_START:%.*]], i64 [[N:%.*]]) { 1900*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[ENTRY:.*]]: 1901*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br label %[[FOR_BODY:.*]] 1902*b3cba9beSMel Chen; CHECK-VF1IC4: [[FOR_BODY]]: 1903*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[I_0_IN10:%.*]] = phi i64 [ [[IV:%.*]], %[[FOR_BODY]] ], [ [[N]], %[[ENTRY]] ] 1904*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX:%.*]] = phi i64 [ [[COND:%.*]], %[[FOR_BODY]] ], [ [[RDX_START]], %[[ENTRY]] ] 1905*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[IV]] = add nsw i64 [[I_0_IN10]], -1 1906*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]] 1907*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP0:%.*]] = load i64, ptr [[ARRAYIDX]], align 8 1908*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[IV]] 1909*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP1:%.*]] = load i64, ptr [[ARRAYIDX1]], align 8 1910*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[CMP2:%.*]] = icmp sgt i64 [[TMP0]], [[TMP1]] 1911*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[COND]] = select i1 [[CMP2]], i64 [[IV]], i64 [[RDX]] 1912*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[CMP:%.*]] = icmp ugt i64 [[I_0_IN10]], 1 1913*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br i1 [[CMP]], label %[[FOR_BODY]], label %[[EXIT:.*]] 1914*b3cba9beSMel Chen; CHECK-VF1IC4: [[EXIT]]: 1915*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[COND_LCSSA:%.*]] = phi i64 [ [[COND]], %[[FOR_BODY]] ] 1916*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: ret i64 [[COND_LCSSA]] 19174ddc1745SMel Chen; 19184ddc1745SMel Chenentry: 19194ddc1745SMel Chen br label %for.body 19204ddc1745SMel Chen 19214ddc1745SMel Chenfor.body: ; preds = %entry, %for.body 19224ddc1745SMel Chen %i.0.in10 = phi i64 [ %iv, %for.body ], [ %n, %entry ] 19234ddc1745SMel Chen %rdx = phi i64 [ %cond, %for.body ], [ %rdx.start, %entry ] 19244ddc1745SMel Chen %iv = add nsw i64 %i.0.in10, -1 19254ddc1745SMel Chen %arrayidx = getelementptr inbounds i64, ptr %a, i64 %iv 19264ddc1745SMel Chen %0 = load i64, ptr %arrayidx, align 8 19274ddc1745SMel Chen %arrayidx1 = getelementptr inbounds i64, ptr %b, i64 %iv 19284ddc1745SMel Chen %1 = load i64, ptr %arrayidx1, align 8 19294ddc1745SMel Chen %cmp2 = icmp sgt i64 %0, %1 19304ddc1745SMel Chen %cond = select i1 %cmp2, i64 %iv, i64 %rdx 19314ddc1745SMel Chen %cmp = icmp ugt i64 %i.0.in10, 1 19324ddc1745SMel Chen br i1 %cmp, label %for.body, label %exit 19334ddc1745SMel Chen 19344ddc1745SMel Chenexit: ; preds = %for.body 19354ddc1745SMel Chen ret i64 %cond 19364ddc1745SMel Chen} 19374ddc1745SMel Chen 1938ad415e30SRamkumar Ramachandra; The sentinel value for increasing-IV vectorization is -LONG_MAX, and since 1939ad415e30SRamkumar Ramachandra; the IV hits this value, it is impossible to vectorize this case. 1940707686b0SMel Chendefine i64 @not_vectorized_select_icmp_iv_out_of_bound(ptr %a, ptr %b, i64 %rdx.start, i64 %n) { 1941*b3cba9beSMel Chen; CHECK-VF4IC1-LABEL: define i64 @not_vectorized_select_icmp_iv_out_of_bound( 1942*b3cba9beSMel Chen; CHECK-VF4IC1-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[RDX_START:%.*]], i64 [[N:%.*]]) { 1943*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[ENTRY:.*]]: 1944*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br label %[[FOR_BODY:.*]] 1945*b3cba9beSMel Chen; CHECK-VF4IC1: [[FOR_BODY]]: 1946*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[IV_J:%.*]] = phi i64 [ [[INC3:%.*]], %[[FOR_BODY]] ], [ -9223372036854775808, %[[ENTRY]] ] 1947*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[IV_I:%.*]] = phi i64 [ [[INC:%.*]], %[[FOR_BODY]] ], [ 0, %[[ENTRY]] ] 1948*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[RDX:%.*]] = phi i64 [ [[COND:%.*]], %[[FOR_BODY]] ], [ [[RDX_START]], %[[ENTRY]] ] 1949*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV_I]] 1950*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP0:%.*]] = load i64, ptr [[ARRAYIDX]], align 8 1951*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[IV_I]] 1952*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP1:%.*]] = load i64, ptr [[ARRAYIDX1]], align 8 1953*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[CMP2:%.*]] = icmp sgt i64 [[TMP0]], [[TMP1]] 1954*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[COND]] = select i1 [[CMP2]], i64 [[IV_J]], i64 [[RDX]] 1955*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[INC]] = add nuw nsw i64 [[IV_I]], 1 1956*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[INC3]] = add nsw i64 [[IV_J]], 1 1957*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[N]] 1958*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT:.*]], label %[[FOR_BODY]] 1959*b3cba9beSMel Chen; CHECK-VF4IC1: [[EXIT]]: 1960*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[COND_LCSSA:%.*]] = phi i64 [ [[COND]], %[[FOR_BODY]] ] 1961*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: ret i64 [[COND_LCSSA]] 1962*b3cba9beSMel Chen; 1963*b3cba9beSMel Chen; CHECK-VF4IC4-LABEL: define i64 @not_vectorized_select_icmp_iv_out_of_bound( 1964*b3cba9beSMel Chen; CHECK-VF4IC4-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[RDX_START:%.*]], i64 [[N:%.*]]) { 1965*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[ENTRY:.*]]: 1966*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br label %[[FOR_BODY:.*]] 1967*b3cba9beSMel Chen; CHECK-VF4IC4: [[FOR_BODY]]: 1968*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[IV_J:%.*]] = phi i64 [ [[INC3:%.*]], %[[FOR_BODY]] ], [ -9223372036854775808, %[[ENTRY]] ] 1969*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[IV_I:%.*]] = phi i64 [ [[INC:%.*]], %[[FOR_BODY]] ], [ 0, %[[ENTRY]] ] 1970*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX:%.*]] = phi i64 [ [[COND:%.*]], %[[FOR_BODY]] ], [ [[RDX_START]], %[[ENTRY]] ] 1971*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV_I]] 1972*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP0:%.*]] = load i64, ptr [[ARRAYIDX]], align 8 1973*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[IV_I]] 1974*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP1:%.*]] = load i64, ptr [[ARRAYIDX1]], align 8 1975*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[CMP2:%.*]] = icmp sgt i64 [[TMP0]], [[TMP1]] 1976*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[COND]] = select i1 [[CMP2]], i64 [[IV_J]], i64 [[RDX]] 1977*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[INC]] = add nuw nsw i64 [[IV_I]], 1 1978*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[INC3]] = add nsw i64 [[IV_J]], 1 1979*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[N]] 1980*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT:.*]], label %[[FOR_BODY]] 1981*b3cba9beSMel Chen; CHECK-VF4IC4: [[EXIT]]: 1982*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[COND_LCSSA:%.*]] = phi i64 [ [[COND]], %[[FOR_BODY]] ] 1983*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: ret i64 [[COND_LCSSA]] 1984*b3cba9beSMel Chen; 1985*b3cba9beSMel Chen; CHECK-VF1IC4-LABEL: define i64 @not_vectorized_select_icmp_iv_out_of_bound( 1986*b3cba9beSMel Chen; CHECK-VF1IC4-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[RDX_START:%.*]], i64 [[N:%.*]]) { 1987*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[ENTRY:.*]]: 1988*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br label %[[FOR_BODY:.*]] 1989*b3cba9beSMel Chen; CHECK-VF1IC4: [[FOR_BODY]]: 1990*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[IV_J:%.*]] = phi i64 [ [[INC3:%.*]], %[[FOR_BODY]] ], [ -9223372036854775808, %[[ENTRY]] ] 1991*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[IV_I:%.*]] = phi i64 [ [[INC:%.*]], %[[FOR_BODY]] ], [ 0, %[[ENTRY]] ] 1992*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX:%.*]] = phi i64 [ [[COND:%.*]], %[[FOR_BODY]] ], [ [[RDX_START]], %[[ENTRY]] ] 1993*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV_I]] 1994*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP0:%.*]] = load i64, ptr [[ARRAYIDX]], align 8 1995*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[IV_I]] 1996*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP1:%.*]] = load i64, ptr [[ARRAYIDX1]], align 8 1997*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[CMP2:%.*]] = icmp sgt i64 [[TMP0]], [[TMP1]] 1998*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[COND]] = select i1 [[CMP2]], i64 [[IV_J]], i64 [[RDX]] 1999*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[INC]] = add nuw nsw i64 [[IV_I]], 1 2000*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[INC3]] = add nsw i64 [[IV_J]], 1 2001*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[N]] 2002*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT:.*]], label %[[FOR_BODY]] 2003*b3cba9beSMel Chen; CHECK-VF1IC4: [[EXIT]]: 2004*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[COND_LCSSA:%.*]] = phi i64 [ [[COND]], %[[FOR_BODY]] ] 2005*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: ret i64 [[COND_LCSSA]] 20064ddc1745SMel Chen; 20074ddc1745SMel Chenentry: 20084ddc1745SMel Chen br label %for.body 20094ddc1745SMel Chen 20104ddc1745SMel Chenfor.body: ; preds = %entry, %for.body 20114ddc1745SMel Chen %iv.j = phi i64 [ %inc3, %for.body ], [ -9223372036854775808, %entry] 20124ddc1745SMel Chen %iv.i = phi i64 [ %inc, %for.body ], [ 0, %entry ] 20134ddc1745SMel Chen %rdx = phi i64 [ %cond, %for.body ], [ %rdx.start, %entry ] 20144ddc1745SMel Chen %arrayidx = getelementptr inbounds i64, ptr %a, i64 %iv.i 20154ddc1745SMel Chen %0 = load i64, ptr %arrayidx, align 8 20164ddc1745SMel Chen %arrayidx1 = getelementptr inbounds i64, ptr %b, i64 %iv.i 20174ddc1745SMel Chen %1 = load i64, ptr %arrayidx1, align 8 20184ddc1745SMel Chen %cmp2 = icmp sgt i64 %0, %1 20194ddc1745SMel Chen %cond = select i1 %cmp2, i64 %iv.j, i64 %rdx 20204ddc1745SMel Chen %inc = add nuw nsw i64 %iv.i, 1 20214ddc1745SMel Chen %inc3 = add nsw i64 %iv.j, 1 20224ddc1745SMel Chen %exitcond.not = icmp eq i64 %inc, %n 20234ddc1745SMel Chen br i1 %exitcond.not, label %exit, label %for.body 20244ddc1745SMel Chen 20254ddc1745SMel Chenexit: ; preds = %for.body 20264ddc1745SMel Chen ret i64 %cond 20274ddc1745SMel Chen} 20284ddc1745SMel Chen 2029ad415e30SRamkumar Ramachandra; The sentinel value for decreasing-IV vectorization is LONG_MAX, and since 2030ad415e30SRamkumar Ramachandra; the IV hits this value, it is impossible to vectorize this case. 2031707686b0SMel Chendefine i64 @not_vectorized_select_decreasing_induction_icmp_iv_out_of_bound(ptr %a) { 2032*b3cba9beSMel Chen; CHECK-VF4IC1-LABEL: define i64 @not_vectorized_select_decreasing_induction_icmp_iv_out_of_bound( 2033*b3cba9beSMel Chen; CHECK-VF4IC1-SAME: ptr [[A:%.*]]) { 2034*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[ENTRY:.*]]: 2035*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br label %[[FOR_BODY:.*]] 2036*b3cba9beSMel Chen; CHECK-VF4IC1: [[FOR_BODY]]: 2037*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[IV:%.*]] = phi i64 [ 9223372036854775807, %[[ENTRY]] ], [ [[DEC:%.*]], %[[FOR_BODY]] ] 2038*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[RDX:%.*]] = phi i64 [ 331, %[[ENTRY]] ], [ [[SPEC_SELECT:%.*]], %[[FOR_BODY]] ] 2039*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]] 2040*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP0:%.*]] = load i64, ptr [[ARRAYIDX]], align 8 2041*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[CMP1:%.*]] = icmp sgt i64 [[TMP0]], 3 2042*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[SPEC_SELECT]] = select i1 [[CMP1]], i64 [[IV]], i64 [[RDX]] 2043*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[DEC]] = add nsw i64 [[IV]], -1 2044*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[CMP_NOT:%.*]] = icmp eq i64 [[IV]], 0 2045*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br i1 [[CMP_NOT]], label %[[EXIT:.*]], label %[[FOR_BODY]] 2046*b3cba9beSMel Chen; CHECK-VF4IC1: [[EXIT]]: 2047*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[SPEC_SELECT_LCSSA:%.*]] = phi i64 [ [[SPEC_SELECT]], %[[FOR_BODY]] ] 2048*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: ret i64 [[SPEC_SELECT_LCSSA]] 2049*b3cba9beSMel Chen; 2050*b3cba9beSMel Chen; CHECK-VF4IC4-LABEL: define i64 @not_vectorized_select_decreasing_induction_icmp_iv_out_of_bound( 2051*b3cba9beSMel Chen; CHECK-VF4IC4-SAME: ptr [[A:%.*]]) { 2052*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[ENTRY:.*]]: 2053*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br label %[[FOR_BODY:.*]] 2054*b3cba9beSMel Chen; CHECK-VF4IC4: [[FOR_BODY]]: 2055*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[IV:%.*]] = phi i64 [ 9223372036854775807, %[[ENTRY]] ], [ [[DEC:%.*]], %[[FOR_BODY]] ] 2056*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX:%.*]] = phi i64 [ 331, %[[ENTRY]] ], [ [[SPEC_SELECT:%.*]], %[[FOR_BODY]] ] 2057*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]] 2058*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP0:%.*]] = load i64, ptr [[ARRAYIDX]], align 8 2059*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[CMP1:%.*]] = icmp sgt i64 [[TMP0]], 3 2060*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[SPEC_SELECT]] = select i1 [[CMP1]], i64 [[IV]], i64 [[RDX]] 2061*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[DEC]] = add nsw i64 [[IV]], -1 2062*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[CMP_NOT:%.*]] = icmp eq i64 [[IV]], 0 2063*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br i1 [[CMP_NOT]], label %[[EXIT:.*]], label %[[FOR_BODY]] 2064*b3cba9beSMel Chen; CHECK-VF4IC4: [[EXIT]]: 2065*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[SPEC_SELECT_LCSSA:%.*]] = phi i64 [ [[SPEC_SELECT]], %[[FOR_BODY]] ] 2066*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: ret i64 [[SPEC_SELECT_LCSSA]] 2067*b3cba9beSMel Chen; 2068*b3cba9beSMel Chen; CHECK-VF1IC4-LABEL: define i64 @not_vectorized_select_decreasing_induction_icmp_iv_out_of_bound( 2069*b3cba9beSMel Chen; CHECK-VF1IC4-SAME: ptr [[A:%.*]]) { 2070*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[ENTRY:.*]]: 2071*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br label %[[FOR_BODY:.*]] 2072*b3cba9beSMel Chen; CHECK-VF1IC4: [[FOR_BODY]]: 2073*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[IV:%.*]] = phi i64 [ 9223372036854775807, %[[ENTRY]] ], [ [[DEC:%.*]], %[[FOR_BODY]] ] 2074*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX:%.*]] = phi i64 [ 331, %[[ENTRY]] ], [ [[SPEC_SELECT:%.*]], %[[FOR_BODY]] ] 2075*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]] 2076*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP0:%.*]] = load i64, ptr [[ARRAYIDX]], align 8 2077*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[CMP1:%.*]] = icmp sgt i64 [[TMP0]], 3 2078*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[SPEC_SELECT]] = select i1 [[CMP1]], i64 [[IV]], i64 [[RDX]] 2079*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[DEC]] = add nsw i64 [[IV]], -1 2080*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[CMP_NOT:%.*]] = icmp eq i64 [[IV]], 0 2081*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br i1 [[CMP_NOT]], label %[[EXIT:.*]], label %[[FOR_BODY]] 2082*b3cba9beSMel Chen; CHECK-VF1IC4: [[EXIT]]: 2083*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[SPEC_SELECT_LCSSA:%.*]] = phi i64 [ [[SPEC_SELECT]], %[[FOR_BODY]] ] 2084*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: ret i64 [[SPEC_SELECT_LCSSA]] 2085ef48e904SRamkumar Ramachandra; 2086ef48e904SRamkumar Ramachandraentry: 2087ef48e904SRamkumar Ramachandra br label %for.body 2088ef48e904SRamkumar Ramachandra 2089ef48e904SRamkumar Ramachandrafor.body: ; preds = %entry, %for.body 2090ef48e904SRamkumar Ramachandra %iv = phi i64 [ 9223372036854775807, %entry ], [ %dec, %for.body ] 2091ef48e904SRamkumar Ramachandra %rdx = phi i64 [ 331, %entry ], [ %spec.select, %for.body ] 2092ef48e904SRamkumar Ramachandra %arrayidx = getelementptr inbounds i64, ptr %a, i64 %iv 2093ef48e904SRamkumar Ramachandra %0 = load i64, ptr %arrayidx, align 8 2094ef48e904SRamkumar Ramachandra %cmp1 = icmp sgt i64 %0, 3 2095ef48e904SRamkumar Ramachandra %spec.select = select i1 %cmp1, i64 %iv, i64 %rdx 2096ef48e904SRamkumar Ramachandra %dec = add nsw i64 %iv, -1 2097ef48e904SRamkumar Ramachandra %cmp.not = icmp eq i64 %iv, 0 2098ef48e904SRamkumar Ramachandra br i1 %cmp.not, label %exit, label %for.body 2099ef48e904SRamkumar Ramachandra 2100ef48e904SRamkumar Ramachandraexit: ; preds = %for.body 2101ef48e904SRamkumar Ramachandra ret i64 %spec.select 2102ef48e904SRamkumar Ramachandra} 2103ef48e904SRamkumar Ramachandra 2104707686b0SMel Chendefine i64 @not_vectorized_select_icmp_non_const_iv_start_value(ptr %a, ptr %b, i64 %ivstart, i64 %rdx.start, i64 %n) { 2105*b3cba9beSMel Chen; CHECK-VF4IC1-LABEL: define i64 @not_vectorized_select_icmp_non_const_iv_start_value( 2106*b3cba9beSMel Chen; CHECK-VF4IC1-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[IVSTART:%.*]], i64 [[RDX_START:%.*]], i64 [[N:%.*]]) { 2107*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[ENTRY:.*]]: 2108*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br label %[[FOR_BODY:.*]] 2109*b3cba9beSMel Chen; CHECK-VF4IC1: [[FOR_BODY]]: 2110*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[IV:%.*]] = phi i64 [ [[INC:%.*]], %[[FOR_BODY]] ], [ [[IVSTART]], %[[ENTRY]] ] 2111*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[RDX:%.*]] = phi i64 [ [[COND:%.*]], %[[FOR_BODY]] ], [ [[RDX_START]], %[[ENTRY]] ] 2112*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]] 2113*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP0:%.*]] = load i64, ptr [[ARRAYIDX]], align 8 2114*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[IV]] 2115*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[TMP1:%.*]] = load i64, ptr [[ARRAYIDX1]], align 8 2116*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[CMP2:%.*]] = icmp sgt i64 [[TMP0]], [[TMP1]] 2117*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[COND]] = select i1 [[CMP2]], i64 [[IV]], i64 [[RDX]] 2118*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[INC]] = add nuw nsw i64 [[IV]], 1 2119*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[N]] 2120*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT:.*]], label %[[FOR_BODY]] 2121*b3cba9beSMel Chen; CHECK-VF4IC1: [[EXIT]]: 2122*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: [[COND_LCSSA:%.*]] = phi i64 [ [[COND]], %[[FOR_BODY]] ] 2123*b3cba9beSMel Chen; CHECK-VF4IC1-NEXT: ret i64 [[COND_LCSSA]] 2124*b3cba9beSMel Chen; 2125*b3cba9beSMel Chen; CHECK-VF4IC4-LABEL: define i64 @not_vectorized_select_icmp_non_const_iv_start_value( 2126*b3cba9beSMel Chen; CHECK-VF4IC4-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[IVSTART:%.*]], i64 [[RDX_START:%.*]], i64 [[N:%.*]]) { 2127*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[ENTRY:.*]]: 2128*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br label %[[FOR_BODY:.*]] 2129*b3cba9beSMel Chen; CHECK-VF4IC4: [[FOR_BODY]]: 2130*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[IV:%.*]] = phi i64 [ [[INC:%.*]], %[[FOR_BODY]] ], [ [[IVSTART]], %[[ENTRY]] ] 2131*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[RDX:%.*]] = phi i64 [ [[COND:%.*]], %[[FOR_BODY]] ], [ [[RDX_START]], %[[ENTRY]] ] 2132*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]] 2133*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP0:%.*]] = load i64, ptr [[ARRAYIDX]], align 8 2134*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[IV]] 2135*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[TMP1:%.*]] = load i64, ptr [[ARRAYIDX1]], align 8 2136*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[CMP2:%.*]] = icmp sgt i64 [[TMP0]], [[TMP1]] 2137*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[COND]] = select i1 [[CMP2]], i64 [[IV]], i64 [[RDX]] 2138*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[INC]] = add nuw nsw i64 [[IV]], 1 2139*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[N]] 2140*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT:.*]], label %[[FOR_BODY]] 2141*b3cba9beSMel Chen; CHECK-VF4IC4: [[EXIT]]: 2142*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: [[COND_LCSSA:%.*]] = phi i64 [ [[COND]], %[[FOR_BODY]] ] 2143*b3cba9beSMel Chen; CHECK-VF4IC4-NEXT: ret i64 [[COND_LCSSA]] 2144*b3cba9beSMel Chen; 2145*b3cba9beSMel Chen; CHECK-VF1IC4-LABEL: define i64 @not_vectorized_select_icmp_non_const_iv_start_value( 2146*b3cba9beSMel Chen; CHECK-VF1IC4-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i64 [[IVSTART:%.*]], i64 [[RDX_START:%.*]], i64 [[N:%.*]]) { 2147*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[ENTRY:.*]]: 2148*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br label %[[FOR_BODY:.*]] 2149*b3cba9beSMel Chen; CHECK-VF1IC4: [[FOR_BODY]]: 2150*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[IV:%.*]] = phi i64 [ [[INC:%.*]], %[[FOR_BODY]] ], [ [[IVSTART]], %[[ENTRY]] ] 2151*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[RDX:%.*]] = phi i64 [ [[COND:%.*]], %[[FOR_BODY]] ], [ [[RDX_START]], %[[ENTRY]] ] 2152*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]] 2153*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP0:%.*]] = load i64, ptr [[ARRAYIDX]], align 8 2154*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[IV]] 2155*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[TMP1:%.*]] = load i64, ptr [[ARRAYIDX1]], align 8 2156*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[CMP2:%.*]] = icmp sgt i64 [[TMP0]], [[TMP1]] 2157*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[COND]] = select i1 [[CMP2]], i64 [[IV]], i64 [[RDX]] 2158*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[INC]] = add nuw nsw i64 [[IV]], 1 2159*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[N]] 2160*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT:.*]], label %[[FOR_BODY]] 2161*b3cba9beSMel Chen; CHECK-VF1IC4: [[EXIT]]: 2162*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: [[COND_LCSSA:%.*]] = phi i64 [ [[COND]], %[[FOR_BODY]] ] 2163*b3cba9beSMel Chen; CHECK-VF1IC4-NEXT: ret i64 [[COND_LCSSA]] 21644ddc1745SMel Chen; 21654ddc1745SMel Chenentry: 21664ddc1745SMel Chen br label %for.body 21674ddc1745SMel Chen 21684ddc1745SMel Chenfor.body: ; preds = %entry, %for.body 21694ddc1745SMel Chen %iv = phi i64 [ %inc, %for.body ], [ %ivstart, %entry ] 21704ddc1745SMel Chen %rdx = phi i64 [ %cond, %for.body ], [ %rdx.start, %entry ] 21714ddc1745SMel Chen %arrayidx = getelementptr inbounds i64, ptr %a, i64 %iv 21724ddc1745SMel Chen %0 = load i64, ptr %arrayidx, align 8 21734ddc1745SMel Chen %arrayidx1 = getelementptr inbounds i64, ptr %b, i64 %iv 21744ddc1745SMel Chen %1 = load i64, ptr %arrayidx1, align 8 21754ddc1745SMel Chen %cmp2 = icmp sgt i64 %0, %1 21764ddc1745SMel Chen %cond = select i1 %cmp2, i64 %iv, i64 %rdx 21774ddc1745SMel Chen %inc = add nuw nsw i64 %iv, 1 21784ddc1745SMel Chen %exitcond.not = icmp eq i64 %inc, %n 21794ddc1745SMel Chen br i1 %exitcond.not, label %exit, label %for.body 21804ddc1745SMel Chen 21814ddc1745SMel Chenexit: ; preds = %for.body 21824ddc1745SMel Chen ret i64 %cond 21834ddc1745SMel Chen} 2184*b3cba9beSMel Chen;. 2185*b3cba9beSMel Chen; CHECK-VF4IC1: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]} 2186*b3cba9beSMel Chen; CHECK-VF4IC1: [[META1]] = !{!"llvm.loop.isvectorized", i32 1} 2187*b3cba9beSMel Chen; CHECK-VF4IC1: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"} 2188*b3cba9beSMel Chen; CHECK-VF4IC1: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]} 2189*b3cba9beSMel Chen; CHECK-VF4IC1: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]} 2190*b3cba9beSMel Chen; CHECK-VF4IC1: [[LOOP5]] = distinct !{[[LOOP5]], [[META2]], [[META1]]} 2191*b3cba9beSMel Chen; CHECK-VF4IC1: [[LOOP6]] = distinct !{[[LOOP6]], [[META1]], [[META2]]} 2192*b3cba9beSMel Chen; CHECK-VF4IC1: [[LOOP7]] = distinct !{[[LOOP7]], [[META2]], [[META1]]} 2193*b3cba9beSMel Chen; CHECK-VF4IC1: [[LOOP8]] = distinct !{[[LOOP8]], [[META1]], [[META2]]} 2194*b3cba9beSMel Chen; CHECK-VF4IC1: [[LOOP9]] = distinct !{[[LOOP9]], [[META2]], [[META1]]} 2195*b3cba9beSMel Chen; CHECK-VF4IC1: [[LOOP10]] = distinct !{[[LOOP10]], [[META1]], [[META2]]} 2196*b3cba9beSMel Chen; CHECK-VF4IC1: [[LOOP11]] = distinct !{[[LOOP11]], [[META2]], [[META1]]} 2197*b3cba9beSMel Chen; CHECK-VF4IC1: [[LOOP12]] = distinct !{[[LOOP12]], [[META1]], [[META2]]} 2198*b3cba9beSMel Chen; CHECK-VF4IC1: [[LOOP13]] = distinct !{[[LOOP13]], [[META2]], [[META1]]} 2199*b3cba9beSMel Chen; CHECK-VF4IC1: [[LOOP14]] = distinct !{[[LOOP14]], [[META1]], [[META2]]} 2200*b3cba9beSMel Chen; CHECK-VF4IC1: [[LOOP15]] = distinct !{[[LOOP15]], [[META2]], [[META1]]} 2201*b3cba9beSMel Chen; CHECK-VF4IC1: [[LOOP16]] = distinct !{[[LOOP16]], [[META1]], [[META2]]} 2202*b3cba9beSMel Chen; CHECK-VF4IC1: [[LOOP17]] = distinct !{[[LOOP17]], [[META2]], [[META1]]} 2203*b3cba9beSMel Chen;. 2204*b3cba9beSMel Chen; CHECK-VF4IC4: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]} 2205*b3cba9beSMel Chen; CHECK-VF4IC4: [[META1]] = !{!"llvm.loop.isvectorized", i32 1} 2206*b3cba9beSMel Chen; CHECK-VF4IC4: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"} 2207*b3cba9beSMel Chen; CHECK-VF4IC4: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]} 2208*b3cba9beSMel Chen; CHECK-VF4IC4: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]} 2209*b3cba9beSMel Chen; CHECK-VF4IC4: [[LOOP5]] = distinct !{[[LOOP5]], [[META2]], [[META1]]} 2210*b3cba9beSMel Chen; CHECK-VF4IC4: [[LOOP6]] = distinct !{[[LOOP6]], [[META1]], [[META2]]} 2211*b3cba9beSMel Chen; CHECK-VF4IC4: [[LOOP7]] = distinct !{[[LOOP7]], [[META2]], [[META1]]} 2212*b3cba9beSMel Chen; CHECK-VF4IC4: [[LOOP8]] = distinct !{[[LOOP8]], [[META1]], [[META2]]} 2213*b3cba9beSMel Chen; CHECK-VF4IC4: [[LOOP9]] = distinct !{[[LOOP9]], [[META2]], [[META1]]} 2214*b3cba9beSMel Chen; CHECK-VF4IC4: [[LOOP10]] = distinct !{[[LOOP10]], [[META1]], [[META2]]} 2215*b3cba9beSMel Chen; CHECK-VF4IC4: [[LOOP11]] = distinct !{[[LOOP11]], [[META2]], [[META1]]} 2216*b3cba9beSMel Chen; CHECK-VF4IC4: [[LOOP12]] = distinct !{[[LOOP12]], [[META1]], [[META2]]} 2217*b3cba9beSMel Chen; CHECK-VF4IC4: [[LOOP13]] = distinct !{[[LOOP13]], [[META2]], [[META1]]} 2218*b3cba9beSMel Chen; CHECK-VF4IC4: [[LOOP14]] = distinct !{[[LOOP14]], [[META1]], [[META2]]} 2219*b3cba9beSMel Chen; CHECK-VF4IC4: [[LOOP15]] = distinct !{[[LOOP15]], [[META2]], [[META1]]} 2220*b3cba9beSMel Chen; CHECK-VF4IC4: [[LOOP16]] = distinct !{[[LOOP16]], [[META1]], [[META2]]} 2221*b3cba9beSMel Chen; CHECK-VF4IC4: [[LOOP17]] = distinct !{[[LOOP17]], [[META2]], [[META1]]} 2222*b3cba9beSMel Chen;. 2223*b3cba9beSMel Chen; CHECK-VF1IC4: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]} 2224*b3cba9beSMel Chen; CHECK-VF1IC4: [[META1]] = !{!"llvm.loop.isvectorized", i32 1} 2225*b3cba9beSMel Chen; CHECK-VF1IC4: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"} 2226*b3cba9beSMel Chen; CHECK-VF1IC4: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]]} 2227*b3cba9beSMel Chen; CHECK-VF1IC4: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]} 2228*b3cba9beSMel Chen; CHECK-VF1IC4: [[LOOP5]] = distinct !{[[LOOP5]], [[META1]]} 2229*b3cba9beSMel Chen; CHECK-VF1IC4: [[LOOP6]] = distinct !{[[LOOP6]], [[META1]], [[META2]]} 2230*b3cba9beSMel Chen; CHECK-VF1IC4: [[LOOP7]] = distinct !{[[LOOP7]], [[META1]]} 2231*b3cba9beSMel Chen; CHECK-VF1IC4: [[LOOP8]] = distinct !{[[LOOP8]], [[META1]], [[META2]]} 2232*b3cba9beSMel Chen; CHECK-VF1IC4: [[LOOP9]] = distinct !{[[LOOP9]], [[META1]]} 2233*b3cba9beSMel Chen; CHECK-VF1IC4: [[LOOP10]] = distinct !{[[LOOP10]], [[META1]], [[META2]]} 2234*b3cba9beSMel Chen; CHECK-VF1IC4: [[LOOP11]] = distinct !{[[LOOP11]], [[META1]]} 2235*b3cba9beSMel Chen; CHECK-VF1IC4: [[LOOP12]] = distinct !{[[LOOP12]], [[META1]], [[META2]]} 2236*b3cba9beSMel Chen; CHECK-VF1IC4: [[LOOP13]] = distinct !{[[LOOP13]], [[META1]]} 2237*b3cba9beSMel Chen; CHECK-VF1IC4: [[LOOP14]] = distinct !{[[LOOP14]], [[META1]], [[META2]]} 2238*b3cba9beSMel Chen; CHECK-VF1IC4: [[LOOP15]] = distinct !{[[LOOP15]], [[META1]]} 2239*b3cba9beSMel Chen; CHECK-VF1IC4: [[LOOP16]] = distinct !{[[LOOP16]], [[META1]], [[META2]]} 2240*b3cba9beSMel Chen; CHECK-VF1IC4: [[LOOP17]] = distinct !{[[LOOP17]], [[META1]]} 2241*b3cba9beSMel Chen;. 2242