xref: /llvm-project/llvm/test/Transforms/LoopVectorize/iv-select-cmp-nested-loop.ll (revision 7f3428d3ed71d87a2088b77b6cab9f3d86544234) 
1f4081711SMel Chen; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
2f4081711SMel Chen; RUN: opt -passes=loop-vectorize -force-vector-interleave=1 -force-vector-width=4 -S < %s | FileCheck %s --check-prefix=CHECK-VF4IC1
3f4081711SMel Chen; RUN: opt -passes=loop-vectorize -force-vector-interleave=4 -force-vector-width=4 -S < %s | FileCheck %s --check-prefix=CHECK-VF4IC4
4f4081711SMel Chen; RUN: opt -passes=loop-vectorize -force-vector-interleave=4 -force-vector-width=1 -S < %s | FileCheck %s --check-prefix=CHECK-VF1IC4
5f4081711SMel Chen
6f4081711SMel Chen; This should be an AnyOf reduction instead of FindLastIV reduction.
7f4081711SMel Chen; The reason is the outer induction variable is invariant for inner loop.
8f4081711SMel Chendefine i64 @select_iv_def_from_outer_loop(ptr %a, i64 %start, i64 %n) {
9f4081711SMel Chen; CHECK-VF4IC1-LABEL: define i64 @select_iv_def_from_outer_loop(
10f4081711SMel Chen; CHECK-VF4IC1-SAME: ptr [[A:%.*]], i64 [[START:%.*]], i64 [[N:%.*]]) {
11f4081711SMel Chen; CHECK-VF4IC1-NEXT:  [[ENTRY:.*]]:
12f4081711SMel Chen; CHECK-VF4IC1-NEXT:    br label %[[OUTER_LOOP:.*]]
13f4081711SMel Chen; CHECK-VF4IC1:       [[OUTER_LOOP]]:
14f4081711SMel Chen; CHECK-VF4IC1-NEXT:    [[RDX_OUTER:%.*]] = phi i64 [ [[START]], %[[ENTRY]] ], [ [[SELECT_LCSSA:%.*]], %[[OUTER_LOOP_EXIT:.*]] ]
15f4081711SMel Chen; CHECK-VF4IC1-NEXT:    [[IV_OUTER:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_OUTER_NEXT:%.*]], %[[OUTER_LOOP_EXIT]] ]
16f4081711SMel Chen; CHECK-VF4IC1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds ptr, ptr [[A]], i64 [[IV_OUTER]]
17f4081711SMel Chen; CHECK-VF4IC1-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8
18f4081711SMel Chen; CHECK-VF4IC1-NEXT:    [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4
19f4081711SMel Chen; CHECK-VF4IC1-NEXT:    br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
20f4081711SMel Chen; CHECK-VF4IC1:       [[VECTOR_PH]]:
21f4081711SMel Chen; CHECK-VF4IC1-NEXT:    [[N_MOD_VF:%.*]] = urem i64 [[N]], 4
22f4081711SMel Chen; CHECK-VF4IC1-NEXT:    [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
23f4081711SMel Chen; CHECK-VF4IC1-NEXT:    br label %[[VECTOR_BODY:.*]]
24f4081711SMel Chen; CHECK-VF4IC1:       [[VECTOR_BODY]]:
25f4081711SMel Chen; CHECK-VF4IC1-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
26f4081711SMel Chen; CHECK-VF4IC1-NEXT:    [[VEC_PHI:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP5:%.*]], %[[VECTOR_BODY]] ]
27f4081711SMel Chen; CHECK-VF4IC1-NEXT:    [[TMP1:%.*]] = add i64 [[INDEX]], 0
28f4081711SMel Chen; CHECK-VF4IC1-NEXT:    [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i64 [[TMP1]]
29f4081711SMel Chen; CHECK-VF4IC1-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP2]], i32 0
30f4081711SMel Chen; CHECK-VF4IC1-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP3]], align 8
31f4081711SMel Chen; CHECK-VF4IC1-NEXT:    [[TMP4:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], splat (i64 3)
32f4081711SMel Chen; CHECK-VF4IC1-NEXT:    [[TMP5]] = or <4 x i1> [[VEC_PHI]], [[TMP4]]
33f4081711SMel Chen; CHECK-VF4IC1-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
34f4081711SMel Chen; CHECK-VF4IC1-NEXT:    [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
35f4081711SMel Chen; CHECK-VF4IC1-NEXT:    br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
36f4081711SMel Chen; CHECK-VF4IC1:       [[MIDDLE_BLOCK]]:
37f4081711SMel Chen; CHECK-VF4IC1-NEXT:    [[TMP7:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP5]])
38f4081711SMel Chen; CHECK-VF4IC1-NEXT:    [[TMP8:%.*]] = freeze i1 [[TMP7]]
39f4081711SMel Chen; CHECK-VF4IC1-NEXT:    [[RDX_SELECT:%.*]] = select i1 [[TMP8]], i64 [[IV_OUTER]], i64 [[RDX_OUTER]]
40f4081711SMel Chen; CHECK-VF4IC1-NEXT:    [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
41f4081711SMel Chen; CHECK-VF4IC1-NEXT:    br i1 [[CMP_N]], label %[[OUTER_LOOP_EXIT]], label %[[SCALAR_PH]]
42f4081711SMel Chen; CHECK-VF4IC1:       [[SCALAR_PH]]:
43f4081711SMel Chen; CHECK-VF4IC1-NEXT:    [[BC_MERGE_RDX:%.*]] = phi i64 [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ], [ [[RDX_OUTER]], %[[OUTER_LOOP]] ]
44*7f3428d3SFlorian Hahn; CHECK-VF4IC1-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[OUTER_LOOP]] ]
45f4081711SMel Chen; CHECK-VF4IC1-NEXT:    br label %[[INNER_LOOP:.*]]
46f4081711SMel Chen; CHECK-VF4IC1:       [[INNER_LOOP]]:
47f4081711SMel Chen; CHECK-VF4IC1-NEXT:    [[RDX_INNER:%.*]] = phi i64 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[SELECT:%.*]], %[[INNER_LOOP]] ]
48f4081711SMel Chen; CHECK-VF4IC1-NEXT:    [[IV_INNER:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_INNER_NEXT:%.*]], %[[INNER_LOOP]] ]
49f4081711SMel Chen; CHECK-VF4IC1-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i64 [[IV_INNER]]
50f4081711SMel Chen; CHECK-VF4IC1-NEXT:    [[TMP9:%.*]] = load i64, ptr [[ARRAYIDX2]], align 8
51f4081711SMel Chen; CHECK-VF4IC1-NEXT:    [[CMP:%.*]] = icmp eq i64 [[TMP9]], 3
52f4081711SMel Chen; CHECK-VF4IC1-NEXT:    [[SELECT]] = select i1 [[CMP]], i64 [[IV_OUTER]], i64 [[RDX_INNER]]
53f4081711SMel Chen; CHECK-VF4IC1-NEXT:    [[IV_INNER_NEXT]] = add nuw nsw i64 [[IV_INNER]], 1
54f4081711SMel Chen; CHECK-VF4IC1-NEXT:    [[EXITCOND_NOT_INNER:%.*]] = icmp eq i64 [[IV_INNER_NEXT]], [[N]]
55f4081711SMel Chen; CHECK-VF4IC1-NEXT:    br i1 [[EXITCOND_NOT_INNER]], label %[[OUTER_LOOP_EXIT]], label %[[INNER_LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
56f4081711SMel Chen; CHECK-VF4IC1:       [[OUTER_LOOP_EXIT]]:
57f4081711SMel Chen; CHECK-VF4IC1-NEXT:    [[SELECT_LCSSA]] = phi i64 [ [[SELECT]], %[[INNER_LOOP]] ], [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ]
58f4081711SMel Chen; CHECK-VF4IC1-NEXT:    [[IV_OUTER_NEXT]] = add nuw nsw i64 [[IV_OUTER]], 1
59f4081711SMel Chen; CHECK-VF4IC1-NEXT:    [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_OUTER_NEXT]], [[N]]
60f4081711SMel Chen; CHECK-VF4IC1-NEXT:    br i1 [[EXITCOND_NOT]], label %[[EXIT:.*]], label %[[OUTER_LOOP]]
61f4081711SMel Chen; CHECK-VF4IC1:       [[EXIT]]:
62f4081711SMel Chen; CHECK-VF4IC1-NEXT:    [[SELECT_LCSSA_LCSSA:%.*]] = phi i64 [ [[SELECT_LCSSA]], %[[OUTER_LOOP_EXIT]] ]
63f4081711SMel Chen; CHECK-VF4IC1-NEXT:    ret i64 [[SELECT_LCSSA_LCSSA]]
64f4081711SMel Chen;
65f4081711SMel Chen; CHECK-VF4IC4-LABEL: define i64 @select_iv_def_from_outer_loop(
66f4081711SMel Chen; CHECK-VF4IC4-SAME: ptr [[A:%.*]], i64 [[START:%.*]], i64 [[N:%.*]]) {
67f4081711SMel Chen; CHECK-VF4IC4-NEXT:  [[ENTRY:.*]]:
68f4081711SMel Chen; CHECK-VF4IC4-NEXT:    br label %[[OUTER_LOOP:.*]]
69f4081711SMel Chen; CHECK-VF4IC4:       [[OUTER_LOOP]]:
70f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[RDX_OUTER:%.*]] = phi i64 [ [[START]], %[[ENTRY]] ], [ [[SELECT_LCSSA:%.*]], %[[OUTER_LOOP_EXIT:.*]] ]
71f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[IV_OUTER:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_OUTER_NEXT:%.*]], %[[OUTER_LOOP_EXIT]] ]
72f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds ptr, ptr [[A]], i64 [[IV_OUTER]]
73f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8
74f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 16
75f4081711SMel Chen; CHECK-VF4IC4-NEXT:    br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
76f4081711SMel Chen; CHECK-VF4IC4:       [[VECTOR_PH]]:
77f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[N_MOD_VF:%.*]] = urem i64 [[N]], 16
78f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
79f4081711SMel Chen; CHECK-VF4IC4-NEXT:    br label %[[VECTOR_BODY:.*]]
80f4081711SMel Chen; CHECK-VF4IC4:       [[VECTOR_BODY]]:
81f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
82f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[VEC_PHI:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP11:%.*]], %[[VECTOR_BODY]] ]
83f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[VEC_PHI1:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP12:%.*]], %[[VECTOR_BODY]] ]
84f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[VEC_PHI2:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP13:%.*]], %[[VECTOR_BODY]] ]
85f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[VEC_PHI3:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP14:%.*]], %[[VECTOR_BODY]] ]
86f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[TMP1:%.*]] = add i64 [[INDEX]], 0
87f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[TMP2:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i64 [[TMP1]]
88f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP2]], i32 0
89f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP2]], i32 4
90f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP2]], i32 8
91f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP2]], i32 12
92f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP3]], align 8
93f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[WIDE_LOAD4:%.*]] = load <4 x i64>, ptr [[TMP4]], align 8
94f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[WIDE_LOAD5:%.*]] = load <4 x i64>, ptr [[TMP5]], align 8
95f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[WIDE_LOAD6:%.*]] = load <4 x i64>, ptr [[TMP6]], align 8
96f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[TMP7:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD]], splat (i64 3)
97f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[TMP8:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD4]], splat (i64 3)
98f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[TMP9:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD5]], splat (i64 3)
99f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[TMP10:%.*]] = icmp eq <4 x i64> [[WIDE_LOAD6]], splat (i64 3)
100f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[TMP11]] = or <4 x i1> [[VEC_PHI]], [[TMP7]]
101f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[TMP12]] = or <4 x i1> [[VEC_PHI1]], [[TMP8]]
102f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[TMP13]] = or <4 x i1> [[VEC_PHI2]], [[TMP9]]
103f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[TMP14]] = or <4 x i1> [[VEC_PHI3]], [[TMP10]]
104f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16
105f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[TMP15:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
106f4081711SMel Chen; CHECK-VF4IC4-NEXT:    br i1 [[TMP15]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
107f4081711SMel Chen; CHECK-VF4IC4:       [[MIDDLE_BLOCK]]:
108f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[BIN_RDX:%.*]] = or <4 x i1> [[TMP12]], [[TMP11]]
109f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[BIN_RDX7:%.*]] = or <4 x i1> [[TMP13]], [[BIN_RDX]]
110f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[BIN_RDX8:%.*]] = or <4 x i1> [[TMP14]], [[BIN_RDX7]]
111f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[TMP16:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[BIN_RDX8]])
112f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[TMP17:%.*]] = freeze i1 [[TMP16]]
113f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[RDX_SELECT:%.*]] = select i1 [[TMP17]], i64 [[IV_OUTER]], i64 [[RDX_OUTER]]
114f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
115f4081711SMel Chen; CHECK-VF4IC4-NEXT:    br i1 [[CMP_N]], label %[[OUTER_LOOP_EXIT]], label %[[SCALAR_PH]]
116f4081711SMel Chen; CHECK-VF4IC4:       [[SCALAR_PH]]:
117f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[BC_MERGE_RDX:%.*]] = phi i64 [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ], [ [[RDX_OUTER]], %[[OUTER_LOOP]] ]
118*7f3428d3SFlorian Hahn; CHECK-VF4IC4-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[OUTER_LOOP]] ]
119f4081711SMel Chen; CHECK-VF4IC4-NEXT:    br label %[[INNER_LOOP:.*]]
120f4081711SMel Chen; CHECK-VF4IC4:       [[INNER_LOOP]]:
121f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[RDX_INNER:%.*]] = phi i64 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[SELECT:%.*]], %[[INNER_LOOP]] ]
122f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[IV_INNER:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_INNER_NEXT:%.*]], %[[INNER_LOOP]] ]
123f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i64 [[IV_INNER]]
124f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[TMP18:%.*]] = load i64, ptr [[ARRAYIDX2]], align 8
125f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[CMP:%.*]] = icmp eq i64 [[TMP18]], 3
126f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[SELECT]] = select i1 [[CMP]], i64 [[IV_OUTER]], i64 [[RDX_INNER]]
127f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[IV_INNER_NEXT]] = add nuw nsw i64 [[IV_INNER]], 1
128f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[EXITCOND_NOT_INNER:%.*]] = icmp eq i64 [[IV_INNER_NEXT]], [[N]]
129f4081711SMel Chen; CHECK-VF4IC4-NEXT:    br i1 [[EXITCOND_NOT_INNER]], label %[[OUTER_LOOP_EXIT]], label %[[INNER_LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
130f4081711SMel Chen; CHECK-VF4IC4:       [[OUTER_LOOP_EXIT]]:
131f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[SELECT_LCSSA]] = phi i64 [ [[SELECT]], %[[INNER_LOOP]] ], [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ]
132f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[IV_OUTER_NEXT]] = add nuw nsw i64 [[IV_OUTER]], 1
133f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_OUTER_NEXT]], [[N]]
134f4081711SMel Chen; CHECK-VF4IC4-NEXT:    br i1 [[EXITCOND_NOT]], label %[[EXIT:.*]], label %[[OUTER_LOOP]]
135f4081711SMel Chen; CHECK-VF4IC4:       [[EXIT]]:
136f4081711SMel Chen; CHECK-VF4IC4-NEXT:    [[SELECT_LCSSA_LCSSA:%.*]] = phi i64 [ [[SELECT_LCSSA]], %[[OUTER_LOOP_EXIT]] ]
137f4081711SMel Chen; CHECK-VF4IC4-NEXT:    ret i64 [[SELECT_LCSSA_LCSSA]]
138f4081711SMel Chen;
139f4081711SMel Chen; CHECK-VF1IC4-LABEL: define i64 @select_iv_def_from_outer_loop(
140f4081711SMel Chen; CHECK-VF1IC4-SAME: ptr [[A:%.*]], i64 [[START:%.*]], i64 [[N:%.*]]) {
141f4081711SMel Chen; CHECK-VF1IC4-NEXT:  [[ENTRY:.*]]:
142f4081711SMel Chen; CHECK-VF1IC4-NEXT:    br label %[[OUTER_LOOP:.*]]
143f4081711SMel Chen; CHECK-VF1IC4:       [[OUTER_LOOP]]:
144f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[RDX_OUTER:%.*]] = phi i64 [ [[START]], %[[ENTRY]] ], [ [[SELECT_LCSSA:%.*]], %[[OUTER_LOOP_EXIT:.*]] ]
145f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[IV_OUTER:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_OUTER_NEXT:%.*]], %[[OUTER_LOOP_EXIT]] ]
146f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds ptr, ptr [[A]], i64 [[IV_OUTER]]
147f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[TMP0:%.*]] = load ptr, ptr [[ARRAYIDX]], align 8
148f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4
149f4081711SMel Chen; CHECK-VF1IC4-NEXT:    br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
150f4081711SMel Chen; CHECK-VF1IC4:       [[VECTOR_PH]]:
151f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[N_MOD_VF:%.*]] = urem i64 [[N]], 4
152f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
153f4081711SMel Chen; CHECK-VF1IC4-NEXT:    br label %[[VECTOR_BODY:.*]]
154f4081711SMel Chen; CHECK-VF1IC4:       [[VECTOR_BODY]]:
155f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
156f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[VEC_PHI:%.*]] = phi i1 [ false, %[[VECTOR_PH]] ], [ [[TMP17:%.*]], %[[VECTOR_BODY]] ]
157f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[VEC_PHI1:%.*]] = phi i1 [ false, %[[VECTOR_PH]] ], [ [[TMP18:%.*]], %[[VECTOR_BODY]] ]
158f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[VEC_PHI2:%.*]] = phi i1 [ false, %[[VECTOR_PH]] ], [ [[TMP19:%.*]], %[[VECTOR_BODY]] ]
159f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[VEC_PHI3:%.*]] = phi i1 [ false, %[[VECTOR_PH]] ], [ [[TMP20:%.*]], %[[VECTOR_BODY]] ]
160f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[TMP1:%.*]] = add i64 [[INDEX]], 0
161f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[TMP2:%.*]] = add i64 [[INDEX]], 1
162f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[TMP3:%.*]] = add i64 [[INDEX]], 2
163f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[TMP4:%.*]] = add i64 [[INDEX]], 3
164f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i64 [[TMP1]]
165f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[TMP6:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i64 [[TMP2]]
166f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[TMP7:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i64 [[TMP3]]
167f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[TMP8:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i64 [[TMP4]]
168f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[TMP9:%.*]] = load i64, ptr [[TMP5]], align 8
169f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[TMP10:%.*]] = load i64, ptr [[TMP6]], align 8
170f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[TMP11:%.*]] = load i64, ptr [[TMP7]], align 8
171f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[TMP12:%.*]] = load i64, ptr [[TMP8]], align 8
172f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[TMP13:%.*]] = icmp eq i64 [[TMP9]], 3
173f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[TMP14:%.*]] = icmp eq i64 [[TMP10]], 3
174f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[TMP15:%.*]] = icmp eq i64 [[TMP11]], 3
175f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[TMP16:%.*]] = icmp eq i64 [[TMP12]], 3
176f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[TMP17]] = or i1 [[VEC_PHI]], [[TMP13]]
177f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[TMP18]] = or i1 [[VEC_PHI1]], [[TMP14]]
178f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[TMP19]] = or i1 [[VEC_PHI2]], [[TMP15]]
179f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[TMP20]] = or i1 [[VEC_PHI3]], [[TMP16]]
180f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
181f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[TMP21:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
182f4081711SMel Chen; CHECK-VF1IC4-NEXT:    br i1 [[TMP21]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
183f4081711SMel Chen; CHECK-VF1IC4:       [[MIDDLE_BLOCK]]:
184f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[BIN_RDX:%.*]] = or i1 [[TMP18]], [[TMP17]]
185f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[BIN_RDX4:%.*]] = or i1 [[TMP19]], [[BIN_RDX]]
186f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[BIN_RDX5:%.*]] = or i1 [[TMP20]], [[BIN_RDX4]]
187f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[TMP22:%.*]] = freeze i1 [[BIN_RDX5]]
188f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[RDX_SELECT:%.*]] = select i1 [[TMP22]], i64 [[IV_OUTER]], i64 [[RDX_OUTER]]
189f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
190f4081711SMel Chen; CHECK-VF1IC4-NEXT:    br i1 [[CMP_N]], label %[[OUTER_LOOP_EXIT]], label %[[SCALAR_PH]]
191f4081711SMel Chen; CHECK-VF1IC4:       [[SCALAR_PH]]:
192f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[BC_MERGE_RDX:%.*]] = phi i64 [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ], [ [[RDX_OUTER]], %[[OUTER_LOOP]] ]
193*7f3428d3SFlorian Hahn; CHECK-VF1IC4-NEXT:    [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[OUTER_LOOP]] ]
194f4081711SMel Chen; CHECK-VF1IC4-NEXT:    br label %[[INNER_LOOP:.*]]
195f4081711SMel Chen; CHECK-VF1IC4:       [[INNER_LOOP]]:
196f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[RDX_INNER:%.*]] = phi i64 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[SELECT:%.*]], %[[INNER_LOOP]] ]
197f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[IV_INNER:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_INNER_NEXT:%.*]], %[[INNER_LOOP]] ]
198f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i64, ptr [[TMP0]], i64 [[IV_INNER]]
199f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[TMP23:%.*]] = load i64, ptr [[ARRAYIDX2]], align 8
200f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[CMP:%.*]] = icmp eq i64 [[TMP23]], 3
201f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[SELECT]] = select i1 [[CMP]], i64 [[IV_OUTER]], i64 [[RDX_INNER]]
202f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[IV_INNER_NEXT]] = add nuw nsw i64 [[IV_INNER]], 1
203f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[EXITCOND_NOT_INNER:%.*]] = icmp eq i64 [[IV_INNER_NEXT]], [[N]]
204f4081711SMel Chen; CHECK-VF1IC4-NEXT:    br i1 [[EXITCOND_NOT_INNER]], label %[[OUTER_LOOP_EXIT]], label %[[INNER_LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
205f4081711SMel Chen; CHECK-VF1IC4:       [[OUTER_LOOP_EXIT]]:
206f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[SELECT_LCSSA]] = phi i64 [ [[SELECT]], %[[INNER_LOOP]] ], [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ]
207f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[IV_OUTER_NEXT]] = add nuw nsw i64 [[IV_OUTER]], 1
208f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[EXITCOND_NOT:%.*]] = icmp eq i64 [[IV_OUTER_NEXT]], [[N]]
209f4081711SMel Chen; CHECK-VF1IC4-NEXT:    br i1 [[EXITCOND_NOT]], label %[[EXIT:.*]], label %[[OUTER_LOOP]]
210f4081711SMel Chen; CHECK-VF1IC4:       [[EXIT]]:
211f4081711SMel Chen; CHECK-VF1IC4-NEXT:    [[SELECT_LCSSA_LCSSA:%.*]] = phi i64 [ [[SELECT_LCSSA]], %[[OUTER_LOOP_EXIT]] ]
212f4081711SMel Chen; CHECK-VF1IC4-NEXT:    ret i64 [[SELECT_LCSSA_LCSSA]]
213f4081711SMel Chen;
214f4081711SMel Chenentry:
215f4081711SMel Chen  br label %outer.loop
216f4081711SMel Chen
217f4081711SMel Chenouter.loop:
218f4081711SMel Chen  %rdx.outer = phi i64 [ %start, %entry ], [ %select, %outer.loop.exit ]
219f4081711SMel Chen  %iv.outer = phi i64 [ 0, %entry ], [ %iv.outer.next, %outer.loop.exit ]
220f4081711SMel Chen  %arrayidx = getelementptr inbounds ptr, ptr %a, i64 %iv.outer
221f4081711SMel Chen  %0 = load ptr, ptr %arrayidx, align 8
222f4081711SMel Chen  br label %inner.loop
223f4081711SMel Chen
224f4081711SMel Cheninner.loop:
225f4081711SMel Chen  %rdx.inner = phi i64 [ %rdx.outer, %outer.loop ], [ %select, %inner.loop ]
226f4081711SMel Chen  %iv.inner = phi i64 [ 0, %outer.loop ], [ %iv.inner.next, %inner.loop ]
227f4081711SMel Chen  %arrayidx2 = getelementptr inbounds i64, ptr %0, i64 %iv.inner
228f4081711SMel Chen  %1 = load i64, ptr %arrayidx2, align 8
229f4081711SMel Chen  %cmp = icmp eq i64 %1, 3
230f4081711SMel Chen  %select = select i1 %cmp, i64 %iv.outer, i64 %rdx.inner
231f4081711SMel Chen  %iv.inner.next = add nuw nsw i64 %iv.inner, 1
232f4081711SMel Chen  %exitcond.not.inner = icmp eq i64 %iv.inner.next, %n
233f4081711SMel Chen  br i1 %exitcond.not.inner, label %outer.loop.exit, label %inner.loop
234f4081711SMel Chen
235f4081711SMel Chenouter.loop.exit:
236f4081711SMel Chen  %iv.outer.next = add nuw nsw i64 %iv.outer, 1
237f4081711SMel Chen  %exitcond.not = icmp eq i64 %iv.outer.next, %n
238f4081711SMel Chen  br i1 %exitcond.not, label %exit, label %outer.loop
239f4081711SMel Chen
240f4081711SMel Chenexit:
241f4081711SMel Chen  ret i64 %select
242f4081711SMel Chen}
243f4081711SMel Chen;.
244f4081711SMel Chen; CHECK-VF4IC1: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
245f4081711SMel Chen; CHECK-VF4IC1: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
246f4081711SMel Chen; CHECK-VF4IC1: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
247f4081711SMel Chen; CHECK-VF4IC1: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}
248f4081711SMel Chen;.
249f4081711SMel Chen; CHECK-VF4IC4: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
250f4081711SMel Chen; CHECK-VF4IC4: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
251f4081711SMel Chen; CHECK-VF4IC4: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
252f4081711SMel Chen; CHECK-VF4IC4: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}
253f4081711SMel Chen;.
254f4081711SMel Chen; CHECK-VF1IC4: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
255f4081711SMel Chen; CHECK-VF1IC4: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
256f4081711SMel Chen; CHECK-VF1IC4: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
257f4081711SMel Chen; CHECK-VF1IC4: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]]}
258f4081711SMel Chen;.
259