1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 2; RUN: opt -passes=loop-vectorize -enable-epilogue-vectorization=false -mattr=+neon -S < %s | FileCheck %s 3 4target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" 5target triple = "aarch64-none-unknown-elf" 6 7define i32 @not_dotp(ptr %a, ptr %b) { 8; CHECK-LABEL: define i32 @not_dotp( 9; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0:[0-9]+]] { 10; CHECK-NEXT: [[ENTRY:.*]]: 11; CHECK-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] 12; CHECK: [[VECTOR_PH]]: 13; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] 14; CHECK: [[VECTOR_BODY]]: 15; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] 16; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <16 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP13:%.*]], %[[VECTOR_BODY]] ] 17; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <16 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP14:%.*]], %[[VECTOR_BODY]] ] 18; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 19; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[A]], i64 [[TMP0]] 20; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 0 21; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[TMP1]], i32 16 22; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <16 x i8>, ptr [[TMP2]], align 1 23; CHECK-NEXT: [[WIDE_LOAD2:%.*]] = load <16 x i8>, ptr [[TMP3]], align 1 24; CHECK-NEXT: [[TMP4:%.*]] = zext <16 x i8> [[WIDE_LOAD]] to <16 x i32> 25; CHECK-NEXT: [[TMP5:%.*]] = zext <16 x i8> [[WIDE_LOAD2]] to <16 x i32> 26; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[B]], i64 [[TMP0]] 27; CHECK-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[TMP6]], i32 0 28; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[TMP6]], i32 16 29; CHECK-NEXT: [[WIDE_LOAD3:%.*]] = load <16 x i8>, ptr [[TMP7]], align 1 30; CHECK-NEXT: [[WIDE_LOAD4:%.*]] = load <16 x i8>, ptr [[TMP8]], align 1 31; CHECK-NEXT: [[TMP9:%.*]] = zext <16 x i8> [[WIDE_LOAD3]] to <16 x i32> 32; CHECK-NEXT: [[TMP10:%.*]] = zext <16 x i8> [[WIDE_LOAD4]] to <16 x i32> 33; CHECK-NEXT: [[TMP11:%.*]] = mul <16 x i32> [[TMP9]], [[TMP4]] 34; CHECK-NEXT: [[TMP12:%.*]] = mul <16 x i32> [[TMP10]], [[TMP5]] 35; CHECK-NEXT: [[TMP13]] = add <16 x i32> [[TMP11]], [[VEC_PHI]] 36; CHECK-NEXT: [[TMP14]] = add <16 x i32> [[TMP12]], [[VEC_PHI1]] 37; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 32 38; CHECK-NEXT: [[TMP15:%.*]] = icmp eq i64 [[INDEX_NEXT]], 992 39; CHECK-NEXT: br i1 [[TMP15]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] 40; 41entry: 42 br label %for.body 43 44for.body: ; preds = %for.body, %entry 45 %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ] 46 %accum = phi i32 [ 0, %entry ], [ %add, %for.body ] 47 %gep.a = getelementptr i8, ptr %a, i64 %iv 48 %load.a = load i8, ptr %gep.a, align 1 49 %ext.a = zext i8 %load.a to i32 50 %gep.b = getelementptr i8, ptr %b, i64 %iv 51 %load.b = load i8, ptr %gep.b, align 1 52 %ext.b = zext i8 %load.b to i32 53 %mul = mul i32 %ext.b, %ext.a 54 %add = add i32 %mul, %accum 55 %iv.next = add i64 %iv, 1 56 %exitcond.not = icmp eq i64 %iv.next, 1000 57 br i1 %exitcond.not, label %for.exit, label %for.body 58 59for.exit: ; preds = %for.body 60 ret i32 %add 61} 62