xref: /llvm-project/llvm/test/Transforms/ArgumentPromotion/X86/attributes.ll (revision bcbc6151640f53e9d78392c66de9760c664d8b1d)
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --scrub-attributes
2; RUN: opt -S -passes=argpromotion < %s | FileCheck %s
3; Test that we only promote arguments when the caller/callee have compatible
4; function attrubtes.
5
6target triple = "x86_64-unknown-linux-gnu"
7
8define internal fastcc void @no_promote_avx2(ptr %arg, ptr readonly %arg1) #0 {
9; CHECK-LABEL: define {{[^@]+}}@no_promote_avx2
10; CHECK-SAME: (ptr [[ARG:%.*]], ptr readonly [[ARG1:%.*]])
11; CHECK-NEXT:  bb:
12; CHECK-NEXT:    [[TMP:%.*]] = load <4 x i64>, ptr [[ARG1]]
13; CHECK-NEXT:    store <4 x i64> [[TMP]], ptr [[ARG]]
14; CHECK-NEXT:    ret void
15;
16bb:
17  %tmp = load <4 x i64>, ptr %arg1
18  store <4 x i64> %tmp, ptr %arg
19  ret void
20}
21
22define void @no_promote(ptr %arg) #1 {
23; CHECK-LABEL: define {{[^@]+}}@no_promote
24; CHECK-SAME: (ptr [[ARG:%.*]])
25; CHECK-NEXT:  bb:
26; CHECK-NEXT:    [[TMP:%.*]] = alloca <4 x i64>, align 32
27; CHECK-NEXT:    [[TMP2:%.*]] = alloca <4 x i64>, align 32
28; CHECK-NEXT:    call void @llvm.memset.p0.i64(ptr align 32 [[TMP]], i8 0, i64 32, i1 false)
29; CHECK-NEXT:    call fastcc void @no_promote_avx2(ptr [[TMP2]], ptr [[TMP]])
30; CHECK-NEXT:    [[TMP4:%.*]] = load <4 x i64>, ptr [[TMP2]], align 32
31; CHECK-NEXT:    store <4 x i64> [[TMP4]], ptr [[ARG]], align 2
32; CHECK-NEXT:    ret void
33;
34bb:
35  %tmp = alloca <4 x i64>, align 32
36  %tmp2 = alloca <4 x i64>, align 32
37  call void @llvm.memset.p0.i64(ptr align 32 %tmp, i8 0, i64 32, i1 false)
38  call fastcc void @no_promote_avx2(ptr %tmp2, ptr %tmp)
39  %tmp4 = load <4 x i64>, ptr %tmp2, align 32
40  store <4 x i64> %tmp4, ptr %arg, align 2
41  ret void
42}
43
44define internal fastcc void @promote_avx2(ptr %arg, ptr readonly %arg1) #0 {
45; CHECK-LABEL: define {{[^@]+}}@promote_avx2
46; CHECK-SAME: (ptr [[ARG:%.*]], <4 x i64> [[ARG1_VAL:%.*]])
47; CHECK-NEXT:  bb:
48; CHECK-NEXT:    store <4 x i64> [[ARG1_VAL]], ptr [[ARG]]
49; CHECK-NEXT:    ret void
50;
51bb:
52  %tmp = load <4 x i64>, ptr %arg1
53  store <4 x i64> %tmp, ptr %arg
54  ret void
55}
56
57define void @promote(ptr %arg) #0 {
58; CHECK-LABEL: define {{[^@]+}}@promote
59; CHECK-SAME: (ptr [[ARG:%.*]])
60; CHECK-NEXT:  bb:
61; CHECK-NEXT:    [[TMP:%.*]] = alloca <4 x i64>, align 32
62; CHECK-NEXT:    [[TMP2:%.*]] = alloca <4 x i64>, align 32
63; CHECK-NEXT:    call void @llvm.memset.p0.i64(ptr align 32 [[TMP]], i8 0, i64 32, i1 false)
64; CHECK-NEXT:    [[TMP_VAL:%.*]] = load <4 x i64>, ptr [[TMP]]
65; CHECK-NEXT:    call fastcc void @promote_avx2(ptr [[TMP2]], <4 x i64> [[TMP_VAL]])
66; CHECK-NEXT:    [[TMP4:%.*]] = load <4 x i64>, ptr [[TMP2]], align 32
67; CHECK-NEXT:    store <4 x i64> [[TMP4]], ptr [[ARG]], align 2
68; CHECK-NEXT:    ret void
69;
70bb:
71  %tmp = alloca <4 x i64>, align 32
72  %tmp2 = alloca <4 x i64>, align 32
73  call void @llvm.memset.p0.i64(ptr align 32 %tmp, i8 0, i64 32, i1 false)
74  call fastcc void @promote_avx2(ptr %tmp2, ptr %tmp)
75  %tmp4 = load <4 x i64>, ptr %tmp2, align 32
76  store <4 x i64> %tmp4, ptr %arg, align 2
77  ret void
78}
79
80; Function Attrs: argmemonly nounwind
81declare void @llvm.memset.p0.i64(ptr nocapture writeonly, i8, i64, i1) #2
82
83attributes #0 = { inlinehint norecurse nounwind uwtable "target-features"="+avx2" }
84attributes #1 = { nounwind uwtable }
85attributes #2 = { argmemonly nounwind }
86