1; RUN: opt < %s -msan-check-access-address=0 -S -passes=msan 2>&1 | FileCheck %s 2; REQUIRES: x86-registered-target 3 4; Test instrumentation of vector shift instructions. 5 6target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" 7target triple = "x86_64-unknown-linux-gnu" 8 9declare <1 x i64> @llvm.x86.mmx.psll.d(<1 x i64>, <1 x i64>) 10declare <16 x i32> @llvm.x86.avx512.psllv.d.512(<16 x i32>, <16 x i32>) 11declare <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32>, <8 x i32>) 12declare <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32>, <4 x i32>) 13declare <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16>, <8 x i16>) 14declare <32 x i16> @llvm.x86.avx512.psrl.w.512(<32 x i16>, <8 x i16>) 15declare <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16>, i32) 16declare <32 x i16> @llvm.x86.avx512.pslli.w.512(<32 x i16>, i32) 17 18define i64 @test_mmx(i64 %x.coerce, i64 %y.coerce) sanitize_memory { 19entry: 20 %0 = bitcast i64 %x.coerce to <2 x i32> 21 %1 = bitcast <2 x i32> %0 to <1 x i64> 22 %2 = bitcast i64 %y.coerce to <1 x i64> 23 %3 = tail call <1 x i64> @llvm.x86.mmx.psll.d(<1 x i64> %1, <1 x i64> %2) 24 %4 = bitcast <1 x i64> %3 to <2 x i32> 25 %5 = bitcast <2 x i32> %4 to <1 x i64> 26 %6 = extractelement <1 x i64> %5, i32 0 27 ret i64 %6 28} 29 30; CHECK-LABEL: @test_mmx 31; CHECK: = icmp ne i64 {{.*}}, 0 32; CHECK: [[B:%.*]] = sext i1 {{.*}} to i64 33; CHECK: [[C:%.*]] = bitcast i64 [[B]] to <1 x i64> 34; CHECK: [[A:%.*]] = call <1 x i64> @llvm.x86.mmx.psll.d( 35; CHECK: = or <1 x i64> {{.*}}[[A]], {{.*}}[[C]] 36; CHECK: call <1 x i64> @llvm.x86.mmx.psll.d( 37; CHECK: ret i64 38 39 40define <8 x i16> @test_sse2_scalar(<8 x i16> %x, i32 %y) sanitize_memory { 41entry: 42 %0 = tail call <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16> %x, i32 %y) 43 ret <8 x i16> %0 44} 45 46; CHECK-LABEL: @test_sse2_scalar 47; CHECK: = icmp ne i32 {{.*}}, 0 48; CHECK: = sext i1 {{.*}} to i128 49; CHECK: = bitcast i128 {{.*}} to <8 x i16> 50; CHECK: = call <8 x i16> @llvm.x86.sse2.pslli.w( 51; CHECK: = or <8 x i16> 52; CHECK: call <8 x i16> @llvm.x86.sse2.pslli.w( 53; CHECK: ret <8 x i16> 54 55 56define <32 x i16> @test_avx512_scalar(<32 x i16> %x, i32 %y) sanitize_memory { 57entry: 58 %0 = tail call <32 x i16> @llvm.x86.avx512.pslli.w.512(<32 x i16> %x, i32 %y) 59 ret <32 x i16> %0 60} 61 62; CHECK-LABEL: @test_avx512_scalar 63; CHECK: = icmp ne i32 {{.*}}, 0 64; CHECK: = sext i1 {{.*}} to i512 65; CHECK: = bitcast i512 {{.*}} to <32 x i16> 66; CHECK: = call <32 x i16> @llvm.x86.avx512.pslli.w.512( 67; CHECK: = or <32 x i16> 68; CHECK: call <32 x i16> @llvm.x86.avx512.pslli.w.512( 69; CHECK: ret <32 x i16> 70 71 72define <8 x i16> @test_sse2(<8 x i16> %x, <8 x i16> %y) sanitize_memory { 73entry: 74 %0 = tail call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> %x, <8 x i16> %y) 75 ret <8 x i16> %0 76} 77 78; CHECK-LABEL: @test_sse2 79; CHECK: = bitcast <8 x i16> {{.*}} to i128 80; CHECK: = trunc i128 {{.*}} to i64 81; CHECK: = icmp ne i64 {{.*}}, 0 82; CHECK: = sext i1 {{.*}} to i128 83; CHECK: = bitcast i128 {{.*}} to <8 x i16> 84; CHECK: = call <8 x i16> @llvm.x86.sse2.psrl.w( 85; CHECK: = or <8 x i16> 86; CHECK: call <8 x i16> @llvm.x86.sse2.psrl.w( 87; CHECK: ret <8 x i16> 88 89 90define <32 x i16> @test_avx512(<32 x i16> %x, <8 x i16> %y) sanitize_memory { 91entry: 92 %0 = tail call <32 x i16> @llvm.x86.avx512.psrl.w.512(<32 x i16> %x, <8 x i16> %y) 93 ret <32 x i16> %0 94} 95 96; CHECK-LABEL: @test_avx512 97; CHECK: = bitcast <8 x i16> {{.*}} to i128 98; CHECK: = trunc i128 {{.*}} to i64 99; CHECK: = icmp ne i64 {{.*}}, 0 100; CHECK: = sext i1 {{.*}} to i512 101; CHECK: = bitcast i512 {{.*}} to <32 x i16> 102; CHECK: = call <32 x i16> @llvm.x86.avx512.psrl.w.512( 103; CHECK: = or <32 x i16> 104; CHECK: call <32 x i16> @llvm.x86.avx512.psrl.w.512( 105; CHECK: ret <32 x i16> 106 107 108; Test variable shift (i.e. vector by vector). 109 110define <4 x i32> @test_avx2(<4 x i32> %x, <4 x i32> %y) sanitize_memory { 111entry: 112 %0 = tail call <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32> %x, <4 x i32> %y) 113 ret <4 x i32> %0 114} 115 116; CHECK-LABEL: @test_avx2 117; CHECK: = icmp ne <4 x i32> {{.*}}, zeroinitializer 118; CHECK: = sext <4 x i1> {{.*}} to <4 x i32> 119; CHECK: = call <4 x i32> @llvm.x86.avx2.psllv.d( 120; CHECK: = or <4 x i32> 121; CHECK: = tail call <4 x i32> @llvm.x86.avx2.psllv.d( 122; CHECK: ret <4 x i32> 123 124define <8 x i32> @test_avx2_256(<8 x i32> %x, <8 x i32> %y) sanitize_memory { 125entry: 126 %0 = tail call <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32> %x, <8 x i32> %y) 127 ret <8 x i32> %0 128} 129 130; CHECK-LABEL: @test_avx2_256 131; CHECK: = icmp ne <8 x i32> {{.*}}, zeroinitializer 132; CHECK: = sext <8 x i1> {{.*}} to <8 x i32> 133; CHECK: = call <8 x i32> @llvm.x86.avx2.psllv.d.256( 134; CHECK: = or <8 x i32> 135; CHECK: = tail call <8 x i32> @llvm.x86.avx2.psllv.d.256( 136; CHECK: ret <8 x i32> 137 138define <16 x i32> @test_avx512_512(<16 x i32> %x, <16 x i32> %y) sanitize_memory { 139entry: 140 %0 = tail call <16 x i32> @llvm.x86.avx512.psllv.d.512(<16 x i32> %x, <16 x i32> %y) 141 ret <16 x i32> %0 142} 143 144; CHECK-LABEL: @test_avx512_512 145; CHECK: = icmp ne <16 x i32> {{.*}}, zeroinitializer 146; CHECK: = sext <16 x i1> {{.*}} to <16 x i32> 147; CHECK: = call <16 x i32> @llvm.x86.avx512.psllv.d.512( 148; CHECK: = or <16 x i32> 149; CHECK: = tail call <16 x i32> @llvm.x86.avx512.psllv.d.512( 150; CHECK: ret <16 x i32> 151