1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 2; RUN: opt < %s -msan-check-access-address=0 -msan-track-origins=1 -S -passes='module(msan)' 2>&1 | FileCheck -allow-deprecated-dag-overlap --check-prefix=CHECK %s 3 4target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" 5target triple = "x86_64-unknown-linux-gnu" 6 7declare i32 @llvm.vector.reduce.add(<3 x i32>) 8declare i32 @llvm.vector.reduce.and(<3 x i32>) 9declare i32 @llvm.vector.reduce.or(<3 x i32>) 10 11define i32 @reduce_add() sanitize_memory { 12; CHECK-LABEL: define i32 @reduce_add( 13; CHECK-SAME: ) #[[ATTR0:[0-9]+]] { 14; CHECK-NEXT: call void @llvm.donothing() 15; CHECK-NEXT: [[P:%.*]] = inttoptr i64 0 to ptr 16; CHECK-NEXT: [[O:%.*]] = load <3 x i32>, ptr [[P]], align 16 17; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64 18; CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080 19; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr 20; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[TMP2]], 17592186044416 21; CHECK-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr 22; CHECK-NEXT: [[_MSLD:%.*]] = load <3 x i32>, ptr [[TMP3]], align 16 23; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 16 24; CHECK-NEXT: [[TMP7:%.*]] = call i32 @llvm.vector.reduce.or.v3i32(<3 x i32> [[_MSLD]]) 25; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.vector.reduce.add.v3i32(<3 x i32> [[O]]) 26; CHECK-NEXT: store i32 [[TMP7]], ptr @__msan_retval_tls, align 8 27; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_origin_tls, align 4 28; CHECK-NEXT: ret i32 [[R]] 29; 30 %p = inttoptr i64 0 to ptr 31 %o = load <3 x i32>, ptr %p 32 %r = call i32 @llvm.vector.reduce.add(<3 x i32> %o) 33 ret i32 %r 34} 35 36define i32 @reduce_and() sanitize_memory { 37; CHECK-LABEL: define i32 @reduce_and( 38; CHECK-SAME: ) #[[ATTR0]] { 39; CHECK-NEXT: call void @llvm.donothing() 40; CHECK-NEXT: [[P:%.*]] = inttoptr i64 0 to ptr 41; CHECK-NEXT: [[O:%.*]] = load <3 x i32>, ptr [[P]], align 16 42; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64 43; CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080 44; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr 45; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[TMP2]], 17592186044416 46; CHECK-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr 47; CHECK-NEXT: [[_MSLD:%.*]] = load <3 x i32>, ptr [[TMP3]], align 16 48; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 16 49; CHECK-NEXT: [[TMP7:%.*]] = or <3 x i32> [[O]], [[_MSLD]] 50; CHECK-NEXT: [[TMP8:%.*]] = call i32 @llvm.vector.reduce.and.v3i32(<3 x i32> [[TMP7]]) 51; CHECK-NEXT: [[TMP9:%.*]] = call i32 @llvm.vector.reduce.or.v3i32(<3 x i32> [[_MSLD]]) 52; CHECK-NEXT: [[TMP10:%.*]] = and i32 [[TMP8]], [[TMP9]] 53; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.vector.reduce.and.v3i32(<3 x i32> [[O]]) 54; CHECK-NEXT: store i32 [[TMP10]], ptr @__msan_retval_tls, align 8 55; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_origin_tls, align 4 56; CHECK-NEXT: ret i32 [[R]] 57; 58 %p = inttoptr i64 0 to ptr 59 %o = load <3 x i32>, ptr %p 60 %r = call i32 @llvm.vector.reduce.and(<3 x i32> %o) 61 ret i32 %r 62} 63 64define i32 @reduce_or() sanitize_memory { 65; CHECK-LABEL: define i32 @reduce_or( 66; CHECK-SAME: ) #[[ATTR0]] { 67; CHECK-NEXT: call void @llvm.donothing() 68; CHECK-NEXT: [[P:%.*]] = inttoptr i64 0 to ptr 69; CHECK-NEXT: [[O:%.*]] = load <3 x i32>, ptr [[P]], align 16 70; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64 71; CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080 72; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr 73; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[TMP2]], 17592186044416 74; CHECK-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr 75; CHECK-NEXT: [[_MSLD:%.*]] = load <3 x i32>, ptr [[TMP3]], align 16 76; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 16 77; CHECK-NEXT: [[TMP7:%.*]] = xor <3 x i32> [[O]], splat (i32 -1) 78; CHECK-NEXT: [[TMP8:%.*]] = or <3 x i32> [[TMP7]], [[_MSLD]] 79; CHECK-NEXT: [[TMP9:%.*]] = call i32 @llvm.vector.reduce.and.v3i32(<3 x i32> [[TMP8]]) 80; CHECK-NEXT: [[TMP10:%.*]] = call i32 @llvm.vector.reduce.or.v3i32(<3 x i32> [[_MSLD]]) 81; CHECK-NEXT: [[TMP11:%.*]] = and i32 [[TMP9]], [[TMP10]] 82; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.vector.reduce.or.v3i32(<3 x i32> [[O]]) 83; CHECK-NEXT: store i32 [[TMP11]], ptr @__msan_retval_tls, align 8 84; CHECK-NEXT: store i32 [[TMP6]], ptr @__msan_retval_origin_tls, align 4 85; CHECK-NEXT: ret i32 [[R]] 86; 87 %p = inttoptr i64 0 to ptr 88 %o = load <3 x i32>, ptr %p 89 %r = call i32 @llvm.vector.reduce.or(<3 x i32> %o) 90 ret i32 %r 91} 92