1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt < %s -passes='module(msan)' -msan-instrumentation-with-call-threshold=0 -msan-track-origins=1 -S | FileCheck %s 3 4target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" 5target triple = "x86_64-unknown-linux-gnu" 6 7!llvm.module.flags = !{!0} 8 9!0 = !{i32 2, !"Debug Info Version", i32 3} 10!2 = distinct !DISubprogram(name: "t", scope: !3, file: !3, line: 4, type: !4, spFlags: DISPFlagDefinition, unit: !6) 11!3 = !DIFile(filename: "tmp/noundef.cpp", directory: "/") 12!4 = !DISubroutineType(types: !5) 13!5 = !{} 14!6 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !3, isOptimized: false, runtimeVersion: 0, emissionKind: NoDebug) 15!10 = !DILocation(line: 9, column: 0, scope: !2) 16!11 = !DILocation(line: 9, column: 1, scope: !2) 17!12 = !DILocation(line: 9, column: 2, scope: !2) 18!13 = !DILocation(line: 9, column: 3, scope: !2) 19!14 = !DILocation(line: 9, column: 4, scope: !2) 20!15 = !DILocation(line: 9, column: 5, scope: !2) 21 22define void @Store(ptr nocapture %p, i32 %x) nounwind uwtable sanitize_memory { 23; CHECK-LABEL: @Store( 24; CHECK-NEXT: entry: 25; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__msan_param_tls, align 8, !dbg [[DBG1:![0-9]+]] 26; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4, !dbg [[DBG1]] 27; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8, !dbg [[DBG1]] 28; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_origin_tls to i64), i64 8) to ptr), align 4, !dbg [[DBG1]] 29; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] 30; CHECK-NEXT: call void @__msan_maybe_warning_8(i64 zeroext [[TMP0]], i32 zeroext [[TMP1]]), !dbg [[DBG1]] 31; CHECK-NEXT: [[TMP4:%.*]] = ptrtoint ptr [[P:%.*]] to i64, !dbg [[DBG1]] 32; CHECK-NEXT: [[TMP5:%.*]] = xor i64 [[TMP4]], 87960930222080, !dbg [[DBG1]] 33; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr, !dbg [[DBG1]] 34; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[TMP5]], 17592186044416, !dbg [[DBG1]] 35; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr, !dbg [[DBG1]] 36; CHECK-NEXT: store i32 [[TMP2]], ptr [[TMP6]], align 4, !dbg [[DBG1]] 37; CHECK-NEXT: call void @__msan_maybe_store_origin_4(i32 zeroext [[TMP2]], ptr [[P]], i32 zeroext [[TMP3]]), !dbg [[DBG1]] 38; CHECK-NEXT: store i32 [[X:%.*]], ptr [[P]], align 4, !dbg [[DBG1]] 39; CHECK-NEXT: ret void 40; 41entry: 42 store i32 %x, ptr %p, align 4, !dbg !10 43 ret void 44} 45 46define void @LoadAndCmp(ptr nocapture %a) nounwind uwtable sanitize_memory { 47; CHECK-LABEL: @LoadAndCmp( 48; CHECK-NEXT: entry: 49; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__msan_param_tls, align 8, !dbg [[DBG1]] 50; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4, !dbg [[DBG1]] 51; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] 52; CHECK-NEXT: call void @__msan_maybe_warning_8(i64 zeroext [[TMP0]], i32 zeroext [[TMP1]]), !dbg [[DBG1]] 53; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A:%.*]], align 4, !dbg [[DBG1]] 54; CHECK-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[A]] to i64, !dbg [[DBG1]] 55; CHECK-NEXT: [[TMP4:%.*]] = xor i64 [[TMP3]], 87960930222080, !dbg [[DBG1]] 56; CHECK-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr, !dbg [[DBG1]] 57; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[TMP4]], 17592186044416, !dbg [[DBG1]] 58; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr, !dbg [[DBG1]] 59; CHECK-NEXT: [[_MSLD:%.*]] = load i32, ptr [[TMP5]], align 4, !dbg [[DBG1]] 60; CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4, !dbg [[DBG1]] 61; CHECK-NEXT: [[TMP9:%.*]] = xor i32 [[TMP2]], 0, !dbg [[DBG7:![0-9]+]] 62; CHECK-NEXT: [[TMP10:%.*]] = or i32 [[_MSLD]], 0, !dbg [[DBG7]] 63; CHECK-NEXT: [[TMP11:%.*]] = icmp ne i32 [[TMP10]], 0, !dbg [[DBG7]] 64; CHECK-NEXT: [[TMP12:%.*]] = xor i32 [[TMP10]], -1, !dbg [[DBG7]] 65; CHECK-NEXT: [[TMP13:%.*]] = and i32 [[TMP12]], [[TMP9]], !dbg [[DBG7]] 66; CHECK-NEXT: [[TMP14:%.*]] = icmp eq i32 [[TMP13]], 0, !dbg [[DBG7]] 67; CHECK-NEXT: [[_MSPROP_ICMP:%.*]] = and i1 [[TMP11]], [[TMP14]], !dbg [[DBG7]] 68; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i32 [[TMP2]], 0, !dbg [[DBG7]] 69; CHECK-NEXT: [[TMP15:%.*]] = zext i1 [[_MSPROP_ICMP]] to i8, !dbg [[DBG8:![0-9]+]] 70; CHECK-NEXT: call void @__msan_maybe_warning_1(i8 zeroext [[TMP15]], i32 zeroext [[TMP8]]), !dbg [[DBG8]] 71; CHECK-NEXT: br i1 [[TOBOOL]], label [[IF_END:%.*]], label [[IF_THEN:%.*]], !dbg [[DBG8]] 72; CHECK: if.then: 73; CHECK-NEXT: store i64 0, ptr @__msan_va_arg_overflow_size_tls, align 8 74; CHECK-NEXT: tail call void (...) @foo() #[[ATTR5:[0-9]+]] 75; CHECK-NEXT: br label [[IF_END]] 76; CHECK: if.end: 77; CHECK-NEXT: ret void 78; 79entry: 80 %0 = load i32, ptr %a, align 4, !dbg !10 81 %tobool = icmp eq i32 %0, 0, !dbg !11 82 br i1 %tobool, label %if.end, label %if.then, !dbg !12 83 84if.then: tail call void (...) @foo() nounwind 85 br label %if.end 86 87if.end: ret void 88} 89 90declare void @foo(...) 91 92define i32 @ReturnInt() nounwind uwtable readnone sanitize_memory { 93; CHECK-LABEL: @ReturnInt( 94; CHECK-NEXT: entry: 95; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] 96; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8, !dbg [[DBG1]] 97; CHECK-NEXT: store i32 0, ptr @__msan_retval_origin_tls, align 4, !dbg [[DBG1]] 98; CHECK-NEXT: ret i32 123, !dbg [[DBG1]] 99; 100entry: 101 ret i32 123, !dbg !10 102} 103 104define void @CopyRetVal(ptr nocapture %a) nounwind uwtable sanitize_memory { 105; CHECK-LABEL: @CopyRetVal( 106; CHECK-NEXT: entry: 107; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__msan_param_tls, align 8, !dbg [[DBG1]] 108; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4, !dbg [[DBG1]] 109; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] 110; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8, !dbg [[DBG1]] 111; CHECK-NEXT: [[CALL:%.*]] = tail call i32 @ReturnInt() #[[ATTR5]], !dbg [[DBG1]] 112; CHECK-NEXT: [[_MSRET:%.*]] = load i32, ptr @__msan_retval_tls, align 8, !dbg [[DBG7]] 113; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_retval_origin_tls, align 4, !dbg [[DBG7]] 114; CHECK-NEXT: call void @__msan_maybe_warning_8(i64 zeroext [[TMP0]], i32 zeroext [[TMP1]]), !dbg [[DBG7]] 115; CHECK-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[A:%.*]] to i64, !dbg [[DBG7]] 116; CHECK-NEXT: [[TMP4:%.*]] = xor i64 [[TMP3]], 87960930222080, !dbg [[DBG7]] 117; CHECK-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr, !dbg [[DBG7]] 118; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[TMP4]], 17592186044416, !dbg [[DBG7]] 119; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr, !dbg [[DBG7]] 120; CHECK-NEXT: store i32 [[_MSRET]], ptr [[TMP5]], align 4, !dbg [[DBG7]] 121; CHECK-NEXT: call void @__msan_maybe_store_origin_4(i32 zeroext [[_MSRET]], ptr [[A]], i32 zeroext [[TMP2]]), !dbg [[DBG7]] 122; CHECK-NEXT: store i32 [[CALL]], ptr [[A]], align 4, !dbg [[DBG7]] 123; CHECK-NEXT: ret void 124; 125entry: 126 %call = tail call i32 @ReturnInt() nounwind, !dbg !10 127 store i32 %call, ptr %a, align 4, !dbg !11 128 ret void 129} 130 131 132 133define void @SExt(ptr nocapture %a, ptr nocapture %b) nounwind uwtable sanitize_memory { 134; CHECK-LABEL: @SExt( 135; CHECK-NEXT: entry: 136; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8, !dbg [[DBG1]] 137; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_origin_tls to i64), i64 8) to ptr), align 4, !dbg [[DBG1]] 138; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr @__msan_param_tls, align 8, !dbg [[DBG1]] 139; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4, !dbg [[DBG1]] 140; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] 141; CHECK-NEXT: call void @__msan_maybe_warning_8(i64 zeroext [[TMP0]], i32 zeroext [[TMP1]]), !dbg [[DBG1]] 142; CHECK-NEXT: [[TMP4:%.*]] = load i16, ptr [[B:%.*]], align 2, !dbg [[DBG1]] 143; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[B]] to i64, !dbg [[DBG1]] 144; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 87960930222080, !dbg [[DBG1]] 145; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr, !dbg [[DBG1]] 146; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[TMP6]], 17592186044416, !dbg [[DBG1]] 147; CHECK-NEXT: [[TMP9:%.*]] = and i64 [[TMP8]], -4, !dbg [[DBG1]] 148; CHECK-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP9]] to ptr, !dbg [[DBG1]] 149; CHECK-NEXT: [[_MSLD:%.*]] = load i16, ptr [[TMP7]], align 2, !dbg [[DBG1]] 150; CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP10]], align 4, !dbg [[DBG1]] 151; CHECK-NEXT: [[_MSPROP:%.*]] = sext i16 [[_MSLD]] to i32, !dbg [[DBG7]] 152; CHECK-NEXT: [[TMP12:%.*]] = sext i16 [[TMP4]] to i32, !dbg [[DBG7]] 153; CHECK-NEXT: call void @__msan_maybe_warning_8(i64 zeroext [[TMP2]], i32 zeroext [[TMP3]]), !dbg [[DBG8]] 154; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[A:%.*]] to i64, !dbg [[DBG8]] 155; CHECK-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], 87960930222080, !dbg [[DBG8]] 156; CHECK-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP14]] to ptr, !dbg [[DBG8]] 157; CHECK-NEXT: [[TMP16:%.*]] = add i64 [[TMP14]], 17592186044416, !dbg [[DBG8]] 158; CHECK-NEXT: [[TMP17:%.*]] = inttoptr i64 [[TMP16]] to ptr, !dbg [[DBG8]] 159; CHECK-NEXT: store i32 [[_MSPROP]], ptr [[TMP15]], align 4, !dbg [[DBG8]] 160; CHECK-NEXT: call void @__msan_maybe_store_origin_4(i32 zeroext [[_MSPROP]], ptr [[A]], i32 zeroext [[TMP11]]), !dbg [[DBG8]] 161; CHECK-NEXT: store i32 [[TMP12]], ptr [[A]], align 4, !dbg [[DBG8]] 162; CHECK-NEXT: ret void 163; 164entry: 165 %0 = load i16, ptr %b, align 2, !dbg !10 166 %1 = sext i16 %0 to i32, !dbg !11 167 store i32 %1, ptr %a, align 4, !dbg !12 168 ret void 169} 170 171define void @MemSet(ptr nocapture %x) nounwind uwtable sanitize_memory { 172; CHECK-LABEL: @MemSet( 173; CHECK-NEXT: entry: 174; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] 175; CHECK-NEXT: [[TMP0:%.*]] = call ptr @__msan_memset(ptr [[X:%.*]], i32 42, i64 10), !dbg [[DBG1]] 176; CHECK-NEXT: ret void 177; 178entry: 179 call void @llvm.memset.p0.i64(ptr %x, i8 42, i64 10, i1 false), !dbg !10 180 ret void 181} 182 183declare void @llvm.memset.p0.i64(ptr nocapture, i8, i64, i1) nounwind 184 185 186 187define void @MemCpy(ptr nocapture %x, ptr nocapture %y) nounwind uwtable sanitize_memory { 188; CHECK-LABEL: @MemCpy( 189; CHECK-NEXT: entry: 190; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8, !dbg [[DBG1]] 191; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_origin_tls to i64), i64 8) to ptr), align 4, !dbg [[DBG1]] 192; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] 193; CHECK-NEXT: [[TMP2:%.*]] = call ptr @__msan_memcpy(ptr [[X:%.*]], ptr [[Y:%.*]], i64 10), !dbg [[DBG1]] 194; CHECK-NEXT: ret void 195; 196entry: 197 call void @llvm.memcpy.p0.p0.i64(ptr %x, ptr %y, i64 10, i1 false), !dbg !10 198 ret void 199} 200 201declare void @llvm.memcpy.p0.p0.i64(ptr nocapture, ptr nocapture, i64, i1) nounwind 202 203 204define void @MemSetInline(ptr nocapture %x) nounwind uwtable sanitize_memory { 205; CHECK-LABEL: @MemSetInline( 206; CHECK-NEXT: entry: 207; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] 208; CHECK-NEXT: [[TMP0:%.*]] = call ptr @__msan_memset(ptr [[X:%.*]], i32 42, i64 10), !dbg [[DBG1]] 209; CHECK-NEXT: ret void 210; 211entry: 212 call void @llvm.memset.inline.p0.i64(ptr %x, i8 42, i64 10, i1 false), !dbg !10 213 ret void 214} 215 216declare void @llvm.memset.inline.p0.i64(ptr nocapture, i8, i64, i1) nounwind 217 218 219define void @MemCpyInline(ptr nocapture %x, ptr nocapture %y) nounwind uwtable sanitize_memory { 220; CHECK-LABEL: @MemCpyInline( 221; CHECK-NEXT: entry: 222; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8, !dbg [[DBG1]] 223; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_origin_tls to i64), i64 8) to ptr), align 4, !dbg [[DBG1]] 224; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] 225; CHECK-NEXT: [[TMP2:%.*]] = call ptr @__msan_memcpy(ptr [[X:%.*]], ptr [[Y:%.*]], i64 10), !dbg [[DBG1]] 226; CHECK-NEXT: ret void 227; 228entry: 229 call void @llvm.memcpy.inline.p0.p0.i64(ptr %x, ptr %y, i64 10, i1 false), !dbg !10 230 ret void 231} 232 233declare void @llvm.memcpy.inline.p0.p0.i64(ptr nocapture, ptr nocapture, i64, i1) nounwind 234 235 236define void @MemMove(ptr nocapture %x, ptr nocapture %y) nounwind uwtable sanitize_memory { 237; CHECK-LABEL: @MemMove( 238; CHECK-NEXT: entry: 239; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8, !dbg [[DBG1]] 240; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_origin_tls to i64), i64 8) to ptr), align 4, !dbg [[DBG1]] 241; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] 242; CHECK-NEXT: [[TMP2:%.*]] = call ptr @__msan_memmove(ptr [[X:%.*]], ptr [[Y:%.*]], i64 10), !dbg [[DBG1]] 243; CHECK-NEXT: ret void 244; 245entry: 246 call void @llvm.memmove.p0.p0.i64(ptr %x, ptr %y, i64 10, i1 false), !dbg !10 247 ret void 248} 249 250declare void @llvm.memmove.p0.p0.i64(ptr nocapture, ptr nocapture, i64, i1) nounwind 251 252 253declare void @llvm.memset.element.unordered.atomic.p0.i64(ptr nocapture writeonly, i8, i64, i32) nounwind 254declare void @llvm.memmove.element.unordered.atomic.p0.p0.i64(ptr nocapture writeonly, ptr nocapture readonly, i64, i32) nounwind 255declare void @llvm.memcpy.element.unordered.atomic.p0.p0.i64(ptr nocapture writeonly, ptr nocapture readonly, i64, i32) nounwind 256 257define void @atomic_memcpy(ptr nocapture %x, ptr nocapture %y) nounwind { 258; CHECK-LABEL: @atomic_memcpy( 259; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] 260; CHECK-NEXT: call void @llvm.memcpy.element.unordered.atomic.p0.p0.i64(ptr align 1 [[X:%.*]], ptr align 2 [[Y:%.*]], i64 16, i32 1), !dbg [[DBG1]] 261; CHECK-NEXT: ret void 262; 263 call void @llvm.memcpy.element.unordered.atomic.p0.p0.i64(ptr align 1 %x, ptr align 2 %y, i64 16, i32 1), !dbg !10 264 ret void 265} 266 267define void @atomic_memmove(ptr nocapture %x, ptr nocapture %y) nounwind { 268; CHECK-LABEL: @atomic_memmove( 269; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] 270; CHECK-NEXT: call void @llvm.memmove.element.unordered.atomic.p0.p0.i64(ptr align 1 [[X:%.*]], ptr align 2 [[Y:%.*]], i64 16, i32 1), !dbg [[DBG1]] 271; CHECK-NEXT: ret void 272; 273 call void @llvm.memmove.element.unordered.atomic.p0.p0.i64(ptr align 1 %x, ptr align 2 %y, i64 16, i32 1), !dbg !10 274 ret void 275} 276 277define void @atomic_memset(ptr nocapture %x) nounwind { 278; CHECK-LABEL: @atomic_memset( 279; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] 280; CHECK-NEXT: call void @llvm.memset.element.unordered.atomic.p0.i64(ptr align 1 [[X:%.*]], i8 88, i64 16, i32 1), !dbg [[DBG1]] 281; CHECK-NEXT: ret void 282; 283 call void @llvm.memset.element.unordered.atomic.p0.i64(ptr align 1 %x, i8 88, i64 16, i32 1), !dbg !10 284 ret void 285} 286 287 288 289 290define i32 @Select(i32 %a, i32 %b, i1 %c) nounwind uwtable readnone sanitize_memory { 291; CHECK-LABEL: @Select( 292; CHECK-NEXT: entry: 293; CHECK-NEXT: [[TMP0:%.*]] = load i1, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8, !dbg [[DBG1]] 294; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_origin_tls to i64), i64 16) to ptr), align 4, !dbg [[DBG1]] 295; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_tls, align 8, !dbg [[DBG1]] 296; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4, !dbg [[DBG1]] 297; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8, !dbg [[DBG1]] 298; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_origin_tls to i64), i64 8) to ptr), align 4, !dbg [[DBG1]] 299; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] 300; CHECK-NEXT: [[TMP6:%.*]] = select i1 [[C:%.*]], i32 [[TMP2]], i32 [[TMP4]], !dbg [[DBG1]] 301; CHECK-NEXT: [[TMP7:%.*]] = xor i32 [[A:%.*]], [[B:%.*]], !dbg [[DBG1]] 302; CHECK-NEXT: [[TMP8:%.*]] = or i32 [[TMP7]], [[TMP2]], !dbg [[DBG1]] 303; CHECK-NEXT: [[TMP9:%.*]] = or i32 [[TMP8]], [[TMP4]], !dbg [[DBG1]] 304; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select i1 [[TMP0]], i32 [[TMP9]], i32 [[TMP6]], !dbg [[DBG1]] 305; CHECK-NEXT: [[TMP10:%.*]] = select i1 [[C]], i32 [[TMP3]], i32 [[TMP5]], !dbg [[DBG1]] 306; CHECK-NEXT: [[TMP11:%.*]] = select i1 [[TMP0]], i32 [[TMP1]], i32 [[TMP10]], !dbg [[DBG1]] 307; CHECK-NEXT: [[COND:%.*]] = select i1 [[C]], i32 [[A]], i32 [[B]], !dbg [[DBG1]] 308; CHECK-NEXT: store i32 [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 8 309; CHECK-NEXT: store i32 [[TMP11]], ptr @__msan_retval_origin_tls, align 4 310; CHECK-NEXT: ret i32 [[COND]] 311; 312entry: 313 %cond = select i1 %c, i32 %a, i32 %b, !dbg !10 314 ret i32 %cond 315} 316 317 318 319 320define <8 x i16> @SelectVector(<8 x i16> %a, <8 x i16> %b, <8 x i1> %c) nounwind uwtable readnone sanitize_memory { 321; CHECK-LABEL: @SelectVector( 322; CHECK-NEXT: entry: 323; CHECK-NEXT: [[TMP0:%.*]] = load <8 x i1>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 32) to ptr), align 8, !dbg [[DBG1]] 324; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_origin_tls to i64), i64 32) to ptr), align 4, !dbg [[DBG1]] 325; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr @__msan_param_tls, align 8, !dbg [[DBG1]] 326; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4, !dbg [[DBG1]] 327; CHECK-NEXT: [[TMP4:%.*]] = load <8 x i16>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8, !dbg [[DBG1]] 328; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_origin_tls to i64), i64 16) to ptr), align 4, !dbg [[DBG1]] 329; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] 330; CHECK-NEXT: [[TMP6:%.*]] = select <8 x i1> [[C:%.*]], <8 x i16> [[TMP2]], <8 x i16> [[TMP4]], !dbg [[DBG1]] 331; CHECK-NEXT: [[TMP7:%.*]] = xor <8 x i16> [[A:%.*]], [[B:%.*]], !dbg [[DBG1]] 332; CHECK-NEXT: [[TMP8:%.*]] = or <8 x i16> [[TMP7]], [[TMP2]], !dbg [[DBG1]] 333; CHECK-NEXT: [[TMP9:%.*]] = or <8 x i16> [[TMP8]], [[TMP4]], !dbg [[DBG1]] 334; CHECK-NEXT: [[_MSPROP_SELECT:%.*]] = select <8 x i1> [[TMP0]], <8 x i16> [[TMP9]], <8 x i16> [[TMP6]], !dbg [[DBG1]] 335; CHECK-NEXT: [[TMP10:%.*]] = bitcast <8 x i1> [[C]] to i8, !dbg [[DBG1]] 336; CHECK-NEXT: [[TMP11:%.*]] = icmp ne i8 [[TMP10]], 0, !dbg [[DBG1]] 337; CHECK-NEXT: [[TMP12:%.*]] = bitcast <8 x i1> [[TMP0]] to i8, !dbg [[DBG1]] 338; CHECK-NEXT: [[TMP13:%.*]] = icmp ne i8 [[TMP12]], 0, !dbg [[DBG1]] 339; CHECK-NEXT: [[TMP14:%.*]] = select i1 [[TMP11]], i32 [[TMP3]], i32 [[TMP5]], !dbg [[DBG1]] 340; CHECK-NEXT: [[TMP15:%.*]] = select i1 [[TMP13]], i32 [[TMP1]], i32 [[TMP14]], !dbg [[DBG1]] 341; CHECK-NEXT: [[COND:%.*]] = select <8 x i1> [[C]], <8 x i16> [[A]], <8 x i16> [[B]], !dbg [[DBG1]] 342; CHECK-NEXT: store <8 x i16> [[_MSPROP_SELECT]], ptr @__msan_retval_tls, align 8 343; CHECK-NEXT: store i32 [[TMP15]], ptr @__msan_retval_origin_tls, align 4 344; CHECK-NEXT: ret <8 x i16> [[COND]] 345; 346entry: 347 %cond = select <8 x i1> %c, <8 x i16> %a, <8 x i16> %b, !dbg !10 348 ret <8 x i16> %cond 349} 350 351 352 353 354define ptr @IntToPtr(i64 %x) nounwind uwtable readnone sanitize_memory { 355; CHECK-LABEL: @IntToPtr( 356; CHECK-NEXT: entry: 357; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__msan_param_tls, align 8, !dbg [[DBG1]] 358; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4, !dbg [[DBG1]] 359; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] 360; CHECK-NEXT: [[TMP2:%.*]] = inttoptr i64 [[X:%.*]] to ptr, !dbg [[DBG1]] 361; CHECK-NEXT: store i64 [[TMP0]], ptr @__msan_retval_tls, align 8 362; CHECK-NEXT: store i32 [[TMP1]], ptr @__msan_retval_origin_tls, align 4 363; CHECK-NEXT: ret ptr [[TMP2]] 364; 365entry: 366 %0 = inttoptr i64 %x to ptr, !dbg !10 367 ret ptr %0 368} 369 370 371 372 373 374define i32 @Div(i32 %a, i32 %b) nounwind uwtable readnone sanitize_memory { 375; CHECK-LABEL: @Div( 376; CHECK-NEXT: entry: 377; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8, !dbg [[DBG1]] 378; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_origin_tls to i64), i64 8) to ptr), align 4, !dbg [[DBG1]] 379; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_tls, align 8, !dbg [[DBG1]] 380; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4, !dbg [[DBG1]] 381; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] 382; CHECK-NEXT: call void @__msan_maybe_warning_4(i32 zeroext [[TMP0]], i32 zeroext [[TMP1]]), !dbg [[DBG1]] 383; CHECK-NEXT: [[DIV:%.*]] = udiv i32 [[A:%.*]], [[B:%.*]], !dbg [[DBG1]] 384; CHECK-NEXT: store i32 [[TMP2]], ptr @__msan_retval_tls, align 8 385; CHECK-NEXT: store i32 [[TMP3]], ptr @__msan_retval_origin_tls, align 4 386; CHECK-NEXT: ret i32 [[DIV]] 387; 388entry: 389 %div = udiv i32 %a, %b, !dbg !10 390 ret i32 %div 391} 392 393 394 395 396 397 398 399define i32 @ShadowLoadAlignmentLarge() nounwind uwtable sanitize_memory { 400; CHECK-LABEL: @ShadowLoadAlignmentLarge( 401; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] 402; CHECK-NEXT: [[Y:%.*]] = alloca i32, align 64, !dbg [[DBG1]] 403; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[Y]] to i64, !dbg [[DBG1]] 404; CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080, !dbg [[DBG1]] 405; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr, !dbg [[DBG1]] 406; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[TMP2]], 17592186044416, !dbg [[DBG1]] 407; CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], -4, !dbg [[DBG1]] 408; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr, !dbg [[DBG1]] 409; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 64 [[TMP3]], i8 -1, i64 4, i1 false), !dbg [[DBG1]] 410; CHECK-NEXT: call void @__msan_set_alloca_origin_with_descr(ptr [[Y]], i64 4, ptr @[[GLOB0:[0-9]+]], ptr @[[GLOB1:[0-9]+]]), !dbg [[DBG1]] 411; CHECK-NEXT: [[TMP8:%.*]] = load volatile i32, ptr [[Y]], align 64, !dbg [[DBG7]] 412; CHECK-NEXT: [[TMP9:%.*]] = ptrtoint ptr [[Y]] to i64, !dbg [[DBG7]] 413; CHECK-NEXT: [[TMP10:%.*]] = xor i64 [[TMP9]], 87960930222080, !dbg [[DBG7]] 414; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to ptr, !dbg [[DBG7]] 415; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[TMP10]], 17592186044416, !dbg [[DBG7]] 416; CHECK-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to ptr, !dbg [[DBG7]] 417; CHECK-NEXT: [[_MSLD:%.*]] = load i32, ptr [[TMP11]], align 64, !dbg [[DBG7]] 418; CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP13]], align 64, !dbg [[DBG7]] 419; CHECK-NEXT: store i32 [[_MSLD]], ptr @__msan_retval_tls, align 8 420; CHECK-NEXT: store i32 [[TMP14]], ptr @__msan_retval_origin_tls, align 4 421; CHECK-NEXT: ret i32 [[TMP8]] 422; 423 %y = alloca i32, align 64, !dbg !10 424 %1 = load volatile i32, ptr %y, align 64, !dbg !11 425 ret i32 %1 426} 427 428 429 430define i32 @ExtractElement(<4 x i32> %vec, i32 %idx) sanitize_memory { 431; CHECK-LABEL: @ExtractElement( 432; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8, !dbg [[DBG1]] 433; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_origin_tls to i64), i64 16) to ptr), align 4, !dbg [[DBG1]] 434; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8, !dbg [[DBG1]] 435; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4, !dbg [[DBG1]] 436; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] 437; CHECK-NEXT: [[_MSPROP:%.*]] = extractelement <4 x i32> [[TMP3]], i32 [[IDX:%.*]], !dbg [[DBG1]] 438; CHECK-NEXT: call void @__msan_maybe_warning_4(i32 zeroext [[TMP1]], i32 zeroext [[TMP2]]), !dbg [[DBG1]] 439; CHECK-NEXT: [[X:%.*]] = extractelement <4 x i32> [[VEC:%.*]], i32 [[IDX]], !dbg [[DBG1]] 440; CHECK-NEXT: store i32 [[_MSPROP]], ptr @__msan_retval_tls, align 8 441; CHECK-NEXT: store i32 [[TMP4]], ptr @__msan_retval_origin_tls, align 4 442; CHECK-NEXT: ret i32 [[X]] 443; 444 %x = extractelement <4 x i32> %vec, i32 %idx, !dbg !10 445 ret i32 %x 446} 447 448 449define <4 x i32> @InsertElement(<4 x i32> %vec, i32 %idx, i32 %x) sanitize_memory { 450; CHECK-LABEL: @InsertElement( 451; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8, !dbg [[DBG1]] 452; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_origin_tls to i64), i64 16) to ptr), align 4, !dbg [[DBG1]] 453; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8, !dbg [[DBG1]] 454; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4, !dbg [[DBG1]] 455; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 24) to ptr), align 8, !dbg [[DBG1]] 456; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_origin_tls to i64), i64 24) to ptr), align 4, !dbg [[DBG1]] 457; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] 458; CHECK-NEXT: [[_MSPROP:%.*]] = insertelement <4 x i32> [[TMP3]], i32 [[TMP5]], i32 [[IDX:%.*]], !dbg [[DBG1]] 459; CHECK-NEXT: [[TMP7:%.*]] = icmp ne i32 [[TMP5]], 0, !dbg [[DBG1]] 460; CHECK-NEXT: [[TMP8:%.*]] = select i1 [[TMP7]], i32 [[TMP6]], i32 [[TMP4]], !dbg [[DBG1]] 461; CHECK-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP1]], 0, !dbg [[DBG1]] 462; CHECK-NEXT: [[TMP10:%.*]] = select i1 [[TMP9]], i32 [[TMP2]], i32 [[TMP8]], !dbg [[DBG1]] 463; CHECK-NEXT: call void @__msan_maybe_warning_4(i32 zeroext [[TMP1]], i32 zeroext [[TMP2]]), !dbg [[DBG1]] 464; CHECK-NEXT: [[VEC1:%.*]] = insertelement <4 x i32> [[VEC:%.*]], i32 [[X:%.*]], i32 [[IDX]], !dbg [[DBG1]] 465; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8 466; CHECK-NEXT: store i32 [[TMP10]], ptr @__msan_retval_origin_tls, align 4 467; CHECK-NEXT: ret <4 x i32> [[VEC1]] 468; 469 %vec1 = insertelement <4 x i32> %vec, i32 %x, i32 %idx, !dbg !10 470 ret <4 x i32> %vec1 471} 472 473 474define <4 x i32> @ShuffleVector(<4 x i32> %vec, <4 x i32> %vec1) sanitize_memory { 475; CHECK-LABEL: @ShuffleVector( 476; CHECK-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @__msan_param_tls, align 8, !dbg [[DBG1]] 477; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4, !dbg [[DBG1]] 478; CHECK-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 16) to ptr), align 8, !dbg [[DBG1]] 479; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_origin_tls to i64), i64 16) to ptr), align 4, !dbg [[DBG1]] 480; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] 481; CHECK-NEXT: [[_MSPROP:%.*]] = shufflevector <4 x i32> [[TMP1]], <4 x i32> [[TMP3]], <4 x i32> <i32 0, i32 4, i32 1, i32 5>, !dbg [[DBG1]] 482; CHECK-NEXT: [[TMP5:%.*]] = bitcast <4 x i32> [[TMP3]] to i128, !dbg [[DBG1]] 483; CHECK-NEXT: [[TMP6:%.*]] = icmp ne i128 [[TMP5]], 0, !dbg [[DBG1]] 484; CHECK-NEXT: [[TMP7:%.*]] = select i1 [[TMP6]], i32 [[TMP4]], i32 [[TMP2]], !dbg [[DBG1]] 485; CHECK-NEXT: [[VEC2:%.*]] = shufflevector <4 x i32> [[VEC:%.*]], <4 x i32> [[VEC1:%.*]], <4 x i32> <i32 0, i32 4, i32 1, i32 5>, !dbg [[DBG1]] 486; CHECK-NEXT: store <4 x i32> [[_MSPROP]], ptr @__msan_retval_tls, align 8 487; CHECK-NEXT: store i32 [[TMP7]], ptr @__msan_retval_origin_tls, align 4 488; CHECK-NEXT: ret <4 x i32> [[VEC2]] 489; 490 %vec2 = shufflevector <4 x i32> %vec, <4 x i32> %vec1, <4 x i32> <i32 0, i32 4, i32 1, i32 5>, !dbg !10 491 ret <4 x i32> %vec2 492} 493 494 495 496%struct.__va_list_tag = type { i32, i32, ptr, ptr } 497declare void @llvm.va_start(ptr) nounwind 498 499define void @VAStart(i32 %x, ...) sanitize_memory { 500; CHECK-LABEL: @VAStart( 501; CHECK-NEXT: entry: 502; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr @__msan_va_arg_overflow_size_tls, align 8, !dbg [[DBG1]] 503; CHECK-NEXT: [[TMP1:%.*]] = add i64 176, [[TMP0]], !dbg [[DBG1]] 504; CHECK-NEXT: [[TMP2:%.*]] = alloca i8, i64 [[TMP1]], align 8, !dbg [[DBG1]] 505; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP2]], i8 0, i64 [[TMP1]], i1 false), !dbg [[DBG1]] 506; CHECK-NEXT: [[SRCSZ:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP1]], i64 800), !dbg [[DBG1]] 507; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP2]], ptr align 8 @__msan_va_arg_tls, i64 [[SRCSZ]], i1 false), !dbg [[DBG1]] 508; CHECK-NEXT: [[TMP3:%.*]] = alloca i8, i64 [[TMP1]], align 8, !dbg [[DBG1]] 509; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 8 [[TMP3]], ptr align 8 @__msan_va_arg_origin_tls, i64 [[SRCSZ]], i1 false), !dbg [[DBG1]] 510; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr @__msan_param_tls, align 8, !dbg [[DBG1]] 511; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr @__msan_param_origin_tls, align 4, !dbg [[DBG1]] 512; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] 513; CHECK-NEXT: [[X_ADDR:%.*]] = alloca i32, align 4, !dbg [[DBG1]] 514; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[X_ADDR]] to i64, !dbg [[DBG1]] 515; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 87960930222080, !dbg [[DBG1]] 516; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr, !dbg [[DBG1]] 517; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[TMP7]], 17592186044416, !dbg [[DBG1]] 518; CHECK-NEXT: [[TMP10:%.*]] = and i64 [[TMP9]], -4, !dbg [[DBG1]] 519; CHECK-NEXT: [[TMP11:%.*]] = inttoptr i64 [[TMP10]] to ptr, !dbg [[DBG1]] 520; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[TMP8]], i8 -1, i64 4, i1 false), !dbg [[DBG1]] 521; CHECK-NEXT: call void @__msan_set_alloca_origin_with_descr(ptr [[X_ADDR]], i64 4, ptr @[[GLOB2:[0-9]+]], ptr @[[GLOB3:[0-9]+]]), !dbg [[DBG1]] 522; CHECK-NEXT: [[VA:%.*]] = alloca [1 x %struct.__va_list_tag], align 16, !dbg [[DBG7]] 523; CHECK-NEXT: [[TMP13:%.*]] = ptrtoint ptr [[VA]] to i64, !dbg [[DBG7]] 524; CHECK-NEXT: [[TMP14:%.*]] = xor i64 [[TMP13]], 87960930222080, !dbg [[DBG7]] 525; CHECK-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP14]] to ptr, !dbg [[DBG7]] 526; CHECK-NEXT: [[TMP16:%.*]] = add i64 [[TMP14]], 17592186044416, !dbg [[DBG7]] 527; CHECK-NEXT: [[TMP17:%.*]] = and i64 [[TMP16]], -4, !dbg [[DBG7]] 528; CHECK-NEXT: [[TMP18:%.*]] = inttoptr i64 [[TMP17]] to ptr, !dbg [[DBG7]] 529; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 16 [[TMP15]], i8 -1, i64 24, i1 false), !dbg [[DBG7]] 530; CHECK-NEXT: call void @__msan_set_alloca_origin_with_descr(ptr [[VA]], i64 24, ptr @[[GLOB4:[0-9]+]], ptr @[[GLOB5:[0-9]+]]), !dbg [[DBG7]] 531; CHECK-NEXT: [[TMP20:%.*]] = ptrtoint ptr [[X_ADDR]] to i64, !dbg [[DBG8]] 532; CHECK-NEXT: [[TMP21:%.*]] = xor i64 [[TMP20]], 87960930222080, !dbg [[DBG8]] 533; CHECK-NEXT: [[TMP22:%.*]] = inttoptr i64 [[TMP21]] to ptr, !dbg [[DBG8]] 534; CHECK-NEXT: [[TMP23:%.*]] = add i64 [[TMP21]], 17592186044416, !dbg [[DBG8]] 535; CHECK-NEXT: [[TMP24:%.*]] = inttoptr i64 [[TMP23]] to ptr, !dbg [[DBG8]] 536; CHECK-NEXT: store i32 [[TMP4]], ptr [[TMP22]], align 4, !dbg [[DBG8]] 537; CHECK-NEXT: call void @__msan_maybe_store_origin_4(i32 zeroext [[TMP4]], ptr [[X_ADDR]], i32 zeroext [[TMP5]]), !dbg [[DBG8]] 538; CHECK-NEXT: store i32 [[X:%.*]], ptr [[X_ADDR]], align 4, !dbg [[DBG8]] 539; CHECK-NEXT: [[TMP26:%.*]] = ptrtoint ptr [[VA]] to i64, !dbg [[DBG11:![0-9]+]] 540; CHECK-NEXT: [[TMP27:%.*]] = xor i64 [[TMP26]], 87960930222080, !dbg [[DBG11]] 541; CHECK-NEXT: [[TMP28:%.*]] = inttoptr i64 [[TMP27]] to ptr, !dbg [[DBG11]] 542; CHECK-NEXT: [[TMP29:%.*]] = add i64 [[TMP27]], 17592186044416, !dbg [[DBG11]] 543; CHECK-NEXT: [[TMP30:%.*]] = inttoptr i64 [[TMP29]] to ptr, !dbg [[DBG11]] 544; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 8 [[TMP28]], i8 0, i64 24, i1 false), !dbg [[DBG11]] 545; CHECK-NEXT: call void @llvm.va_start.p0(ptr [[VA]]), !dbg [[DBG11]] 546; CHECK-NEXT: [[TMP31:%.*]] = ptrtoint ptr [[VA]] to i64, !dbg [[DBG11]] 547; CHECK-NEXT: [[TMP32:%.*]] = add i64 [[TMP31]], 16, !dbg [[DBG11]] 548; CHECK-NEXT: [[TMP33:%.*]] = inttoptr i64 [[TMP32]] to ptr, !dbg [[DBG11]] 549; CHECK-NEXT: [[TMP34:%.*]] = load ptr, ptr [[TMP33]], align 8, !dbg [[DBG11]] 550; CHECK-NEXT: [[TMP35:%.*]] = ptrtoint ptr [[TMP34]] to i64, !dbg [[DBG11]] 551; CHECK-NEXT: [[TMP36:%.*]] = xor i64 [[TMP35]], 87960930222080, !dbg [[DBG11]] 552; CHECK-NEXT: [[TMP37:%.*]] = inttoptr i64 [[TMP36]] to ptr, !dbg [[DBG11]] 553; CHECK-NEXT: [[TMP38:%.*]] = add i64 [[TMP36]], 17592186044416, !dbg [[DBG11]] 554; CHECK-NEXT: [[TMP39:%.*]] = inttoptr i64 [[TMP38]] to ptr, !dbg [[DBG11]] 555; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[TMP37]], ptr align 16 [[TMP2]], i64 176, i1 false), !dbg [[DBG11]] 556; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[TMP39]], ptr align 16 [[TMP3]], i64 176, i1 false), !dbg [[DBG11]] 557; CHECK-NEXT: [[TMP41:%.*]] = ptrtoint ptr [[VA]] to i64, !dbg [[DBG11]] 558; CHECK-NEXT: [[TMP42:%.*]] = add i64 [[TMP41]], 8, !dbg [[DBG11]] 559; CHECK-NEXT: [[TMP43:%.*]] = inttoptr i64 [[TMP42]] to ptr, !dbg [[DBG11]] 560; CHECK-NEXT: [[TMP44:%.*]] = load ptr, ptr [[TMP43]], align 8, !dbg [[DBG11]] 561; CHECK-NEXT: [[TMP45:%.*]] = ptrtoint ptr [[TMP44]] to i64, !dbg [[DBG11]] 562; CHECK-NEXT: [[TMP46:%.*]] = xor i64 [[TMP45]], 87960930222080, !dbg [[DBG11]] 563; CHECK-NEXT: [[TMP47:%.*]] = inttoptr i64 [[TMP46]] to ptr, !dbg [[DBG11]] 564; CHECK-NEXT: [[TMP48:%.*]] = add i64 [[TMP46]], 17592186044416, !dbg [[DBG11]] 565; CHECK-NEXT: [[TMP49:%.*]] = inttoptr i64 [[TMP48]] to ptr, !dbg [[DBG11]] 566; CHECK-NEXT: [[TMP50:%.*]] = getelementptr i8, ptr [[TMP2]], i32 176, !dbg [[DBG11]] 567; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[TMP47]], ptr align 16 [[TMP50]], i64 [[TMP0]], i1 false), !dbg [[DBG11]] 568; CHECK-NEXT: [[TMP51:%.*]] = getelementptr i8, ptr [[TMP3]], i32 176, !dbg [[DBG11]] 569; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 16 [[TMP49]], ptr align 16 [[TMP51]], i64 [[TMP0]], i1 false), !dbg [[DBG11]] 570; CHECK-NEXT: ret void 571; 572entry: 573 %x.addr = alloca i32, align 4, !dbg !10 574 %va = alloca [1 x %struct.__va_list_tag], align 16, !dbg !11 575 store i32 %x, ptr %x.addr, align 4, !dbg !12 576 call void @llvm.va_start(ptr %va), !dbg !15 577 ret void 578} 579 580 581 582define i32 @NoSanitizeMemory(i32 %x) uwtable { 583; CHECK-LABEL: @NoSanitizeMemory( 584; CHECK-NEXT: entry: 585; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] 586; CHECK-NEXT: [[TMP0:%.*]] = xor i32 [[X:%.*]], 0, !dbg [[DBG1]] 587; CHECK-NEXT: [[TMP1:%.*]] = and i32 -1, [[TMP0]], !dbg [[DBG1]] 588; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0, !dbg [[DBG1]] 589; CHECK-NEXT: [[_MSPROP_ICMP:%.*]] = and i1 false, [[TMP2]], !dbg [[DBG1]] 590; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i32 [[X]], 0, !dbg [[DBG1]] 591; CHECK-NEXT: br i1 [[TOBOOL]], label [[IF_END:%.*]], label [[IF_THEN:%.*]], !dbg [[DBG7]] 592; CHECK: if.then: 593; CHECK-NEXT: tail call void @bar(), !dbg [[DBG8]] 594; CHECK-NEXT: br label [[IF_END]] 595; CHECK: if.end: 596; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8 597; CHECK-NEXT: store i32 0, ptr @__msan_retval_origin_tls, align 4 598; CHECK-NEXT: ret i32 [[X]] 599; 600entry: 601 %tobool = icmp eq i32 %x, 0, !dbg !10 602 br i1 %tobool, label %if.end, label %if.then, !dbg !11 603 604if.then: tail call void @bar(), !dbg !12 605 br label %if.end 606 607if.end: ret i32 %x 608} 609 610declare void @bar() 611 612 613 614 615define i32 @NoSanitizeMemoryAlloca() { 616; CHECK-LABEL: @NoSanitizeMemoryAlloca( 617; CHECK-NEXT: entry: 618; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] 619; CHECK-NEXT: [[P:%.*]] = alloca i32, align 4, !dbg [[DBG1]] 620; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[P]] to i64, !dbg [[DBG1]] 621; CHECK-NEXT: [[TMP1:%.*]] = xor i64 [[TMP0]], 87960930222080, !dbg [[DBG1]] 622; CHECK-NEXT: [[TMP2:%.*]] = inttoptr i64 [[TMP1]] to ptr, !dbg [[DBG1]] 623; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[TMP1]], 17592186044416, !dbg [[DBG1]] 624; CHECK-NEXT: [[TMP4:%.*]] = and i64 [[TMP3]], -4, !dbg [[DBG1]] 625; CHECK-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr, !dbg [[DBG1]] 626; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 4 [[TMP2]], i8 0, i64 4, i1 false), !dbg [[DBG1]] 627; CHECK-NEXT: store i64 0, ptr @__msan_param_tls, align 8, !dbg [[DBG7]] 628; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8, !dbg [[DBG7]] 629; CHECK-NEXT: [[X:%.*]] = call i32 @NoSanitizeMemoryAllocaHelper(ptr [[P]]), !dbg [[DBG7]] 630; CHECK-NEXT: [[_MSRET:%.*]] = load i32, ptr @__msan_retval_tls, align 8 631; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr @__msan_retval_origin_tls, align 4 632; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8 633; CHECK-NEXT: store i32 0, ptr @__msan_retval_origin_tls, align 4 634; CHECK-NEXT: ret i32 [[X]] 635; 636entry: 637 %p = alloca i32, align 4, !dbg !10 638 %x = call i32 @NoSanitizeMemoryAllocaHelper(ptr %p), !dbg !11 639 ret i32 %x 640} 641 642declare i32 @NoSanitizeMemoryAllocaHelper(ptr %p) 643 644 645 646 647define i32 @NoSanitizeMemoryUndef() { 648; CHECK-LABEL: @NoSanitizeMemoryUndef( 649; CHECK-NEXT: entry: 650; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] 651; CHECK-NEXT: store i32 0, ptr @__msan_param_tls, align 8, !dbg [[DBG1]] 652; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8, !dbg [[DBG1]] 653; CHECK-NEXT: [[X:%.*]] = call i32 @NoSanitizeMemoryUndefHelper(i32 undef), !dbg [[DBG1]] 654; CHECK-NEXT: [[_MSRET:%.*]] = load i32, ptr @__msan_retval_tls, align 8 655; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr @__msan_retval_origin_tls, align 4 656; CHECK-NEXT: store i32 0, ptr @__msan_retval_tls, align 8 657; CHECK-NEXT: store i32 0, ptr @__msan_retval_origin_tls, align 4 658; CHECK-NEXT: ret i32 [[X]] 659; 660entry: 661 %x = call i32 @NoSanitizeMemoryUndefHelper(i32 undef), !dbg !10 662 ret i32 %x 663} 664 665declare i32 @NoSanitizeMemoryUndefHelper(i32 %x) 666 667declare void @llvm.lifetime.start.p0(i64 immarg %0, ptr nocapture %1) 668declare void @llvm.lifetime.end.p0(i64 immarg %0, ptr nocapture %1) 669declare void @foo8(ptr nocapture) 670 671 672define void @msan() sanitize_memory { 673; CHECK-LABEL: @msan( 674; CHECK-NEXT: entry: 675; CHECK-NEXT: call void @llvm.donothing(), !dbg [[DBG1]] 676; CHECK-NEXT: [[TEXT:%.*]] = alloca i8, align 1, !dbg [[DBG1]] 677; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 1, ptr [[TEXT]]), !dbg [[DBG7]] 678; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[TEXT]] to i64, !dbg [[DBG7]] 679; CHECK-NEXT: [[TMP1:%.*]] = xor i64 [[TMP0]], 87960930222080, !dbg [[DBG7]] 680; CHECK-NEXT: [[TMP2:%.*]] = inttoptr i64 [[TMP1]] to ptr, !dbg [[DBG7]] 681; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[TMP1]], 17592186044416, !dbg [[DBG7]] 682; CHECK-NEXT: [[TMP4:%.*]] = and i64 [[TMP3]], -4, !dbg [[DBG7]] 683; CHECK-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr, !dbg [[DBG7]] 684; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr align 1 [[TMP2]], i8 -1, i64 1, i1 false), !dbg [[DBG7]] 685; CHECK-NEXT: call void @__msan_set_alloca_origin_with_descr(ptr [[TEXT]], i64 1, ptr @[[GLOB6:[0-9]+]], ptr @[[GLOB7:[0-9]+]]), !dbg [[DBG7]] 686; CHECK-NEXT: store i64 0, ptr @__msan_param_tls, align 8, !dbg [[DBG8]] 687; CHECK-NEXT: call void @foo8(ptr [[TEXT]]), !dbg [[DBG8]] 688; CHECK-NEXT: call void @llvm.lifetime.end.p0(i64 1, ptr [[TEXT]]), !dbg 689; CHECK-NEXT: ret void, !dbg 690; 691entry: 692 %text = alloca i8, align 1, !dbg !10 693 call void @llvm.lifetime.start.p0(i64 1, ptr %text), !dbg !11 694 call void @foo8(ptr %text), !dbg !12 695 call void @llvm.lifetime.end.p0(i64 1, ptr %text), !dbg !13 696 ret void, !dbg !14 697} 698