1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py 2; RUN: opt %s -S -passes=msan 2>&1 | FileCheck %s 3 4target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" 5target triple = "x86_64-unknown-linux-gnu" 6 7declare i64 @llvm.ctlz.i64(i64, i1) nounwind readnone 8define i64 @test_ctlz_i64_zeropoison(i64 %v) #0 { 9; CHECK-LABEL: @test_ctlz_i64_zeropoison( 10; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 11; CHECK-NEXT: call void @llvm.donothing() 12; CHECK-NEXT: [[_MSCZ_BS:%.*]] = icmp ne i64 [[TMP1]], 0 13; CHECK-NEXT: [[_MSCZ_BZP:%.*]] = icmp eq i64 [[V:%.*]], 0 14; CHECK-NEXT: [[_MSCZ_BS1:%.*]] = or i1 [[_MSCZ_BS]], [[_MSCZ_BZP]] 15; CHECK-NEXT: [[_MSCZ_OS:%.*]] = sext i1 [[_MSCZ_BS1]] to i64 16; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.ctlz.i64(i64 [[V]], i1 true) 17; CHECK-NEXT: store i64 [[_MSCZ_OS]], ptr @__msan_retval_tls, align 8 18; CHECK-NEXT: ret i64 [[RES]] 19; 20 %res = call i64 @llvm.ctlz.i64(i64 %v, i1 true) ; <<i64>> [#uses=1] 21 ret i64 %res 22} 23define i64 @test_ctlz_i64_nozeropoison(i64 %v) #0 { 24; CHECK-LABEL: @test_ctlz_i64_nozeropoison( 25; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 26; CHECK-NEXT: call void @llvm.donothing() 27; CHECK-NEXT: [[_MSCZ_BS:%.*]] = icmp ne i64 [[TMP1]], 0 28; CHECK-NEXT: [[_MSCZ_OS:%.*]] = sext i1 [[_MSCZ_BS]] to i64 29; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.ctlz.i64(i64 [[V:%.*]], i1 false) 30; CHECK-NEXT: store i64 [[_MSCZ_OS]], ptr @__msan_retval_tls, align 8 31; CHECK-NEXT: ret i64 [[RES]] 32; 33 %res = call i64 @llvm.ctlz.i64(i64 %v, i1 false) ; <<i64>> [#uses=1] 34 ret i64 %res 35} 36 37declare <2 x i64> @llvm.ctlz.v2i64(<2 x i64>, i1) nounwind readnone 38define <2 x i64> @test_ctlz_v2i64_zeropoison(<2 x i64> %v) #0 { 39; CHECK-LABEL: @test_ctlz_v2i64_zeropoison( 40; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 41; CHECK-NEXT: call void @llvm.donothing() 42; CHECK-NEXT: [[_MSCZ_BS:%.*]] = icmp ne <2 x i64> [[TMP1]], zeroinitializer 43; CHECK-NEXT: [[_MSCZ_BZP:%.*]] = icmp eq <2 x i64> [[V:%.*]], zeroinitializer 44; CHECK-NEXT: [[_MSCZ_BS1:%.*]] = or <2 x i1> [[_MSCZ_BS]], [[_MSCZ_BZP]] 45; CHECK-NEXT: [[_MSCZ_OS:%.*]] = sext <2 x i1> [[_MSCZ_BS1]] to <2 x i64> 46; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> [[V]], i1 true) 47; CHECK-NEXT: store <2 x i64> [[_MSCZ_OS]], ptr @__msan_retval_tls, align 8 48; CHECK-NEXT: ret <2 x i64> [[RES]] 49; 50 %res = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %v, i1 true) ; <<2 x i64>> [#uses=1] 51 ret <2 x i64> %res 52} 53define <2 x i64> @test_ctlz_v2i64_nozeropoison(<2 x i64> %v) #0 { 54; CHECK-LABEL: @test_ctlz_v2i64_nozeropoison( 55; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 56; CHECK-NEXT: call void @llvm.donothing() 57; CHECK-NEXT: [[_MSCZ_BS:%.*]] = icmp ne <2 x i64> [[TMP1]], zeroinitializer 58; CHECK-NEXT: [[_MSCZ_OS:%.*]] = sext <2 x i1> [[_MSCZ_BS]] to <2 x i64> 59; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> [[V:%.*]], i1 false) 60; CHECK-NEXT: store <2 x i64> [[_MSCZ_OS]], ptr @__msan_retval_tls, align 8 61; CHECK-NEXT: ret <2 x i64> [[RES]] 62; 63 %res = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %v, i1 false) ; <<2 x i64>> [#uses=1] 64 ret <2 x i64> %res 65} 66 67declare i64 @llvm.cttz.i64(i64, i1) nounwind readnone 68define i64 @test_cttz_i64_zeropoison(i64 %v) #0 { 69; CHECK-LABEL: @test_cttz_i64_zeropoison( 70; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 71; CHECK-NEXT: call void @llvm.donothing() 72; CHECK-NEXT: [[_MSCZ_BS:%.*]] = icmp ne i64 [[TMP1]], 0 73; CHECK-NEXT: [[_MSCZ_BZP:%.*]] = icmp eq i64 [[V:%.*]], 0 74; CHECK-NEXT: [[_MSCZ_BS1:%.*]] = or i1 [[_MSCZ_BS]], [[_MSCZ_BZP]] 75; CHECK-NEXT: [[_MSCZ_OS:%.*]] = sext i1 [[_MSCZ_BS1]] to i64 76; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.cttz.i64(i64 [[V]], i1 true) 77; CHECK-NEXT: store i64 [[_MSCZ_OS]], ptr @__msan_retval_tls, align 8 78; CHECK-NEXT: ret i64 [[RES]] 79; 80 %res = call i64 @llvm.cttz.i64(i64 %v, i1 true) ; <<i64>> [#uses=1] 81 ret i64 %res 82} 83define i64 @test_cttz_i64_nozeropoison(i64 %v) #0 { 84; CHECK-LABEL: @test_cttz_i64_nozeropoison( 85; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 86; CHECK-NEXT: call void @llvm.donothing() 87; CHECK-NEXT: [[_MSCZ_BS:%.*]] = icmp ne i64 [[TMP1]], 0 88; CHECK-NEXT: [[_MSCZ_OS:%.*]] = sext i1 [[_MSCZ_BS]] to i64 89; CHECK-NEXT: [[RES:%.*]] = call i64 @llvm.cttz.i64(i64 [[V:%.*]], i1 false) 90; CHECK-NEXT: store i64 [[_MSCZ_OS]], ptr @__msan_retval_tls, align 8 91; CHECK-NEXT: ret i64 [[RES]] 92; 93 %res = call i64 @llvm.cttz.i64(i64 %v, i1 false) ; <<i64>> [#uses=1] 94 ret i64 %res 95} 96 97declare <2 x i64> @llvm.cttz.v2i64(<2 x i64>, i1) nounwind readnone 98define <2 x i64> @test_cttz_v2i64_zeropoison(<2 x i64> %v) #0 { 99; CHECK-LABEL: @test_cttz_v2i64_zeropoison( 100; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 101; CHECK-NEXT: call void @llvm.donothing() 102; CHECK-NEXT: [[_MSCZ_BS:%.*]] = icmp ne <2 x i64> [[TMP1]], zeroinitializer 103; CHECK-NEXT: [[_MSCZ_BZP:%.*]] = icmp eq <2 x i64> [[V:%.*]], zeroinitializer 104; CHECK-NEXT: [[_MSCZ_BS1:%.*]] = or <2 x i1> [[_MSCZ_BS]], [[_MSCZ_BZP]] 105; CHECK-NEXT: [[_MSCZ_OS:%.*]] = sext <2 x i1> [[_MSCZ_BS1]] to <2 x i64> 106; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> [[V]], i1 true) 107; CHECK-NEXT: store <2 x i64> [[_MSCZ_OS]], ptr @__msan_retval_tls, align 8 108; CHECK-NEXT: ret <2 x i64> [[RES]] 109; 110 %res = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %v, i1 true) ; <<2 x i64>> [#uses=1] 111 ret <2 x i64> %res 112} 113define <2 x i64> @test_cttz_v2i64_nozeropoison(<2 x i64> %v) #0 { 114; CHECK-LABEL: @test_cttz_v2i64_nozeropoison( 115; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @__msan_param_tls, align 8 116; CHECK-NEXT: call void @llvm.donothing() 117; CHECK-NEXT: [[_MSCZ_BS:%.*]] = icmp ne <2 x i64> [[TMP1]], zeroinitializer 118; CHECK-NEXT: [[_MSCZ_OS:%.*]] = sext <2 x i1> [[_MSCZ_BS]] to <2 x i64> 119; CHECK-NEXT: [[RES:%.*]] = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> [[V:%.*]], i1 false) 120; CHECK-NEXT: store <2 x i64> [[_MSCZ_OS]], ptr @__msan_retval_tls, align 8 121; CHECK-NEXT: ret <2 x i64> [[RES]] 122; 123 %res = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %v, i1 false) ; <<2 x i64>> [#uses=1] 124 ret <2 x i64> %res 125} 126 127 128attributes #0 = { sanitize_memory } 129