1; RUN: opt < %s -msan-check-access-address=0 -S -passes=msan 2>&1 | FileCheck %s 2; REQUIRES: x86-registered-target 3 4target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" 5target triple = "x86_64-unknown-linux-gnu" 6 7declare <2 x i64> @llvm.x86.pclmulqdq(<2 x i64>, <2 x i64>, i8 immarg) nounwind readnone 8declare <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64>, <4 x i64>, i8 immarg) nounwind readnone 9declare <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64>, <8 x i64>, i8 immarg) nounwind readnone 10 11define <2 x i64> @clmul00(<2 x i64> %a, <2 x i64> %b) sanitize_memory { 12entry: 13 %0 = tail call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %a, <2 x i64> %b, i8 0) 14 ret <2 x i64> %0 15} 16 17; CHECK-LABEL: @clmul00 18; CHECK: %[[S0:.*]] = load <2 x i64>, ptr {{.*}}@__msan_param_tls 19; CHECK: %[[S1:.*]] = load <2 x i64>, ptr {{.*}}@__msan_param_tls 20; CHECK: %[[SHUF0:.*]] = shufflevector <2 x i64> %[[S0]], <2 x i64> poison, <2 x i32> zeroinitializer 21; CHECK: %[[SHUF1:.*]] = shufflevector <2 x i64> %[[S1]], <2 x i64> poison, <2 x i32> zeroinitializer 22; CHECK: %[[SRET:.*]] = or <2 x i64> %[[SHUF0]], %[[SHUF1]] 23; CHECK: store <2 x i64> %[[SRET]], ptr {{.*}}@__msan_retval_tls 24 25define <2 x i64> @clmul10(<2 x i64> %a, <2 x i64> %b) sanitize_memory { 26entry: 27 %0 = tail call <2 x i64> @llvm.x86.pclmulqdq(<2 x i64> %a, <2 x i64> %b, i8 16) 28 ret <2 x i64> %0 29} 30 31; CHECK-LABEL: @clmul10 32; CHECK: %[[S0:.*]] = load <2 x i64>, ptr {{.*}}@__msan_param_tls 33; CHECK: %[[S1:.*]] = load <2 x i64>, ptr {{.*}}@__msan_param_tls 34; CHECK: %[[SHUF0:.*]] = shufflevector <2 x i64> %[[S0]], <2 x i64> poison, <2 x i32> zeroinitializer 35; CHECK: %[[SHUF1:.*]] = shufflevector <2 x i64> %[[S1]], <2 x i64> poison, <2 x i32> <i32 1, i32 1> 36; CHECK: %[[SRET:.*]] = or <2 x i64> %[[SHUF0]], %[[SHUF1]] 37; CHECK: store <2 x i64> %[[SRET]], ptr {{.*}}@__msan_retval_tls 38 39define <4 x i64> @clmul11_256(<4 x i64> %a, <4 x i64> %b) sanitize_memory { 40entry: 41 %0 = tail call <4 x i64> @llvm.x86.pclmulqdq.256(<4 x i64> %a, <4 x i64> %b, i8 17) 42 ret <4 x i64> %0 43} 44 45; CHECK-LABEL: @clmul11_256 46; CHECK: %[[S0:.*]] = load <4 x i64>, ptr {{.*}}@__msan_param_tls 47; CHECK: %[[S1:.*]] = load <4 x i64>, ptr {{.*}}@__msan_param_tls 48; CHECK: %[[SHUF0:.*]] = shufflevector <4 x i64> %[[S0]], <4 x i64> poison, <4 x i32> <i32 1, i32 1, i32 3, i32 3> 49; CHECK: %[[SHUF1:.*]] = shufflevector <4 x i64> %[[S1]], <4 x i64> poison, <4 x i32> <i32 1, i32 1, i32 3, i32 3> 50; CHECK: %[[SRET:.*]] = or <4 x i64> %[[SHUF0]], %[[SHUF1]] 51; CHECK: store <4 x i64> %[[SRET]], ptr {{.*}}@__msan_retval_tls 52 53define <8 x i64> @clmul01_512(<8 x i64> %a, <8 x i64> %b) sanitize_memory { 54entry: 55 %0 = tail call <8 x i64> @llvm.x86.pclmulqdq.512(<8 x i64> %a, <8 x i64> %b, i8 16) 56 ret <8 x i64> %0 57} 58 59; CHECK-LABEL: @clmul01_512 60; CHECK: %[[S0:.*]] = load <8 x i64>, ptr {{.*}}@__msan_param_tls 61; CHECK: %[[S1:.*]] = load <8 x i64>, ptr {{.*}}@__msan_param_tls 62; CHECK: %[[SHUF0:.*]] = shufflevector <8 x i64> %[[S0]], <8 x i64> poison, <8 x i32> <i32 0, i32 0, i32 2, i32 2, i32 4, i32 4, i32 6, i32 6> 63; CHECK: %[[SHUF1:.*]] = shufflevector <8 x i64> %[[S1]], <8 x i64> poison, <8 x i32> <i32 1, i32 1, i32 3, i32 3, i32 5, i32 5, i32 7, i32 7> 64; CHECK: %[[SRET:.*]] = or <8 x i64> %[[SHUF0]], %[[SHUF1]] 65; ORIGIN: %[[FLAT:.*]] = bitcast <8 x i64> %[[SHUF1]] to i512 66; ORIGIN: %[[I:.*]] = icmp ne i512 %[[FLAT]], 0 67; ORIGIN: %[[O:.*]] = select i1 %[[I]], 68; CHECK: store <8 x i64> %[[SRET]], ptr {{.*}}@__msan_retval_tls 69; ORIGIN: store i32 %[[O]], ptr @__msan_retval_origin_tls 70