1*5ceb0bc7SSimon Moll; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2*5ceb0bc7SSimon Moll; RUN: llc < %s -mtriple=ve-unknown-unknown -mattr=+vpu | FileCheck %s 3*5ceb0bc7SSimon Moll 4*5ceb0bc7SSimon Molldefine fastcc <512 x i32> @brd_v512i32(i32 %s) { 5*5ceb0bc7SSimon Moll; CHECK-LABEL: brd_v512i32: 6*5ceb0bc7SSimon Moll; CHECK: # %bb.0: 7*5ceb0bc7SSimon Moll; CHECK-NEXT: and %s0, %s0, (32)0 8*5ceb0bc7SSimon Moll; CHECK-NEXT: sll %s1, %s0, 32 9*5ceb0bc7SSimon Moll; CHECK-NEXT: and %s0, %s0, (32)0 10*5ceb0bc7SSimon Moll; CHECK-NEXT: or %s0, %s0, %s1 11*5ceb0bc7SSimon Moll; CHECK-NEXT: lea %s1, 256 12*5ceb0bc7SSimon Moll; CHECK-NEXT: lvl %s1 13*5ceb0bc7SSimon Moll; CHECK-NEXT: vbrd %v0, %s0 14*5ceb0bc7SSimon Moll; CHECK-NEXT: b.l.t (, %s10) 15*5ceb0bc7SSimon Moll %val = insertelement <512 x i32> undef, i32 %s, i32 0 16*5ceb0bc7SSimon Moll %ret = shufflevector <512 x i32> %val, <512 x i32> undef, <512 x i32> zeroinitializer 17*5ceb0bc7SSimon Moll ret <512 x i32> %ret 18*5ceb0bc7SSimon Moll} 19*5ceb0bc7SSimon Moll 20*5ceb0bc7SSimon Molldefine fastcc <512 x i32> @brdi_v512i32() { 21*5ceb0bc7SSimon Moll; CHECK-LABEL: brdi_v512i32: 22*5ceb0bc7SSimon Moll; CHECK: # %bb.0: 23*5ceb0bc7SSimon Moll; CHECK-NEXT: or %s0, 17, (0)1 24*5ceb0bc7SSimon Moll; CHECK-NEXT: sll %s1, %s0, 32 25*5ceb0bc7SSimon Moll; CHECK-NEXT: and %s0, %s0, (32)0 26*5ceb0bc7SSimon Moll; CHECK-NEXT: or %s0, %s0, %s1 27*5ceb0bc7SSimon Moll; CHECK-NEXT: lea %s1, 256 28*5ceb0bc7SSimon Moll; CHECK-NEXT: lvl %s1 29*5ceb0bc7SSimon Moll; CHECK-NEXT: vbrd %v0, %s0 30*5ceb0bc7SSimon Moll; CHECK-NEXT: b.l.t (, %s10) 31*5ceb0bc7SSimon Moll %val = insertelement <512 x i32> undef, i32 17, i32 0 32*5ceb0bc7SSimon Moll %ret = shufflevector <512 x i32> %val, <512 x i32> undef, <512 x i32> zeroinitializer 33*5ceb0bc7SSimon Moll ret <512 x i32> %ret 34*5ceb0bc7SSimon Moll} 35*5ceb0bc7SSimon Moll 36*5ceb0bc7SSimon Molldefine fastcc <512 x float> @brd_v512f32(float %s) { 37*5ceb0bc7SSimon Moll; CHECK-LABEL: brd_v512f32: 38*5ceb0bc7SSimon Moll; CHECK: # %bb.0: 39*5ceb0bc7SSimon Moll; CHECK-NEXT: and %s1, %s0, (32)1 40*5ceb0bc7SSimon Moll; CHECK-NEXT: srl %s0, %s0, 32 41*5ceb0bc7SSimon Moll; CHECK-NEXT: or %s0, %s0, %s1 42*5ceb0bc7SSimon Moll; CHECK-NEXT: lea %s1, 256 43*5ceb0bc7SSimon Moll; CHECK-NEXT: lvl %s1 44*5ceb0bc7SSimon Moll; CHECK-NEXT: vbrd %v0, %s0 45*5ceb0bc7SSimon Moll; CHECK-NEXT: b.l.t (, %s10) 46*5ceb0bc7SSimon Moll %val = insertelement <512 x float> undef, float %s, i32 0 47*5ceb0bc7SSimon Moll %ret = shufflevector <512 x float> %val, <512 x float> undef, <512 x i32> zeroinitializer 48*5ceb0bc7SSimon Moll ret <512 x float> %ret 49*5ceb0bc7SSimon Moll} 50*5ceb0bc7SSimon Moll 51*5ceb0bc7SSimon Molldefine fastcc <512 x float> @brdi_v512f32() { 52*5ceb0bc7SSimon Moll; CHECK-LABEL: brdi_v512f32: 53*5ceb0bc7SSimon Moll; CHECK: # %bb.0: 54*5ceb0bc7SSimon Moll; CHECK-NEXT: lea.sl %s0, 0 55*5ceb0bc7SSimon Moll; CHECK-NEXT: and %s1, %s0, (32)1 56*5ceb0bc7SSimon Moll; CHECK-NEXT: srl %s0, %s0, 32 57*5ceb0bc7SSimon Moll; CHECK-NEXT: or %s0, %s0, %s1 58*5ceb0bc7SSimon Moll; CHECK-NEXT: lea %s1, 256 59*5ceb0bc7SSimon Moll; CHECK-NEXT: lvl %s1 60*5ceb0bc7SSimon Moll; CHECK-NEXT: vbrd %v0, %s0 61*5ceb0bc7SSimon Moll; CHECK-NEXT: b.l.t (, %s10) 62*5ceb0bc7SSimon Moll %val = insertelement <512 x float> undef, float 0.e+00, i32 0 63*5ceb0bc7SSimon Moll %ret = shufflevector <512 x float> %val, <512 x float> undef, <512 x i32> zeroinitializer 64*5ceb0bc7SSimon Moll ret <512 x float> %ret 65*5ceb0bc7SSimon Moll} 66