1a65ccc1bSUlrich Weigand; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 2a65ccc1bSUlrich Weigand; Test 128-bit addition in vector registers on z13 and later 3a65ccc1bSUlrich Weigand; 4a65ccc1bSUlrich Weigand; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s 5*8424bf20SUlrich Weigand; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=arch15 | FileCheck %s 6a65ccc1bSUlrich Weigand 7a65ccc1bSUlrich Weiganddefine i128 @f1(i128 %a, i128 %b) { 8a65ccc1bSUlrich Weigand; CHECK-LABEL: f1: 9a65ccc1bSUlrich Weigand; CHECK: # %bb.0: 10a65ccc1bSUlrich Weigand; CHECK-NEXT: vl %v0, 0(%r4), 3 11a65ccc1bSUlrich Weigand; CHECK-NEXT: vl %v1, 0(%r3), 3 12a65ccc1bSUlrich Weigand; CHECK-NEXT: vaq %v0, %v1, %v0 13a65ccc1bSUlrich Weigand; CHECK-NEXT: vst %v0, 0(%r2), 3 14a65ccc1bSUlrich Weigand; CHECK-NEXT: br %r14 15a65ccc1bSUlrich Weigand %res = add i128 %a, %b 16a65ccc1bSUlrich Weigand ret i128 %res 17a65ccc1bSUlrich Weigand} 18