xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/vwmacc-sdnode.ll (revision d89d45ca9a6e51be388a6ff3893d59e54748b928) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+v -target-abi=ilp32 \
3; RUN:     -verify-machineinstrs < %s | FileCheck %s
4; RUN: llc -mtriple=riscv64 -mattr=+v -target-abi=lp64 \
5; RUN:     -verify-machineinstrs < %s | FileCheck %s
6
7define <vscale x 1 x i64> @vwmacc_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, <vscale x 1 x i64> %vc) {
8; CHECK-LABEL: vwmacc_vv_nxv1i32:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
11; CHECK-NEXT:    vwmacc.vv v10, v8, v9
12; CHECK-NEXT:    vmv1r.v v8, v10
13; CHECK-NEXT:    ret
14  %vd = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
15  %ve = sext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
16
17  %x = mul <vscale x 1 x i64> %vd, %ve
18  %y = add <vscale x 1 x i64> %x, %vc
19  ret <vscale x 1 x i64> %y
20}
21
22define <vscale x 1 x i64> @vwmacc_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b, <vscale x 1 x i64> %vc) {
23; CHECK-LABEL: vwmacc_vx_nxv1i32:
24; CHECK:       # %bb.0:
25; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
26; CHECK-NEXT:    vwmacc.vx v9, a0, v8
27; CHECK-NEXT:    vmv1r.v v8, v9
28; CHECK-NEXT:    ret
29  %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
30  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
31  %vd = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
32  %ve = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
33
34  %x = mul <vscale x 1 x i64> %vd, %ve
35  %y = add <vscale x 1 x i64> %x, %vc
36  ret <vscale x 1 x i64> %y
37}
38
39define <vscale x 1 x i64> @vwmaccu_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, <vscale x 1 x i64> %vc) {
40; CHECK-LABEL: vwmaccu_vv_nxv1i32:
41; CHECK:       # %bb.0:
42; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
43; CHECK-NEXT:    vwmaccu.vv v10, v8, v9
44; CHECK-NEXT:    vmv1r.v v8, v10
45; CHECK-NEXT:    ret
46  %vd = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
47  %ve = zext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
48
49  %x = mul <vscale x 1 x i64> %vd, %ve
50  %y = add <vscale x 1 x i64> %x, %vc
51  ret <vscale x 1 x i64> %y
52}
53
54define <vscale x 1 x i64> @vwmaccu_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b, <vscale x 1 x i64> %vc) {
55; CHECK-LABEL: vwmaccu_vx_nxv1i32:
56; CHECK:       # %bb.0:
57; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
58; CHECK-NEXT:    vwmaccu.vx v9, a0, v8
59; CHECK-NEXT:    vmv1r.v v8, v9
60; CHECK-NEXT:    ret
61  %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
62  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
63  %vd = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
64  %ve = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
65
66  %x = mul <vscale x 1 x i64> %vd, %ve
67  %y = add <vscale x 1 x i64> %x, %vc
68  ret <vscale x 1 x i64> %y
69}
70
71define <vscale x 1 x i64> @vwmaccsu_vv_nxv1i32(<vscale x 1 x i32> %va, <vscale x 1 x i32> %vb, <vscale x 1 x i64> %vc) {
72; CHECK-LABEL: vwmaccsu_vv_nxv1i32:
73; CHECK:       # %bb.0:
74; CHECK-NEXT:    vsetvli a0, zero, e32, mf2, ta, ma
75; CHECK-NEXT:    vwmaccsu.vv v10, v9, v8
76; CHECK-NEXT:    vmv1r.v v8, v10
77; CHECK-NEXT:    ret
78  %vd = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
79  %ve = sext <vscale x 1 x i32> %vb to <vscale x 1 x i64>
80
81  %x = mul <vscale x 1 x i64> %vd, %ve
82  %y = add <vscale x 1 x i64> %x, %vc
83  ret <vscale x 1 x i64> %y
84}
85
86define <vscale x 1 x i64> @vwmaccsu_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b, <vscale x 1 x i64> %vc) {
87; CHECK-LABEL: vwmaccsu_vx_nxv1i32:
88; CHECK:       # %bb.0:
89; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
90; CHECK-NEXT:    vwmaccsu.vx v9, a0, v8
91; CHECK-NEXT:    vmv1r.v v8, v9
92; CHECK-NEXT:    ret
93  %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
94  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
95  %vd = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
96  %ve = sext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
97
98  %x = mul <vscale x 1 x i64> %vd, %ve
99  %y = add <vscale x 1 x i64> %x, %vc
100  ret <vscale x 1 x i64> %y
101}
102
103define <vscale x 1 x i64> @vwmaccus_vx_nxv1i32(<vscale x 1 x i32> %va, i32 %b, <vscale x 1 x i64> %vc) {
104; CHECK-LABEL: vwmaccus_vx_nxv1i32:
105; CHECK:       # %bb.0:
106; CHECK-NEXT:    vsetvli a1, zero, e32, mf2, ta, ma
107; CHECK-NEXT:    vwmaccus.vx v9, a0, v8
108; CHECK-NEXT:    vmv1r.v v8, v9
109; CHECK-NEXT:    ret
110  %head = insertelement <vscale x 1 x i32> poison, i32 %b, i32 0
111  %splat = shufflevector <vscale x 1 x i32> %head, <vscale x 1 x i32> poison, <vscale x 1 x i32> zeroinitializer
112  %vd = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
113  %ve = zext <vscale x 1 x i32> %splat to <vscale x 1 x i64>
114
115  %x = mul <vscale x 1 x i64> %vd, %ve
116  %y = add <vscale x 1 x i64> %x, %vc
117  ret <vscale x 1 x i64> %y
118}
119
120define <vscale x 2 x i64> @vwmacc_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, <vscale x 2 x i64> %vc) {
121; CHECK-LABEL: vwmacc_vv_nxv2i32:
122; CHECK:       # %bb.0:
123; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
124; CHECK-NEXT:    vwmacc.vv v10, v8, v9
125; CHECK-NEXT:    vmv2r.v v8, v10
126; CHECK-NEXT:    ret
127  %vd = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
128  %ve = sext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
129
130  %x = mul <vscale x 2 x i64> %vd, %ve
131  %y = add <vscale x 2 x i64> %x, %vc
132  ret <vscale x 2 x i64> %y
133}
134
135define <vscale x 2 x i64> @vwmacc_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b, <vscale x 2 x i64> %vc) {
136; CHECK-LABEL: vwmacc_vx_nxv2i32:
137; CHECK:       # %bb.0:
138; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
139; CHECK-NEXT:    vwmacc.vx v10, a0, v8
140; CHECK-NEXT:    vmv2r.v v8, v10
141; CHECK-NEXT:    ret
142  %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
143  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
144  %vd = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
145  %ve = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
146
147  %x = mul <vscale x 2 x i64> %vd, %ve
148  %y = add <vscale x 2 x i64> %x, %vc
149  ret <vscale x 2 x i64> %y
150}
151
152define <vscale x 2 x i64> @vwmaccu_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, <vscale x 2 x i64> %vc) {
153; CHECK-LABEL: vwmaccu_vv_nxv2i32:
154; CHECK:       # %bb.0:
155; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
156; CHECK-NEXT:    vwmaccu.vv v10, v8, v9
157; CHECK-NEXT:    vmv2r.v v8, v10
158; CHECK-NEXT:    ret
159  %vd = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
160  %ve = zext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
161
162  %x = mul <vscale x 2 x i64> %vd, %ve
163  %y = add <vscale x 2 x i64> %x, %vc
164  ret <vscale x 2 x i64> %y
165}
166
167define <vscale x 2 x i64> @vwmaccu_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b, <vscale x 2 x i64> %vc) {
168; CHECK-LABEL: vwmaccu_vx_nxv2i32:
169; CHECK:       # %bb.0:
170; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
171; CHECK-NEXT:    vwmaccu.vx v10, a0, v8
172; CHECK-NEXT:    vmv2r.v v8, v10
173; CHECK-NEXT:    ret
174  %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
175  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
176  %vd = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
177  %ve = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
178
179  %x = mul <vscale x 2 x i64> %vd, %ve
180  %y = add <vscale x 2 x i64> %x, %vc
181  ret <vscale x 2 x i64> %y
182}
183
184define <vscale x 2 x i64> @vwmaccsu_vv_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, <vscale x 2 x i64> %vc) {
185; CHECK-LABEL: vwmaccsu_vv_nxv2i32:
186; CHECK:       # %bb.0:
187; CHECK-NEXT:    vsetvli a0, zero, e32, m1, ta, ma
188; CHECK-NEXT:    vwmaccsu.vv v10, v9, v8
189; CHECK-NEXT:    vmv2r.v v8, v10
190; CHECK-NEXT:    ret
191  %vd = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
192  %ve = sext <vscale x 2 x i32> %vb to <vscale x 2 x i64>
193
194  %x = mul <vscale x 2 x i64> %vd, %ve
195  %y = add <vscale x 2 x i64> %x, %vc
196  ret <vscale x 2 x i64> %y
197}
198
199define <vscale x 2 x i64> @vwmaccsu_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b, <vscale x 2 x i64> %vc) {
200; CHECK-LABEL: vwmaccsu_vx_nxv2i32:
201; CHECK:       # %bb.0:
202; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
203; CHECK-NEXT:    vwmaccsu.vx v10, a0, v8
204; CHECK-NEXT:    vmv2r.v v8, v10
205; CHECK-NEXT:    ret
206  %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
207  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
208  %vd = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
209  %ve = sext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
210
211  %x = mul <vscale x 2 x i64> %vd, %ve
212  %y = add <vscale x 2 x i64> %x, %vc
213  ret <vscale x 2 x i64> %y
214}
215
216define <vscale x 2 x i64> @vwmaccus_vx_nxv2i32(<vscale x 2 x i32> %va, i32 %b, <vscale x 2 x i64> %vc) {
217; CHECK-LABEL: vwmaccus_vx_nxv2i32:
218; CHECK:       # %bb.0:
219; CHECK-NEXT:    vsetvli a1, zero, e32, m1, ta, ma
220; CHECK-NEXT:    vwmaccus.vx v10, a0, v8
221; CHECK-NEXT:    vmv2r.v v8, v10
222; CHECK-NEXT:    ret
223  %head = insertelement <vscale x 2 x i32> poison, i32 %b, i32 0
224  %splat = shufflevector <vscale x 2 x i32> %head, <vscale x 2 x i32> poison, <vscale x 2 x i32> zeroinitializer
225  %vd = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
226  %ve = zext <vscale x 2 x i32> %splat to <vscale x 2 x i64>
227
228  %x = mul <vscale x 2 x i64> %vd, %ve
229  %y = add <vscale x 2 x i64> %x, %vc
230  ret <vscale x 2 x i64> %y
231}
232
233define <vscale x 4 x i64> @vwmacc_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb, <vscale x 4 x i64> %vc) {
234; CHECK-LABEL: vwmacc_vv_nxv4i32:
235; CHECK:       # %bb.0:
236; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
237; CHECK-NEXT:    vwmacc.vv v12, v8, v10
238; CHECK-NEXT:    vmv4r.v v8, v12
239; CHECK-NEXT:    ret
240  %vd = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
241  %ve = sext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
242
243  %x = mul <vscale x 4 x i64> %vd, %ve
244  %y = add <vscale x 4 x i64> %x, %vc
245  ret <vscale x 4 x i64> %y
246}
247
248define <vscale x 4 x i64> @vwmacc_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b, <vscale x 4 x i64> %vc) {
249; CHECK-LABEL: vwmacc_vx_nxv4i32:
250; CHECK:       # %bb.0:
251; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
252; CHECK-NEXT:    vwmacc.vx v12, a0, v8
253; CHECK-NEXT:    vmv4r.v v8, v12
254; CHECK-NEXT:    ret
255  %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
256  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
257  %vd = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
258  %ve = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
259
260  %x = mul <vscale x 4 x i64> %vd, %ve
261  %y = add <vscale x 4 x i64> %x, %vc
262  ret <vscale x 4 x i64> %y
263}
264
265define <vscale x 4 x i64> @vwmaccu_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb, <vscale x 4 x i64> %vc) {
266; CHECK-LABEL: vwmaccu_vv_nxv4i32:
267; CHECK:       # %bb.0:
268; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
269; CHECK-NEXT:    vwmaccu.vv v12, v8, v10
270; CHECK-NEXT:    vmv4r.v v8, v12
271; CHECK-NEXT:    ret
272  %vd = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
273  %ve = zext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
274
275  %x = mul <vscale x 4 x i64> %vd, %ve
276  %y = add <vscale x 4 x i64> %x, %vc
277  ret <vscale x 4 x i64> %y
278}
279
280define <vscale x 4 x i64> @vwmaccu_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b, <vscale x 4 x i64> %vc) {
281; CHECK-LABEL: vwmaccu_vx_nxv4i32:
282; CHECK:       # %bb.0:
283; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
284; CHECK-NEXT:    vwmaccu.vx v12, a0, v8
285; CHECK-NEXT:    vmv4r.v v8, v12
286; CHECK-NEXT:    ret
287  %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
288  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
289  %vd = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
290  %ve = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
291
292  %x = mul <vscale x 4 x i64> %vd, %ve
293  %y = add <vscale x 4 x i64> %x, %vc
294  ret <vscale x 4 x i64> %y
295}
296
297define <vscale x 4 x i64> @vwmaccsu_vv_nxv4i32(<vscale x 4 x i32> %va, <vscale x 4 x i32> %vb, <vscale x 4 x i64> %vc) {
298; CHECK-LABEL: vwmaccsu_vv_nxv4i32:
299; CHECK:       # %bb.0:
300; CHECK-NEXT:    vsetvli a0, zero, e32, m2, ta, ma
301; CHECK-NEXT:    vwmaccsu.vv v12, v10, v8
302; CHECK-NEXT:    vmv4r.v v8, v12
303; CHECK-NEXT:    ret
304  %vd = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
305  %ve = sext <vscale x 4 x i32> %vb to <vscale x 4 x i64>
306
307  %x = mul <vscale x 4 x i64> %vd, %ve
308  %y = add <vscale x 4 x i64> %x, %vc
309  ret <vscale x 4 x i64> %y
310}
311
312define <vscale x 4 x i64> @vwmaccsu_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b, <vscale x 4 x i64> %vc) {
313; CHECK-LABEL: vwmaccsu_vx_nxv4i32:
314; CHECK:       # %bb.0:
315; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
316; CHECK-NEXT:    vwmaccsu.vx v12, a0, v8
317; CHECK-NEXT:    vmv4r.v v8, v12
318; CHECK-NEXT:    ret
319  %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
320  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
321  %vd = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
322  %ve = sext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
323
324  %x = mul <vscale x 4 x i64> %vd, %ve
325  %y = add <vscale x 4 x i64> %x, %vc
326  ret <vscale x 4 x i64> %y
327}
328
329define <vscale x 4 x i64> @vwmaccus_vx_nxv4i32(<vscale x 4 x i32> %va, i32 %b, <vscale x 4 x i64> %vc) {
330; CHECK-LABEL: vwmaccus_vx_nxv4i32:
331; CHECK:       # %bb.0:
332; CHECK-NEXT:    vsetvli a1, zero, e32, m2, ta, ma
333; CHECK-NEXT:    vwmaccus.vx v12, a0, v8
334; CHECK-NEXT:    vmv4r.v v8, v12
335; CHECK-NEXT:    ret
336  %head = insertelement <vscale x 4 x i32> poison, i32 %b, i32 0
337  %splat = shufflevector <vscale x 4 x i32> %head, <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer
338  %vd = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
339  %ve = zext <vscale x 4 x i32> %splat to <vscale x 4 x i64>
340
341  %x = mul <vscale x 4 x i64> %vd, %ve
342  %y = add <vscale x 4 x i64> %x, %vc
343  ret <vscale x 4 x i64> %y
344}
345
346define <vscale x 8 x i64> @vwmacc_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i64> %vc) {
347; CHECK-LABEL: vwmacc_vv_nxv8i32:
348; CHECK:       # %bb.0:
349; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
350; CHECK-NEXT:    vwmacc.vv v16, v8, v12
351; CHECK-NEXT:    vmv8r.v v8, v16
352; CHECK-NEXT:    ret
353  %vd = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
354  %ve = sext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
355
356  %x = mul <vscale x 8 x i64> %vd, %ve
357  %y = add <vscale x 8 x i64> %x, %vc
358  ret <vscale x 8 x i64> %y
359}
360
361define <vscale x 8 x i64> @vwmacc_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b, <vscale x 8 x i64> %vc) {
362; CHECK-LABEL: vwmacc_vx_nxv8i32:
363; CHECK:       # %bb.0:
364; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
365; CHECK-NEXT:    vwmacc.vx v16, a0, v8
366; CHECK-NEXT:    vmv8r.v v8, v16
367; CHECK-NEXT:    ret
368  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
369  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
370  %vd = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
371  %ve = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
372
373  %x = mul <vscale x 8 x i64> %vd, %ve
374  %y = add <vscale x 8 x i64> %x, %vc
375  ret <vscale x 8 x i64> %y
376}
377
378define <vscale x 8 x i64> @vwmaccu_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i64> %vc) {
379; CHECK-LABEL: vwmaccu_vv_nxv8i32:
380; CHECK:       # %bb.0:
381; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
382; CHECK-NEXT:    vwmaccu.vv v16, v8, v12
383; CHECK-NEXT:    vmv8r.v v8, v16
384; CHECK-NEXT:    ret
385  %vd = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
386  %ve = zext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
387
388  %x = mul <vscale x 8 x i64> %vd, %ve
389  %y = add <vscale x 8 x i64> %x, %vc
390  ret <vscale x 8 x i64> %y
391}
392
393define <vscale x 8 x i64> @vwmaccu_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b, <vscale x 8 x i64> %vc) {
394; CHECK-LABEL: vwmaccu_vx_nxv8i32:
395; CHECK:       # %bb.0:
396; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
397; CHECK-NEXT:    vwmaccu.vx v16, a0, v8
398; CHECK-NEXT:    vmv8r.v v8, v16
399; CHECK-NEXT:    ret
400  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
401  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
402  %vd = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
403  %ve = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
404
405  %x = mul <vscale x 8 x i64> %vd, %ve
406  %y = add <vscale x 8 x i64> %x, %vc
407  ret <vscale x 8 x i64> %y
408}
409
410define <vscale x 8 x i64> @vwmaccsu_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb, <vscale x 8 x i64> %vc) {
411; CHECK-LABEL: vwmaccsu_vv_nxv8i32:
412; CHECK:       # %bb.0:
413; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
414; CHECK-NEXT:    vwmaccsu.vv v16, v12, v8
415; CHECK-NEXT:    vmv8r.v v8, v16
416; CHECK-NEXT:    ret
417  %vd = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
418  %ve = sext <vscale x 8 x i32> %vb to <vscale x 8 x i64>
419
420  %x = mul <vscale x 8 x i64> %vd, %ve
421  %y = add <vscale x 8 x i64> %x, %vc
422  ret <vscale x 8 x i64> %y
423}
424
425define <vscale x 8 x i64> @vwmaccsu_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b, <vscale x 8 x i64> %vc) {
426; CHECK-LABEL: vwmaccsu_vx_nxv8i32:
427; CHECK:       # %bb.0:
428; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
429; CHECK-NEXT:    vwmaccsu.vx v16, a0, v8
430; CHECK-NEXT:    vmv8r.v v8, v16
431; CHECK-NEXT:    ret
432  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
433  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
434  %vd = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
435  %ve = sext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
436
437  %x = mul <vscale x 8 x i64> %vd, %ve
438  %y = add <vscale x 8 x i64> %x, %vc
439  ret <vscale x 8 x i64> %y
440}
441
442define <vscale x 8 x i64> @vwmaccus_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b, <vscale x 8 x i64> %vc) {
443; CHECK-LABEL: vwmaccus_vx_nxv8i32:
444; CHECK:       # %bb.0:
445; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
446; CHECK-NEXT:    vwmaccus.vx v16, a0, v8
447; CHECK-NEXT:    vmv8r.v v8, v16
448; CHECK-NEXT:    ret
449  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
450  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
451  %vd = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
452  %ve = zext <vscale x 8 x i32> %splat to <vscale x 8 x i64>
453
454  %x = mul <vscale x 8 x i64> %vd, %ve
455  %y = add <vscale x 8 x i64> %x, %vc
456  ret <vscale x 8 x i64> %y
457}
458