xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/vselect-vp-bf16.ll (revision 9d068f7137a2ad732d008df46eb71aadb0cd8a8e) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -mattr=+d,+m,+v,+zvfbfmin -target-abi=ilp32d \
3; RUN:     -verify-machineinstrs < %s | FileCheck %s
4; RUN: llc -mtriple=riscv64 -mattr=+d,+m,+v,+zvfbfmin -target-abi=lp64d \
5; RUN:     -verify-machineinstrs < %s | FileCheck %s
6
7declare <vscale x 1 x bfloat> @llvm.vp.select.nxv1bf16(<vscale x 1 x i1>, <vscale x 1 x bfloat>, <vscale x 1 x bfloat>, i32)
8
9define <vscale x 1 x bfloat> @select_nxv1bf16(<vscale x 1 x i1> %a, <vscale x 1 x bfloat> %b, <vscale x 1 x bfloat> %c, i32 zeroext %evl) {
10; CHECK-LABEL: select_nxv1bf16:
11; CHECK:       # %bb.0:
12; CHECK-NEXT:    vsetvli zero, a0, e16, mf4, ta, ma
13; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
14; CHECK-NEXT:    ret
15  %v = call <vscale x 1 x bfloat> @llvm.vp.select.nxv1bf16(<vscale x 1 x i1> %a, <vscale x 1 x bfloat> %b, <vscale x 1 x bfloat> %c, i32 %evl)
16  ret <vscale x 1 x bfloat> %v
17}
18
19declare <vscale x 2 x bfloat> @llvm.vp.select.nxv2bf16(<vscale x 2 x i1>, <vscale x 2 x bfloat>, <vscale x 2 x bfloat>, i32)
20
21define <vscale x 2 x bfloat> @select_nxv2bf16(<vscale x 2 x i1> %a, <vscale x 2 x bfloat> %b, <vscale x 2 x bfloat> %c, i32 zeroext %evl) {
22; CHECK-LABEL: select_nxv2bf16:
23; CHECK:       # %bb.0:
24; CHECK-NEXT:    vsetvli zero, a0, e16, mf2, ta, ma
25; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
26; CHECK-NEXT:    ret
27  %v = call <vscale x 2 x bfloat> @llvm.vp.select.nxv2bf16(<vscale x 2 x i1> %a, <vscale x 2 x bfloat> %b, <vscale x 2 x bfloat> %c, i32 %evl)
28  ret <vscale x 2 x bfloat> %v
29}
30
31declare <vscale x 4 x bfloat> @llvm.vp.select.nxv4bf16(<vscale x 4 x i1>, <vscale x 4 x bfloat>, <vscale x 4 x bfloat>, i32)
32
33define <vscale x 4 x bfloat> @select_nxv4bf16(<vscale x 4 x i1> %a, <vscale x 4 x bfloat> %b, <vscale x 4 x bfloat> %c, i32 zeroext %evl) {
34; CHECK-LABEL: select_nxv4bf16:
35; CHECK:       # %bb.0:
36; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
37; CHECK-NEXT:    vmerge.vvm v8, v9, v8, v0
38; CHECK-NEXT:    ret
39  %v = call <vscale x 4 x bfloat> @llvm.vp.select.nxv4bf16(<vscale x 4 x i1> %a, <vscale x 4 x bfloat> %b, <vscale x 4 x bfloat> %c, i32 %evl)
40  ret <vscale x 4 x bfloat> %v
41}
42
43declare <vscale x 8 x bfloat> @llvm.vp.select.nxv8bf16(<vscale x 8 x i1>, <vscale x 8 x bfloat>, <vscale x 8 x bfloat>, i32)
44
45define <vscale x 8 x bfloat> @select_nxv8bf16(<vscale x 8 x i1> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %c, i32 zeroext %evl) {
46; CHECK-LABEL: select_nxv8bf16:
47; CHECK:       # %bb.0:
48; CHECK-NEXT:    vsetvli zero, a0, e16, m2, ta, ma
49; CHECK-NEXT:    vmerge.vvm v8, v10, v8, v0
50; CHECK-NEXT:    ret
51  %v = call <vscale x 8 x bfloat> @llvm.vp.select.nxv8bf16(<vscale x 8 x i1> %a, <vscale x 8 x bfloat> %b, <vscale x 8 x bfloat> %c, i32 %evl)
52  ret <vscale x 8 x bfloat> %v
53}
54
55declare <vscale x 16 x bfloat> @llvm.vp.select.nxv16bf16(<vscale x 16 x i1>, <vscale x 16 x bfloat>, <vscale x 16 x bfloat>, i32)
56
57define <vscale x 16 x bfloat> @select_nxv16bf16(<vscale x 16 x i1> %a, <vscale x 16 x bfloat> %b, <vscale x 16 x bfloat> %c, i32 zeroext %evl) {
58; CHECK-LABEL: select_nxv16bf16:
59; CHECK:       # %bb.0:
60; CHECK-NEXT:    vsetvli zero, a0, e16, m4, ta, ma
61; CHECK-NEXT:    vmerge.vvm v8, v12, v8, v0
62; CHECK-NEXT:    ret
63  %v = call <vscale x 16 x bfloat> @llvm.vp.select.nxv16bf16(<vscale x 16 x i1> %a, <vscale x 16 x bfloat> %b, <vscale x 16 x bfloat> %c, i32 %evl)
64  ret <vscale x 16 x bfloat> %v
65}
66
67declare <vscale x 32 x bfloat> @llvm.vp.select.nxv32bf16(<vscale x 32 x i1>, <vscale x 32 x bfloat>, <vscale x 32 x bfloat>, i32)
68
69define <vscale x 32 x bfloat> @select_nxv32bf16(<vscale x 32 x i1> %a, <vscale x 32 x bfloat> %b, <vscale x 32 x bfloat> %c, i32 zeroext %evl) {
70; CHECK-LABEL: select_nxv32bf16:
71; CHECK:       # %bb.0:
72; CHECK-NEXT:    vsetvli zero, a0, e16, m8, ta, ma
73; CHECK-NEXT:    vmerge.vvm v8, v16, v8, v0
74; CHECK-NEXT:    ret
75  %v = call <vscale x 32 x bfloat> @llvm.vp.select.nxv32bf16(<vscale x 32 x i1> %a, <vscale x 32 x bfloat> %b, <vscale x 32 x bfloat> %c, i32 %evl)
76  ret <vscale x 32 x bfloat> %v
77}
78