xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/vp-splice.ll (revision d8d131dfa99762ccdd2116661980b7d0493cd7b5) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple riscv64 -mattr=+f,+d,+v -verify-machineinstrs \
3; RUN:   < %s | FileCheck %s
4
5declare <vscale x 2 x i64> @llvm.experimental.vp.splice.nxv2i64(<vscale x 2 x i64>, <vscale x 2 x i64>, i32, <vscale x 2 x i1>, i32, i32)
6
7declare <vscale x 1 x i64> @llvm.experimental.vp.splice.nxv1i64(<vscale x 1 x i64>, <vscale x 1 x i64>, i32, <vscale x 1 x i1>, i32, i32)
8declare <vscale x 2 x i32> @llvm.experimental.vp.splice.nxv2i32(<vscale x 2 x i32>, <vscale x 2 x i32>, i32, <vscale x 2 x i1>, i32, i32)
9declare <vscale x 4 x i16> @llvm.experimental.vp.splice.nxv4i16(<vscale x 4 x i16>, <vscale x 4 x i16>, i32, <vscale x 4 x i1>, i32, i32)
10declare <vscale x 8 x i8> @llvm.experimental.vp.splice.nxv8i8(<vscale x 8 x i8>, <vscale x 8 x i8>, i32, <vscale x 8 x i1>, i32, i32)
11
12declare <vscale x 1 x double> @llvm.experimental.vp.splice.nxv1f64(<vscale x 1 x double>, <vscale x 1 x double>, i32, <vscale x 1 x i1>, i32, i32)
13declare <vscale x 2 x float> @llvm.experimental.vp.splice.nxv2f32(<vscale x 2 x float>, <vscale x 2 x float>, i32, <vscale x 2 x i1>, i32, i32)
14
15declare <vscale x 16 x i64> @llvm.experimental.vp.splice.nxv16i64(<vscale x 16 x i64>, <vscale x 16 x i64>, i32, <vscale x 16 x i1>, i32, i32)
16
17define <vscale x 2 x i64> @test_vp_splice_nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
18; CHECK-LABEL: test_vp_splice_nxv2i64:
19; CHECK:       # %bb.0:
20; CHECK-NEXT:    addi a0, a0, -5
21; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
22; CHECK-NEXT:    vslidedown.vi v8, v8, 5
23; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
24; CHECK-NEXT:    vslideup.vx v8, v10, a0
25; CHECK-NEXT:    ret
26  %v = call <vscale x 2 x i64> @llvm.experimental.vp.splice.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, i32 5, <vscale x 2 x i1> splat (i1 1), i32 %evla, i32 %evlb)
27  ret <vscale x 2 x i64> %v
28}
29
30define <vscale x 2 x i64> @test_vp_splice_nxv2i64_negative_offset(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
31; CHECK-LABEL: test_vp_splice_nxv2i64_negative_offset:
32; CHECK:       # %bb.0:
33; CHECK-NEXT:    addi a0, a0, -5
34; CHECK-NEXT:    vsetivli zero, 5, e64, m2, ta, ma
35; CHECK-NEXT:    vslidedown.vx v8, v8, a0
36; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, ma
37; CHECK-NEXT:    vslideup.vi v8, v10, 5
38; CHECK-NEXT:    ret
39  %v = call <vscale x 2 x i64> @llvm.experimental.vp.splice.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, i32 -5, <vscale x 2 x i1> splat (i1 1), i32 %evla, i32 %evlb)
40  ret <vscale x 2 x i64> %v
41}
42
43define <vscale x 2 x i64> @test_vp_splice_nxv2i64_masked(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) {
44; CHECK-LABEL: test_vp_splice_nxv2i64_masked:
45; CHECK:       # %bb.0:
46; CHECK-NEXT:    addi a0, a0, -5
47; CHECK-NEXT:    vsetvli zero, a0, e64, m2, ta, ma
48; CHECK-NEXT:    vslidedown.vi v8, v8, 5, v0.t
49; CHECK-NEXT:    vsetvli zero, a1, e64, m2, ta, mu
50; CHECK-NEXT:    vslideup.vx v8, v10, a0, v0.t
51; CHECK-NEXT:    ret
52  %v = call <vscale x 2 x i64> @llvm.experimental.vp.splice.nxv2i64(<vscale x 2 x i64> %va, <vscale x 2 x i64> %vb, i32 5, <vscale x 2 x i1> %mask, i32 %evla, i32 %evlb)
53  ret <vscale x 2 x i64> %v
54}
55
56define <vscale x 1 x i64> @test_vp_splice_nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
57; CHECK-LABEL: test_vp_splice_nxv1i64:
58; CHECK:       # %bb.0:
59; CHECK-NEXT:    addi a0, a0, -5
60; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
61; CHECK-NEXT:    vslidedown.vi v8, v8, 5
62; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
63; CHECK-NEXT:    vslideup.vx v8, v9, a0
64; CHECK-NEXT:    ret
65  %v = call <vscale x 1 x i64> @llvm.experimental.vp.splice.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, i32 5, <vscale x 1 x i1> splat (i1 1), i32 %evla, i32 %evlb)
66  ret <vscale x 1 x i64> %v
67}
68
69define <vscale x 1 x i64> @test_vp_splice_nxv1i64_negative_offset(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
70; CHECK-LABEL: test_vp_splice_nxv1i64_negative_offset:
71; CHECK:       # %bb.0:
72; CHECK-NEXT:    addi a0, a0, -5
73; CHECK-NEXT:    vsetivli zero, 5, e64, m1, ta, ma
74; CHECK-NEXT:    vslidedown.vx v8, v8, a0
75; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
76; CHECK-NEXT:    vslideup.vi v8, v9, 5
77; CHECK-NEXT:    ret
78  %v = call <vscale x 1 x i64> @llvm.experimental.vp.splice.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, i32 -5, <vscale x 1 x i1> splat (i1 1), i32 %evla, i32 %evlb)
79  ret <vscale x 1 x i64> %v
80}
81
82define <vscale x 1 x i64> @test_vp_splice_nxv1i64_masked(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, <vscale x 1 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) {
83; CHECK-LABEL: test_vp_splice_nxv1i64_masked:
84; CHECK:       # %bb.0:
85; CHECK-NEXT:    addi a0, a0, -5
86; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
87; CHECK-NEXT:    vslidedown.vi v8, v8, 5, v0.t
88; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, mu
89; CHECK-NEXT:    vslideup.vx v8, v9, a0, v0.t
90; CHECK-NEXT:    ret
91  %v = call <vscale x 1 x i64> @llvm.experimental.vp.splice.nxv1i64(<vscale x 1 x i64> %va, <vscale x 1 x i64> %vb, i32 5, <vscale x 1 x i1> %mask, i32 %evla, i32 %evlb)
92  ret <vscale x 1 x i64> %v
93}
94
95define <vscale x 2 x i32> @test_vp_splice_nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
96; CHECK-LABEL: test_vp_splice_nxv2i32:
97; CHECK:       # %bb.0:
98; CHECK-NEXT:    addi a0, a0, -5
99; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
100; CHECK-NEXT:    vslidedown.vi v8, v8, 5
101; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
102; CHECK-NEXT:    vslideup.vx v8, v9, a0
103; CHECK-NEXT:    ret
104  %v = call <vscale x 2 x i32> @llvm.experimental.vp.splice.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, i32 5, <vscale x 2 x i1> splat (i1 1), i32 %evla, i32 %evlb)
105  ret <vscale x 2 x i32> %v
106}
107
108define <vscale x 2 x i32> @test_vp_splice_nxv2i32_negative_offset(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
109; CHECK-LABEL: test_vp_splice_nxv2i32_negative_offset:
110; CHECK:       # %bb.0:
111; CHECK-NEXT:    addi a0, a0, -5
112; CHECK-NEXT:    vsetivli zero, 5, e32, m1, ta, ma
113; CHECK-NEXT:    vslidedown.vx v8, v8, a0
114; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
115; CHECK-NEXT:    vslideup.vi v8, v9, 5
116; CHECK-NEXT:    ret
117  %v = call <vscale x 2 x i32> @llvm.experimental.vp.splice.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, i32 -5, <vscale x 2 x i1> splat (i1 1), i32 %evla, i32 %evlb)
118  ret <vscale x 2 x i32> %v
119}
120
121define <vscale x 2 x i32> @test_vp_splice_nxv2i32_masked(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) {
122; CHECK-LABEL: test_vp_splice_nxv2i32_masked:
123; CHECK:       # %bb.0:
124; CHECK-NEXT:    addi a0, a0, -5
125; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
126; CHECK-NEXT:    vslidedown.vi v8, v8, 5, v0.t
127; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, mu
128; CHECK-NEXT:    vslideup.vx v8, v9, a0, v0.t
129; CHECK-NEXT:    ret
130  %v = call <vscale x 2 x i32> @llvm.experimental.vp.splice.nxv2i32(<vscale x 2 x i32> %va, <vscale x 2 x i32> %vb, i32 5, <vscale x 2 x i1> %mask, i32 %evla, i32 %evlb)
131  ret <vscale x 2 x i32> %v
132}
133
134define <vscale x 4 x i16> @test_vp_splice_nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
135; CHECK-LABEL: test_vp_splice_nxv4i16:
136; CHECK:       # %bb.0:
137; CHECK-NEXT:    addi a0, a0, -5
138; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
139; CHECK-NEXT:    vslidedown.vi v8, v8, 5
140; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
141; CHECK-NEXT:    vslideup.vx v8, v9, a0
142; CHECK-NEXT:    ret
143  %v = call <vscale x 4 x i16> @llvm.experimental.vp.splice.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb, i32 5, <vscale x 4 x i1> splat (i1 1), i32 %evla, i32 %evlb)
144  ret <vscale x 4 x i16> %v
145}
146
147define <vscale x 4 x i16> @test_vp_splice_nxv4i16_negative_offset(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
148; CHECK-LABEL: test_vp_splice_nxv4i16_negative_offset:
149; CHECK:       # %bb.0:
150; CHECK-NEXT:    addi a0, a0, -5
151; CHECK-NEXT:    vsetivli zero, 5, e16, m1, ta, ma
152; CHECK-NEXT:    vslidedown.vx v8, v8, a0
153; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, ma
154; CHECK-NEXT:    vslideup.vi v8, v9, 5
155; CHECK-NEXT:    ret
156  %v = call <vscale x 4 x i16> @llvm.experimental.vp.splice.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb, i32 -5, <vscale x 4 x i1> splat (i1 1), i32 %evla, i32 %evlb)
157  ret <vscale x 4 x i16> %v
158}
159
160define <vscale x 4 x i16> @test_vp_splice_nxv4i16_masked(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb, <vscale x 4 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) {
161; CHECK-LABEL: test_vp_splice_nxv4i16_masked:
162; CHECK:       # %bb.0:
163; CHECK-NEXT:    addi a0, a0, -5
164; CHECK-NEXT:    vsetvli zero, a0, e16, m1, ta, ma
165; CHECK-NEXT:    vslidedown.vi v8, v8, 5, v0.t
166; CHECK-NEXT:    vsetvli zero, a1, e16, m1, ta, mu
167; CHECK-NEXT:    vslideup.vx v8, v9, a0, v0.t
168; CHECK-NEXT:    ret
169  %v = call <vscale x 4 x i16> @llvm.experimental.vp.splice.nxv4i16(<vscale x 4 x i16> %va, <vscale x 4 x i16> %vb, i32 5, <vscale x 4 x i1> %mask, i32 %evla, i32 %evlb)
170  ret <vscale x 4 x i16> %v
171}
172
173define <vscale x 8 x i8> @test_vp_splice_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
174; CHECK-LABEL: test_vp_splice_nxv8i8:
175; CHECK:       # %bb.0:
176; CHECK-NEXT:    addi a0, a0, -5
177; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
178; CHECK-NEXT:    vslidedown.vi v8, v8, 5
179; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
180; CHECK-NEXT:    vslideup.vx v8, v9, a0
181; CHECK-NEXT:    ret
182  %v = call <vscale x 8 x i8> @llvm.experimental.vp.splice.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, i32 5, <vscale x 8 x i1> splat (i1 1), i32 %evla, i32 %evlb)
183  ret <vscale x 8 x i8> %v
184}
185
186define <vscale x 8 x i8> @test_vp_splice_nxv8i8_negative_offset(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
187; CHECK-LABEL: test_vp_splice_nxv8i8_negative_offset:
188; CHECK:       # %bb.0:
189; CHECK-NEXT:    addi a0, a0, -5
190; CHECK-NEXT:    vsetivli zero, 5, e8, m1, ta, ma
191; CHECK-NEXT:    vslidedown.vx v8, v8, a0
192; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, ma
193; CHECK-NEXT:    vslideup.vi v8, v9, 5
194; CHECK-NEXT:    ret
195  %v = call <vscale x 8 x i8> @llvm.experimental.vp.splice.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, i32 -5, <vscale x 8 x i1> splat (i1 1), i32 %evla, i32 %evlb)
196  ret <vscale x 8 x i8> %v
197}
198
199define <vscale x 8 x i8> @test_vp_splice_nxv8i8_masked(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, <vscale x 8 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) {
200; CHECK-LABEL: test_vp_splice_nxv8i8_masked:
201; CHECK:       # %bb.0:
202; CHECK-NEXT:    addi a0, a0, -5
203; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, ma
204; CHECK-NEXT:    vslidedown.vi v8, v8, 5, v0.t
205; CHECK-NEXT:    vsetvli zero, a1, e8, m1, ta, mu
206; CHECK-NEXT:    vslideup.vx v8, v9, a0, v0.t
207; CHECK-NEXT:    ret
208  %v = call <vscale x 8 x i8> @llvm.experimental.vp.splice.nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb, i32 5, <vscale x 8 x i1> %mask, i32 %evla, i32 %evlb)
209  ret <vscale x 8 x i8> %v
210}
211
212define <vscale x 1 x double> @test_vp_splice_nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
213; CHECK-LABEL: test_vp_splice_nxv1f64:
214; CHECK:       # %bb.0:
215; CHECK-NEXT:    addi a0, a0, -5
216; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
217; CHECK-NEXT:    vslidedown.vi v8, v8, 5
218; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
219; CHECK-NEXT:    vslideup.vx v8, v9, a0
220; CHECK-NEXT:    ret
221  %v = call <vscale x 1 x double> @llvm.experimental.vp.splice.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, i32 5, <vscale x 1 x i1> splat (i1 1), i32 %evla, i32 %evlb)
222  ret <vscale x 1 x double> %v
223}
224
225define <vscale x 1 x double> @test_vp_splice_nxv1f64_negative_offset(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
226; CHECK-LABEL: test_vp_splice_nxv1f64_negative_offset:
227; CHECK:       # %bb.0:
228; CHECK-NEXT:    addi a0, a0, -5
229; CHECK-NEXT:    vsetivli zero, 5, e64, m1, ta, ma
230; CHECK-NEXT:    vslidedown.vx v8, v8, a0
231; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, ma
232; CHECK-NEXT:    vslideup.vi v8, v9, 5
233; CHECK-NEXT:    ret
234  %v = call <vscale x 1 x double> @llvm.experimental.vp.splice.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, i32 -5, <vscale x 1 x i1> splat (i1 1), i32 %evla, i32 %evlb)
235  ret <vscale x 1 x double> %v
236}
237
238define <vscale x 1 x double> @test_vp_splice_nxv1f64_masked(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, <vscale x 1 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) {
239; CHECK-LABEL: test_vp_splice_nxv1f64_masked:
240; CHECK:       # %bb.0:
241; CHECK-NEXT:    addi a0, a0, -5
242; CHECK-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
243; CHECK-NEXT:    vslidedown.vi v8, v8, 5, v0.t
244; CHECK-NEXT:    vsetvli zero, a1, e64, m1, ta, mu
245; CHECK-NEXT:    vslideup.vx v8, v9, a0, v0.t
246; CHECK-NEXT:    ret
247  %v = call <vscale x 1 x double> @llvm.experimental.vp.splice.nxv1f64(<vscale x 1 x double> %va, <vscale x 1 x double> %vb, i32 5, <vscale x 1 x i1> %mask, i32 %evla, i32 %evlb)
248  ret <vscale x 1 x double> %v
249}
250
251define <vscale x 2 x float> @test_vp_splice_nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
252; CHECK-LABEL: test_vp_splice_nxv2f32:
253; CHECK:       # %bb.0:
254; CHECK-NEXT:    addi a0, a0, -5
255; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
256; CHECK-NEXT:    vslidedown.vi v8, v8, 5
257; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
258; CHECK-NEXT:    vslideup.vx v8, v9, a0
259; CHECK-NEXT:    ret
260  %v = call <vscale x 2 x float> @llvm.experimental.vp.splice.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, i32 5, <vscale x 2 x i1> splat (i1 1), i32 %evla, i32 %evlb)
261  ret <vscale x 2 x float> %v
262}
263
264define <vscale x 2 x float> @test_vp_splice_nxv2f32_negative_offset(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, i32 zeroext %evla, i32 zeroext %evlb) {
265; CHECK-LABEL: test_vp_splice_nxv2f32_negative_offset:
266; CHECK:       # %bb.0:
267; CHECK-NEXT:    addi a0, a0, -5
268; CHECK-NEXT:    vsetivli zero, 5, e32, m1, ta, ma
269; CHECK-NEXT:    vslidedown.vx v8, v8, a0
270; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, ma
271; CHECK-NEXT:    vslideup.vi v8, v9, 5
272; CHECK-NEXT:    ret
273  %v = call <vscale x 2 x float> @llvm.experimental.vp.splice.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, i32 -5, <vscale x 2 x i1> splat (i1 1), i32 %evla, i32 %evlb)
274  ret <vscale x 2 x float> %v
275}
276
277define <vscale x 2 x float> @test_vp_splice_nxv2f32_masked(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, <vscale x 2 x i1> %mask, i32 zeroext %evla, i32 zeroext %evlb) {
278; CHECK-LABEL: test_vp_splice_nxv2f32_masked:
279; CHECK:       # %bb.0:
280; CHECK-NEXT:    addi a0, a0, -5
281; CHECK-NEXT:    vsetvli zero, a0, e32, m1, ta, ma
282; CHECK-NEXT:    vslidedown.vi v8, v8, 5, v0.t
283; CHECK-NEXT:    vsetvli zero, a1, e32, m1, ta, mu
284; CHECK-NEXT:    vslideup.vx v8, v9, a0, v0.t
285; CHECK-NEXT:    ret
286  %v = call <vscale x 2 x float> @llvm.experimental.vp.splice.nxv2f32(<vscale x 2 x float> %va, <vscale x 2 x float> %vb, i32 5, <vscale x 2 x i1> %mask, i32 %evla, i32 %evlb)
287  ret <vscale x 2 x float> %v
288}
289