xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/vaaddu-sdnode.ll (revision 97982a8c605fac7c86d02e641a6cd7898b3ca343) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
2; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
3; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
4
5define <vscale x 8 x i8> @vaaddu_vv_nxv8i8_floor(<vscale x 8 x i8> %x, <vscale x 8 x i8> %y) {
6; CHECK-LABEL: vaaddu_vv_nxv8i8_floor:
7; CHECK:       # %bb.0:
8; CHECK-NEXT:    csrwi vxrm, 2
9; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
10; CHECK-NEXT:    vaaddu.vv v8, v8, v9
11; CHECK-NEXT:    ret
12  %xzv = zext <vscale x 8 x i8> %x to <vscale x 8 x i16>
13  %yzv = zext <vscale x 8 x i8> %y to <vscale x 8 x i16>
14  %add = add nuw nsw <vscale x 8 x i16> %xzv, %yzv
15  %div = lshr <vscale x 8 x i16> %add, splat (i16 1)
16  %ret = trunc <vscale x 8 x i16> %div to <vscale x 8 x i8>
17  ret <vscale x 8 x i8> %ret
18}
19
20define <vscale x 8 x i8> @vaaddu_vx_nxv8i8_floor(<vscale x 8 x i8> %x, i8 %y) {
21; CHECK-LABEL: vaaddu_vx_nxv8i8_floor:
22; CHECK:       # %bb.0:
23; CHECK-NEXT:    csrwi vxrm, 2
24; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
25; CHECK-NEXT:    vaaddu.vx v8, v8, a0
26; CHECK-NEXT:    ret
27  %xzv = zext <vscale x 8 x i8> %x to <vscale x 8 x i16>
28  %yhead = insertelement <vscale x 8 x i8> poison, i8 %y, i32 0
29  %ysplat = shufflevector <vscale x 8 x i8> %yhead, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
30  %yzv = zext <vscale x 8 x i8> %ysplat to <vscale x 8 x i16>
31  %add = add nuw nsw <vscale x 8 x i16> %xzv, %yzv
32  %div = lshr <vscale x 8 x i16> %add, splat (i16 1)
33  %ret = trunc <vscale x 8 x i16> %div to <vscale x 8 x i8>
34  ret <vscale x 8 x i8> %ret
35}
36
37define <vscale x 8 x i8> @vaaddu_vv_nxv8i8_floor_sexti16(<vscale x 8 x i8> %x, <vscale x 8 x i8> %y) {
38; CHECK-LABEL: vaaddu_vv_nxv8i8_floor_sexti16:
39; CHECK:       # %bb.0:
40; CHECK-NEXT:    csrwi vxrm, 2
41; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
42; CHECK-NEXT:    vaadd.vv v8, v8, v9
43; CHECK-NEXT:    ret
44  %xzv = sext <vscale x 8 x i8> %x to <vscale x 8 x i16>
45  %yzv = sext <vscale x 8 x i8> %y to <vscale x 8 x i16>
46  %add = add nuw nsw <vscale x 8 x i16> %xzv, %yzv
47  %div = lshr <vscale x 8 x i16> %add, splat (i16 1)
48  %ret = trunc <vscale x 8 x i16> %div to <vscale x 8 x i8>
49  ret <vscale x 8 x i8> %ret
50}
51
52define <vscale x 8 x i8> @vaaddu_vv_nxv8i8_floor_zexti32(<vscale x 8 x i8> %x, <vscale x 8 x i8> %y) {
53; CHECK-LABEL: vaaddu_vv_nxv8i8_floor_zexti32:
54; CHECK:       # %bb.0:
55; CHECK-NEXT:    csrwi vxrm, 2
56; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
57; CHECK-NEXT:    vaaddu.vv v8, v8, v9
58; CHECK-NEXT:    ret
59  %xzv = zext <vscale x 8 x i8> %x to <vscale x 8 x i32>
60  %yzv = zext <vscale x 8 x i8> %y to <vscale x 8 x i32>
61  %add = add nuw nsw <vscale x 8 x i32> %xzv, %yzv
62  %div = lshr <vscale x 8 x i32> %add, splat (i32 1)
63  %ret = trunc <vscale x 8 x i32> %div to <vscale x 8 x i8>
64  ret <vscale x 8 x i8> %ret
65}
66
67define <vscale x 8 x i8> @vaaddu_vv_nxv8i8_floor_lshr2(<vscale x 8 x i8> %x, <vscale x 8 x i8> %y) {
68; CHECK-LABEL: vaaddu_vv_nxv8i8_floor_lshr2:
69; CHECK:       # %bb.0:
70; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
71; CHECK-NEXT:    vwaddu.vv v10, v8, v9
72; CHECK-NEXT:    vnsrl.wi v8, v10, 2
73; CHECK-NEXT:    ret
74  %xzv = zext <vscale x 8 x i8> %x to <vscale x 8 x i16>
75  %yzv = zext <vscale x 8 x i8> %y to <vscale x 8 x i16>
76  %add = add nuw nsw <vscale x 8 x i16> %xzv, %yzv
77  %div = lshr <vscale x 8 x i16> %add, splat (i16 2)
78  %ret = trunc <vscale x 8 x i16> %div to <vscale x 8 x i8>
79  ret <vscale x 8 x i8> %ret
80}
81
82define <vscale x 8 x i16> @vaaddu_vv_nxv8i16_floor(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y) {
83; CHECK-LABEL: vaaddu_vv_nxv8i16_floor:
84; CHECK:       # %bb.0:
85; CHECK-NEXT:    csrwi vxrm, 2
86; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
87; CHECK-NEXT:    vaaddu.vv v8, v8, v10
88; CHECK-NEXT:    ret
89  %xzv = zext <vscale x 8 x i16> %x to <vscale x 8 x i32>
90  %yzv = zext <vscale x 8 x i16> %y to <vscale x 8 x i32>
91  %add = add nuw nsw <vscale x 8 x i32> %xzv, %yzv
92  %div = lshr <vscale x 8 x i32> %add, splat (i32 1)
93  %ret = trunc <vscale x 8 x i32> %div to <vscale x 8 x i16>
94  ret <vscale x 8 x i16> %ret
95}
96
97define <vscale x 8 x i16> @vaaddu_vx_nxv8i16_floor(<vscale x 8 x i16> %x, i16 %y) {
98; CHECK-LABEL: vaaddu_vx_nxv8i16_floor:
99; CHECK:       # %bb.0:
100; CHECK-NEXT:    csrwi vxrm, 2
101; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
102; CHECK-NEXT:    vaaddu.vx v8, v8, a0
103; CHECK-NEXT:    ret
104  %xzv = zext <vscale x 8 x i16> %x to <vscale x 8 x i32>
105  %yhead = insertelement <vscale x 8 x i16> poison, i16 %y, i16 0
106  %ysplat = shufflevector <vscale x 8 x i16> %yhead, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
107  %yzv = zext <vscale x 8 x i16> %ysplat to <vscale x 8 x i32>
108  %add = add nuw nsw <vscale x 8 x i32> %xzv, %yzv
109  %div = lshr <vscale x 8 x i32> %add, splat (i32 1)
110  %ret = trunc <vscale x 8 x i32> %div to <vscale x 8 x i16>
111  ret <vscale x 8 x i16> %ret
112}
113
114define <vscale x 8 x i32> @vaaddu_vv_nxv8i32_floor(<vscale x 8 x i32> %x, <vscale x 8 x i32> %y) {
115; CHECK-LABEL: vaaddu_vv_nxv8i32_floor:
116; CHECK:       # %bb.0:
117; CHECK-NEXT:    csrwi vxrm, 2
118; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
119; CHECK-NEXT:    vaaddu.vv v8, v8, v12
120; CHECK-NEXT:    ret
121  %xzv = zext <vscale x 8 x i32> %x to <vscale x 8 x i64>
122  %yzv = zext <vscale x 8 x i32> %y to <vscale x 8 x i64>
123  %add = add nuw nsw <vscale x 8 x i64> %xzv, %yzv
124  %div = lshr <vscale x 8 x i64> %add, splat (i64 1)
125  %ret = trunc <vscale x 8 x i64> %div to <vscale x 8 x i32>
126  ret <vscale x 8 x i32> %ret
127}
128
129define <vscale x 8 x i32> @vaaddu_vx_nxv8i32_floor(<vscale x 8 x i32> %x, i32 %y) {
130; CHECK-LABEL: vaaddu_vx_nxv8i32_floor:
131; CHECK:       # %bb.0:
132; CHECK-NEXT:    csrwi vxrm, 2
133; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
134; CHECK-NEXT:    vaaddu.vx v8, v8, a0
135; CHECK-NEXT:    ret
136  %xzv = zext <vscale x 8 x i32> %x to <vscale x 8 x i64>
137  %yhead = insertelement <vscale x 8 x i32> poison, i32 %y, i32 0
138  %ysplat = shufflevector <vscale x 8 x i32> %yhead, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
139  %yzv = zext <vscale x 8 x i32> %ysplat to <vscale x 8 x i64>
140  %add = add nuw nsw <vscale x 8 x i64> %xzv, %yzv
141  %div = lshr <vscale x 8 x i64> %add, splat (i64 1)
142  %ret = trunc <vscale x 8 x i64> %div to <vscale x 8 x i32>
143  ret <vscale x 8 x i32> %ret
144}
145
146define <vscale x 8 x i64> @vaaddu_vv_nxv8i64_floor(<vscale x 8 x i64> %x, <vscale x 8 x i64> %y) {
147; CHECK-LABEL: vaaddu_vv_nxv8i64_floor:
148; CHECK:       # %bb.0:
149; CHECK-NEXT:    csrwi vxrm, 2
150; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
151; CHECK-NEXT:    vaaddu.vv v8, v8, v16
152; CHECK-NEXT:    ret
153  %xzv = zext <vscale x 8 x i64> %x to <vscale x 8 x i128>
154  %yzv = zext <vscale x 8 x i64> %y to <vscale x 8 x i128>
155  %add = add nuw nsw <vscale x 8 x i128> %xzv, %yzv
156  %div = lshr <vscale x 8 x i128> %add, splat (i128 1)
157  %ret = trunc <vscale x 8 x i128> %div to <vscale x 8 x i64>
158  ret <vscale x 8 x i64> %ret
159}
160
161define <vscale x 8 x i64> @vaaddu_vx_nxv8i64_floor(<vscale x 8 x i64> %x, i64 %y) {
162; RV32-LABEL: vaaddu_vx_nxv8i64_floor:
163; RV32:       # %bb.0:
164; RV32-NEXT:    addi sp, sp, -16
165; RV32-NEXT:    .cfi_def_cfa_offset 16
166; RV32-NEXT:    sw a0, 8(sp)
167; RV32-NEXT:    sw a1, 12(sp)
168; RV32-NEXT:    addi a0, sp, 8
169; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
170; RV32-NEXT:    vlse64.v v16, (a0), zero
171; RV32-NEXT:    csrwi vxrm, 2
172; RV32-NEXT:    vaaddu.vv v8, v8, v16
173; RV32-NEXT:    addi sp, sp, 16
174; RV32-NEXT:    .cfi_def_cfa_offset 0
175; RV32-NEXT:    ret
176;
177; RV64-LABEL: vaaddu_vx_nxv8i64_floor:
178; RV64:       # %bb.0:
179; RV64-NEXT:    csrwi vxrm, 2
180; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
181; RV64-NEXT:    vaaddu.vx v8, v8, a0
182; RV64-NEXT:    ret
183  %xzv = zext <vscale x 8 x i64> %x to <vscale x 8 x i128>
184  %yhead = insertelement <vscale x 8 x i64> poison, i64 %y, i64 0
185  %ysplat = shufflevector <vscale x 8 x i64> %yhead, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
186  %yzv = zext <vscale x 8 x i64> %ysplat to <vscale x 8 x i128>
187  %add = add nuw nsw <vscale x 8 x i128> %xzv, %yzv
188  %div = lshr <vscale x 8 x i128> %add, splat (i128 1)
189  %ret = trunc <vscale x 8 x i128> %div to <vscale x 8 x i64>
190  ret <vscale x 8 x i64> %ret
191}
192
193define <vscale x 8 x i8> @vaaddu_vv_nxv8i8_ceil(<vscale x 8 x i8> %x, <vscale x 8 x i8> %y) {
194; CHECK-LABEL: vaaddu_vv_nxv8i8_ceil:
195; CHECK:       # %bb.0:
196; CHECK-NEXT:    csrwi vxrm, 0
197; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
198; CHECK-NEXT:    vaaddu.vv v8, v8, v9
199; CHECK-NEXT:    ret
200  %xzv = zext <vscale x 8 x i8> %x to <vscale x 8 x i16>
201  %yzv = zext <vscale x 8 x i8> %y to <vscale x 8 x i16>
202  %add = add nuw nsw <vscale x 8 x i16> %xzv, %yzv
203  %add1 = add nuw nsw <vscale x 8 x i16> %add, splat (i16 1)
204  %div = lshr <vscale x 8 x i16> %add1, splat (i16 1)
205  %ret = trunc <vscale x 8 x i16> %div to <vscale x 8 x i8>
206  ret <vscale x 8 x i8> %ret
207}
208
209define <vscale x 8 x i8> @vaaddu_vx_nxv8i8_ceil(<vscale x 8 x i8> %x, i8 %y) {
210; CHECK-LABEL: vaaddu_vx_nxv8i8_ceil:
211; CHECK:       # %bb.0:
212; CHECK-NEXT:    csrwi vxrm, 0
213; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, ma
214; CHECK-NEXT:    vaaddu.vx v8, v8, a0
215; CHECK-NEXT:    ret
216  %xzv = zext <vscale x 8 x i8> %x to <vscale x 8 x i16>
217  %yhead = insertelement <vscale x 8 x i8> poison, i8 %y, i32 0
218  %ysplat = shufflevector <vscale x 8 x i8> %yhead, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
219  %yzv = zext <vscale x 8 x i8> %ysplat to <vscale x 8 x i16>
220  %add = add nuw nsw <vscale x 8 x i16> %xzv, %yzv
221  %add1 = add nuw nsw <vscale x 8 x i16> %add, splat (i16 1)
222  %div = lshr <vscale x 8 x i16> %add1, splat (i16 1)
223  %ret = trunc <vscale x 8 x i16> %div to <vscale x 8 x i8>
224  ret <vscale x 8 x i8> %ret
225}
226
227define <vscale x 8 x i8> @vaaddu_vv_nxv8i8_ceil_sexti16(<vscale x 8 x i8> %x, <vscale x 8 x i8> %y) {
228; CHECK-LABEL: vaaddu_vv_nxv8i8_ceil_sexti16:
229; CHECK:       # %bb.0:
230; CHECK-NEXT:    csrwi vxrm, 0
231; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
232; CHECK-NEXT:    vaadd.vv v8, v8, v9
233; CHECK-NEXT:    ret
234  %xzv = sext <vscale x 8 x i8> %x to <vscale x 8 x i16>
235  %yzv = sext <vscale x 8 x i8> %y to <vscale x 8 x i16>
236  %add = add nuw nsw <vscale x 8 x i16> %xzv, %yzv
237  %add1 = add nuw nsw <vscale x 8 x i16> %add, splat (i16 1)
238  %div = lshr <vscale x 8 x i16> %add1, splat (i16 1)
239  %ret = trunc <vscale x 8 x i16> %div to <vscale x 8 x i8>
240  ret <vscale x 8 x i8> %ret
241}
242
243define <vscale x 8 x i8> @vaaddu_vv_nxv8i8_ceil_zexti32(<vscale x 8 x i8> %x, <vscale x 8 x i8> %y) {
244; CHECK-LABEL: vaaddu_vv_nxv8i8_ceil_zexti32:
245; CHECK:       # %bb.0:
246; CHECK-NEXT:    csrwi vxrm, 0
247; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
248; CHECK-NEXT:    vaaddu.vv v8, v8, v9
249; CHECK-NEXT:    ret
250  %xzv = zext <vscale x 8 x i8> %x to <vscale x 8 x i32>
251  %yzv = zext <vscale x 8 x i8> %y to <vscale x 8 x i32>
252  %add = add nuw nsw <vscale x 8 x i32> %xzv, %yzv
253  %add1 = add nuw nsw <vscale x 8 x i32> %add, splat (i32 1)
254  %div = lshr <vscale x 8 x i32> %add1, splat (i32 1)
255  %ret = trunc <vscale x 8 x i32> %div to <vscale x 8 x i8>
256  ret <vscale x 8 x i8> %ret
257}
258
259define <vscale x 8 x i8> @vaaddu_vv_nxv8i8_ceil_lshr2(<vscale x 8 x i8> %x, <vscale x 8 x i8> %y) {
260; CHECK-LABEL: vaaddu_vv_nxv8i8_ceil_lshr2:
261; CHECK:       # %bb.0:
262; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
263; CHECK-NEXT:    vwaddu.vv v10, v8, v9
264; CHECK-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
265; CHECK-NEXT:    vadd.vi v10, v10, 2
266; CHECK-NEXT:    vsetvli zero, zero, e8, m1, ta, ma
267; CHECK-NEXT:    vnsrl.wi v8, v10, 2
268; CHECK-NEXT:    ret
269  %xzv = zext <vscale x 8 x i8> %x to <vscale x 8 x i16>
270  %yzv = zext <vscale x 8 x i8> %y to <vscale x 8 x i16>
271  %add = add nuw nsw <vscale x 8 x i16> %xzv, %yzv
272  %add1 = add nuw nsw <vscale x 8 x i16> %add, splat (i16 2)
273  %div = lshr <vscale x 8 x i16> %add1, splat (i16 2)
274  %ret = trunc <vscale x 8 x i16> %div to <vscale x 8 x i8>
275  ret <vscale x 8 x i8> %ret
276}
277
278define <vscale x 8 x i8> @vaaddu_vv_nxv8i8_ceil_add2(<vscale x 8 x i8> %x, <vscale x 8 x i8> %y) {
279; CHECK-LABEL: vaaddu_vv_nxv8i8_ceil_add2:
280; CHECK:       # %bb.0:
281; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, ma
282; CHECK-NEXT:    vwaddu.vv v10, v8, v9
283; CHECK-NEXT:    vsetvli zero, zero, e16, m2, ta, ma
284; CHECK-NEXT:    vadd.vi v10, v10, 2
285; CHECK-NEXT:    vsetvli zero, zero, e8, m1, ta, ma
286; CHECK-NEXT:    vnsrl.wi v8, v10, 2
287; CHECK-NEXT:    ret
288  %xzv = zext <vscale x 8 x i8> %x to <vscale x 8 x i16>
289  %yzv = zext <vscale x 8 x i8> %y to <vscale x 8 x i16>
290  %add = add nuw nsw <vscale x 8 x i16> %xzv, %yzv
291  %add2 = add nuw nsw <vscale x 8 x i16> %add, splat (i16 2)
292  %div = lshr <vscale x 8 x i16> %add2, splat (i16 2)
293  %ret = trunc <vscale x 8 x i16> %div to <vscale x 8 x i8>
294  ret <vscale x 8 x i8> %ret
295}
296
297define <vscale x 8 x i16> @vaaddu_vv_nxv8i16_ceil(<vscale x 8 x i16> %x, <vscale x 8 x i16> %y) {
298; CHECK-LABEL: vaaddu_vv_nxv8i16_ceil:
299; CHECK:       # %bb.0:
300; CHECK-NEXT:    csrwi vxrm, 0
301; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, ma
302; CHECK-NEXT:    vaaddu.vv v8, v8, v10
303; CHECK-NEXT:    ret
304  %xzv = zext <vscale x 8 x i16> %x to <vscale x 8 x i32>
305  %yzv = zext <vscale x 8 x i16> %y to <vscale x 8 x i32>
306  %add = add nuw nsw <vscale x 8 x i32> %xzv, %yzv
307  %add1 = add nuw nsw <vscale x 8 x i32> %add, splat (i32 1)
308  %div = lshr <vscale x 8 x i32> %add1, splat (i32 1)
309  %ret = trunc <vscale x 8 x i32> %div to <vscale x 8 x i16>
310  ret <vscale x 8 x i16> %ret
311}
312
313define <vscale x 8 x i16> @vaaddu_vx_nxv8i16_ceil(<vscale x 8 x i16> %x, i16 %y) {
314; CHECK-LABEL: vaaddu_vx_nxv8i16_ceil:
315; CHECK:       # %bb.0:
316; CHECK-NEXT:    csrwi vxrm, 0
317; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, ma
318; CHECK-NEXT:    vaaddu.vx v8, v8, a0
319; CHECK-NEXT:    ret
320  %xzv = zext <vscale x 8 x i16> %x to <vscale x 8 x i32>
321  %yhead = insertelement <vscale x 8 x i16> poison, i16 %y, i16 0
322  %ysplat = shufflevector <vscale x 8 x i16> %yhead, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
323  %yzv = zext <vscale x 8 x i16> %ysplat to <vscale x 8 x i32>
324  %add = add nuw nsw <vscale x 8 x i32> %xzv, %yzv
325  %add1 = add nuw nsw <vscale x 8 x i32> %add, splat (i32 1)
326  %div = lshr <vscale x 8 x i32> %add1, splat (i32 1)
327  %ret = trunc <vscale x 8 x i32> %div to <vscale x 8 x i16>
328  ret <vscale x 8 x i16> %ret
329}
330
331define <vscale x 8 x i32> @vaaddu_vv_nxv8i32_ceil(<vscale x 8 x i32> %x, <vscale x 8 x i32> %y) {
332; CHECK-LABEL: vaaddu_vv_nxv8i32_ceil:
333; CHECK:       # %bb.0:
334; CHECK-NEXT:    csrwi vxrm, 0
335; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, ma
336; CHECK-NEXT:    vaaddu.vv v8, v8, v12
337; CHECK-NEXT:    ret
338  %xzv = zext <vscale x 8 x i32> %x to <vscale x 8 x i64>
339  %yzv = zext <vscale x 8 x i32> %y to <vscale x 8 x i64>
340  %add = add nuw nsw <vscale x 8 x i64> %xzv, %yzv
341  %add1 = add nuw nsw <vscale x 8 x i64> %add, splat (i64 1)
342  %div = lshr <vscale x 8 x i64> %add1, splat (i64 1)
343  %ret = trunc <vscale x 8 x i64> %div to <vscale x 8 x i32>
344  ret <vscale x 8 x i32> %ret
345}
346
347define <vscale x 8 x i32> @vaaddu_vx_nxv8i32_ceil(<vscale x 8 x i32> %x, i32 %y) {
348; CHECK-LABEL: vaaddu_vx_nxv8i32_ceil:
349; CHECK:       # %bb.0:
350; CHECK-NEXT:    csrwi vxrm, 0
351; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, ma
352; CHECK-NEXT:    vaaddu.vx v8, v8, a0
353; CHECK-NEXT:    ret
354  %xzv = zext <vscale x 8 x i32> %x to <vscale x 8 x i64>
355  %yhead = insertelement <vscale x 8 x i32> poison, i32 %y, i32 0
356  %ysplat = shufflevector <vscale x 8 x i32> %yhead, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
357  %yzv = zext <vscale x 8 x i32> %ysplat to <vscale x 8 x i64>
358  %add = add nuw nsw <vscale x 8 x i64> %xzv, %yzv
359  %add1 = add nuw nsw <vscale x 8 x i64> %add, splat (i64 1)
360  %div = lshr <vscale x 8 x i64> %add1, splat (i64 1)
361  %ret = trunc <vscale x 8 x i64> %div to <vscale x 8 x i32>
362  ret <vscale x 8 x i32> %ret
363}
364
365define <vscale x 8 x i64> @vaaddu_vv_nxv8i64_ceil(<vscale x 8 x i64> %x, <vscale x 8 x i64> %y) {
366; CHECK-LABEL: vaaddu_vv_nxv8i64_ceil:
367; CHECK:       # %bb.0:
368; CHECK-NEXT:    csrwi vxrm, 0
369; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, ma
370; CHECK-NEXT:    vaaddu.vv v8, v8, v16
371; CHECK-NEXT:    ret
372  %xzv = zext <vscale x 8 x i64> %x to <vscale x 8 x i128>
373  %yzv = zext <vscale x 8 x i64> %y to <vscale x 8 x i128>
374  %add = add nuw nsw <vscale x 8 x i128> %xzv, %yzv
375  %add1 = add nuw nsw <vscale x 8 x i128> %add, splat (i128 1)
376  %div = lshr <vscale x 8 x i128> %add1, splat (i128 1)
377  %ret = trunc <vscale x 8 x i128> %div to <vscale x 8 x i64>
378  ret <vscale x 8 x i64> %ret
379}
380
381define <vscale x 8 x i64> @vaaddu_vx_nxv8i64_ceil(<vscale x 8 x i64> %x, i64 %y) {
382; RV32-LABEL: vaaddu_vx_nxv8i64_ceil:
383; RV32:       # %bb.0:
384; RV32-NEXT:    addi sp, sp, -16
385; RV32-NEXT:    .cfi_def_cfa_offset 16
386; RV32-NEXT:    sw a0, 8(sp)
387; RV32-NEXT:    sw a1, 12(sp)
388; RV32-NEXT:    addi a0, sp, 8
389; RV32-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
390; RV32-NEXT:    vlse64.v v16, (a0), zero
391; RV32-NEXT:    csrwi vxrm, 0
392; RV32-NEXT:    vaaddu.vv v8, v8, v16
393; RV32-NEXT:    addi sp, sp, 16
394; RV32-NEXT:    .cfi_def_cfa_offset 0
395; RV32-NEXT:    ret
396;
397; RV64-LABEL: vaaddu_vx_nxv8i64_ceil:
398; RV64:       # %bb.0:
399; RV64-NEXT:    csrwi vxrm, 0
400; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, ma
401; RV64-NEXT:    vaaddu.vx v8, v8, a0
402; RV64-NEXT:    ret
403  %xzv = zext <vscale x 8 x i64> %x to <vscale x 8 x i128>
404  %yhead = insertelement <vscale x 8 x i64> poison, i64 %y, i64 0
405  %ysplat = shufflevector <vscale x 8 x i64> %yhead, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
406  %yzv = zext <vscale x 8 x i64> %ysplat to <vscale x 8 x i128>
407  %add = add nuw nsw <vscale x 8 x i128> %xzv, %yzv
408  %add1 = add nuw nsw <vscale x 8 x i128> %add, splat (i128 1)
409  %div = lshr <vscale x 8 x i128> %add1, splat (i128 1)
410  %ret = trunc <vscale x 8 x i128> %div to <vscale x 8 x i64>
411  ret <vscale x 8 x i64> %ret
412}
413