xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/setcc-integer.ll (revision ffe03ff75c26d598ce71d19c5eacf528f63a670b) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+m,+v \
3; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV32
4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+m,+v \
5; RUN:   -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV64
6
7define <vscale x 8 x i1> @icmp_eq_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
8; CHECK-LABEL: icmp_eq_vv_nxv8i8:
9; CHECK:       # %bb.0:
10; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
11; CHECK-NEXT:    vmseq.vv v0, v8, v9
12; CHECK-NEXT:    ret
13  %vc = icmp eq <vscale x 8 x i8> %va, %vb
14  ret <vscale x 8 x i1> %vc
15}
16
17define <vscale x 8 x i1> @icmp_eq_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
18; CHECK-LABEL: icmp_eq_vx_nxv8i8:
19; CHECK:       # %bb.0:
20; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
21; CHECK-NEXT:    vmseq.vx v0, v8, a0
22; CHECK-NEXT:    ret
23  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
24  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
25  %vc = icmp eq <vscale x 8 x i8> %va, %splat
26  ret <vscale x 8 x i1> %vc
27}
28
29define <vscale x 8 x i1> @icmp_eq_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
30; CHECK-LABEL: icmp_eq_xv_nxv8i8:
31; CHECK:       # %bb.0:
32; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
33; CHECK-NEXT:    vmseq.vx v0, v8, a0
34; CHECK-NEXT:    ret
35  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
36  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
37  %vc = icmp eq <vscale x 8 x i8> %splat, %va
38  ret <vscale x 8 x i1> %vc
39}
40
41define <vscale x 8 x i1> @icmp_eq_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
42; CHECK-LABEL: icmp_eq_vi_nxv8i8_0:
43; CHECK:       # %bb.0:
44; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
45; CHECK-NEXT:    vmseq.vi v0, v8, 0
46; CHECK-NEXT:    ret
47  %head = insertelement <vscale x 8 x i8> poison, i8 0, i32 0
48  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
49  %vc = icmp eq <vscale x 8 x i8> %va, %splat
50  ret <vscale x 8 x i1> %vc
51}
52
53define <vscale x 8 x i1> @icmp_eq_vi_nxv8i8_1(<vscale x 8 x i8> %va) {
54; CHECK-LABEL: icmp_eq_vi_nxv8i8_1:
55; CHECK:       # %bb.0:
56; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
57; CHECK-NEXT:    vmseq.vi v0, v8, 5
58; CHECK-NEXT:    ret
59  %head = insertelement <vscale x 8 x i8> poison, i8 5, i32 0
60  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
61  %vc = icmp eq <vscale x 8 x i8> %va, %splat
62  ret <vscale x 8 x i1> %vc
63}
64
65define <vscale x 8 x i1> @icmp_eq_iv_nxv8i8_1(<vscale x 8 x i8> %va) {
66; CHECK-LABEL: icmp_eq_iv_nxv8i8_1:
67; CHECK:       # %bb.0:
68; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
69; CHECK-NEXT:    vmseq.vi v0, v8, 5
70; CHECK-NEXT:    ret
71  %head = insertelement <vscale x 8 x i8> poison, i8 5, i32 0
72  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
73  %vc = icmp eq <vscale x 8 x i8> %splat, %va
74  ret <vscale x 8 x i1> %vc
75}
76
77define <vscale x 8 x i1> @icmp_ne_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
78; CHECK-LABEL: icmp_ne_vv_nxv8i8:
79; CHECK:       # %bb.0:
80; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
81; CHECK-NEXT:    vmsne.vv v0, v8, v9
82; CHECK-NEXT:    ret
83  %vc = icmp ne <vscale x 8 x i8> %va, %vb
84  ret <vscale x 8 x i1> %vc
85}
86
87define <vscale x 8 x i1> @icmp_ne_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
88; CHECK-LABEL: icmp_ne_vx_nxv8i8:
89; CHECK:       # %bb.0:
90; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
91; CHECK-NEXT:    vmsne.vx v0, v8, a0
92; CHECK-NEXT:    ret
93  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
94  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
95  %vc = icmp ne <vscale x 8 x i8> %va, %splat
96  ret <vscale x 8 x i1> %vc
97}
98
99define <vscale x 8 x i1> @icmp_ne_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
100; CHECK-LABEL: icmp_ne_xv_nxv8i8:
101; CHECK:       # %bb.0:
102; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
103; CHECK-NEXT:    vmsne.vx v0, v8, a0
104; CHECK-NEXT:    ret
105  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
106  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
107  %vc = icmp ne <vscale x 8 x i8> %splat, %va
108  ret <vscale x 8 x i1> %vc
109}
110
111define <vscale x 8 x i1> @icmp_ne_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
112; CHECK-LABEL: icmp_ne_vi_nxv8i8_0:
113; CHECK:       # %bb.0:
114; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
115; CHECK-NEXT:    vmsne.vi v0, v8, 5
116; CHECK-NEXT:    ret
117  %head = insertelement <vscale x 8 x i8> poison, i8 5, i32 0
118  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
119  %vc = icmp ne <vscale x 8 x i8> %va, %splat
120  ret <vscale x 8 x i1> %vc
121}
122
123define <vscale x 8 x i1> @icmp_ugt_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
124; CHECK-LABEL: icmp_ugt_vv_nxv8i8:
125; CHECK:       # %bb.0:
126; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
127; CHECK-NEXT:    vmsltu.vv v0, v9, v8
128; CHECK-NEXT:    ret
129  %vc = icmp ugt <vscale x 8 x i8> %va, %vb
130  ret <vscale x 8 x i1> %vc
131}
132
133define <vscale x 8 x i1> @icmp_ugt_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
134; CHECK-LABEL: icmp_ugt_vx_nxv8i8:
135; CHECK:       # %bb.0:
136; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
137; CHECK-NEXT:    vmsgtu.vx v0, v8, a0
138; CHECK-NEXT:    ret
139  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
140  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
141  %vc = icmp ugt <vscale x 8 x i8> %va, %splat
142  ret <vscale x 8 x i1> %vc
143}
144
145define <vscale x 8 x i1> @icmp_ugt_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
146; CHECK-LABEL: icmp_ugt_xv_nxv8i8:
147; CHECK:       # %bb.0:
148; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
149; CHECK-NEXT:    vmsltu.vx v0, v8, a0
150; CHECK-NEXT:    ret
151  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
152  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
153  %vc = icmp ugt <vscale x 8 x i8> %splat, %va
154  ret <vscale x 8 x i1> %vc
155}
156
157define <vscale x 8 x i1> @icmp_ugt_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
158; CHECK-LABEL: icmp_ugt_vi_nxv8i8_0:
159; CHECK:       # %bb.0:
160; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
161; CHECK-NEXT:    vmsgtu.vi v0, v8, 5
162; CHECK-NEXT:    ret
163  %head = insertelement <vscale x 8 x i8> poison, i8 5, i32 0
164  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
165  %vc = icmp ugt <vscale x 8 x i8> %va, %splat
166  ret <vscale x 8 x i1> %vc
167}
168
169define <vscale x 8 x i1> @icmp_uge_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
170; CHECK-LABEL: icmp_uge_vv_nxv8i8:
171; CHECK:       # %bb.0:
172; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
173; CHECK-NEXT:    vmsleu.vv v0, v9, v8
174; CHECK-NEXT:    ret
175  %vc = icmp uge <vscale x 8 x i8> %va, %vb
176  ret <vscale x 8 x i1> %vc
177}
178
179define <vscale x 8 x i1> @icmp_uge_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
180; CHECK-LABEL: icmp_uge_vx_nxv8i8:
181; CHECK:       # %bb.0:
182; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
183; CHECK-NEXT:    vmv.v.x v9, a0
184; CHECK-NEXT:    vmsleu.vv v0, v9, v8
185; CHECK-NEXT:    ret
186  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
187  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
188  %vc = icmp uge <vscale x 8 x i8> %va, %splat
189  ret <vscale x 8 x i1> %vc
190}
191
192define <vscale x 8 x i1> @icmp_uge_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
193; CHECK-LABEL: icmp_uge_xv_nxv8i8:
194; CHECK:       # %bb.0:
195; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
196; CHECK-NEXT:    vmsleu.vx v0, v8, a0
197; CHECK-NEXT:    ret
198  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
199  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
200  %vc = icmp uge <vscale x 8 x i8> %splat, %va
201  ret <vscale x 8 x i1> %vc
202}
203
204define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
205; CHECK-LABEL: icmp_uge_vi_nxv8i8_0:
206; CHECK:       # %bb.0:
207; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
208; CHECK-NEXT:    vmv.v.i v9, -16
209; CHECK-NEXT:    vmsleu.vv v0, v9, v8
210; CHECK-NEXT:    ret
211  %head = insertelement <vscale x 8 x i8> poison, i8 -16, i32 0
212  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
213  %vc = icmp uge <vscale x 8 x i8> %va, %splat
214  ret <vscale x 8 x i1> %vc
215}
216
217define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_1(<vscale x 8 x i8> %va) {
218; CHECK-LABEL: icmp_uge_vi_nxv8i8_1:
219; CHECK:       # %bb.0:
220; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
221; CHECK-NEXT:    vmsgtu.vi v0, v8, 14
222; CHECK-NEXT:    ret
223  %head = insertelement <vscale x 8 x i8> poison, i8 15, i32 0
224  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
225  %vc = icmp uge <vscale x 8 x i8> %va, %splat
226  ret <vscale x 8 x i1> %vc
227}
228
229define <vscale x 8 x i1> @icmp_uge_iv_nxv8i8_1(<vscale x 8 x i8> %va) {
230; CHECK-LABEL: icmp_uge_iv_nxv8i8_1:
231; CHECK:       # %bb.0:
232; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
233; CHECK-NEXT:    vmsleu.vi v0, v8, 15
234; CHECK-NEXT:    ret
235  %head = insertelement <vscale x 8 x i8> poison, i8 15, i32 0
236  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
237  %vc = icmp uge <vscale x 8 x i8> %splat, %va
238  ret <vscale x 8 x i1> %vc
239}
240
241define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_2(<vscale x 8 x i8> %va) {
242; CHECK-LABEL: icmp_uge_vi_nxv8i8_2:
243; CHECK:       # %bb.0:
244; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
245; CHECK-NEXT:    vmset.m v0
246; CHECK-NEXT:    ret
247  %head = insertelement <vscale x 8 x i8> poison, i8 0, i32 0
248  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
249  %vc = icmp uge <vscale x 8 x i8> %va, %splat
250  ret <vscale x 8 x i1> %vc
251}
252
253define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_3(<vscale x 8 x i8> %va) {
254; CHECK-LABEL: icmp_uge_vi_nxv8i8_3:
255; CHECK:       # %bb.0:
256; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
257; CHECK-NEXT:    vmsgtu.vi v0, v8, 0
258; CHECK-NEXT:    ret
259  %head = insertelement <vscale x 8 x i8> poison, i8 1, i32 0
260  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
261  %vc = icmp uge <vscale x 8 x i8> %va, %splat
262  ret <vscale x 8 x i1> %vc
263}
264
265define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_4(<vscale x 8 x i8> %va) {
266; CHECK-LABEL: icmp_uge_vi_nxv8i8_4:
267; CHECK:       # %bb.0:
268; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
269; CHECK-NEXT:    vmsgtu.vi v0, v8, -16
270; CHECK-NEXT:    ret
271  %head = insertelement <vscale x 8 x i8> poison, i8 -15, i32 0
272  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
273  %vc = icmp uge <vscale x 8 x i8> %va, %splat
274  ret <vscale x 8 x i1> %vc
275}
276
277define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_5(<vscale x 8 x i8> %va) {
278; CHECK-LABEL: icmp_uge_vi_nxv8i8_5:
279; CHECK:       # %bb.0:
280; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
281; CHECK-NEXT:    vmsgtu.vi v0, v8, 15
282; CHECK-NEXT:    ret
283  %head = insertelement <vscale x 8 x i8> poison, i8 16, i32 0
284  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
285  %vc = icmp uge <vscale x 8 x i8> %va, %splat
286  ret <vscale x 8 x i1> %vc
287}
288
289; Test that we don't optimize uge x, 0 -> ugt x, -1
290define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_6(<vscale x 8 x i8> %va, iXLen %vl) {
291; CHECK-LABEL: icmp_uge_vi_nxv8i8_6:
292; CHECK:       # %bb.0:
293; CHECK-NEXT:    vsetvli zero, a0, e8, m1, ta, mu
294; CHECK-NEXT:    vmv.v.i v9, 0
295; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
296; CHECK-NEXT:    vmsleu.vv v0, v9, v8
297; CHECK-NEXT:    ret
298  %splat = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.iXLen(<vscale x 8 x i8> undef, i8 0, iXLen %vl)
299  %vc = icmp uge <vscale x 8 x i8> %va, %splat
300  ret <vscale x 8 x i1> %vc
301}
302
303define <vscale x 8 x i1> @icmp_ult_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
304; CHECK-LABEL: icmp_ult_vv_nxv8i8:
305; CHECK:       # %bb.0:
306; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
307; CHECK-NEXT:    vmsltu.vv v0, v8, v9
308; CHECK-NEXT:    ret
309  %vc = icmp ult <vscale x 8 x i8> %va, %vb
310  ret <vscale x 8 x i1> %vc
311}
312
313define <vscale x 8 x i1> @icmp_ult_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
314; CHECK-LABEL: icmp_ult_vx_nxv8i8:
315; CHECK:       # %bb.0:
316; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
317; CHECK-NEXT:    vmsltu.vx v0, v8, a0
318; CHECK-NEXT:    ret
319  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
320  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
321  %vc = icmp ult <vscale x 8 x i8> %va, %splat
322  ret <vscale x 8 x i1> %vc
323}
324
325define <vscale x 8 x i1> @icmp_ult_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
326; CHECK-LABEL: icmp_ult_xv_nxv8i8:
327; CHECK:       # %bb.0:
328; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
329; CHECK-NEXT:    vmsgtu.vx v0, v8, a0
330; CHECK-NEXT:    ret
331  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
332  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
333  %vc = icmp ult <vscale x 8 x i8> %splat, %va
334  ret <vscale x 8 x i1> %vc
335}
336
337define <vscale x 8 x i1> @icmp_ult_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
338; CHECK-LABEL: icmp_ult_vi_nxv8i8_0:
339; CHECK:       # %bb.0:
340; CHECK-NEXT:    li a0, -16
341; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
342; CHECK-NEXT:    vmsltu.vx v0, v8, a0
343; CHECK-NEXT:    ret
344  %head = insertelement <vscale x 8 x i8> poison, i8 -16, i32 0
345  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
346  %vc = icmp ult <vscale x 8 x i8> %va, %splat
347  ret <vscale x 8 x i1> %vc
348}
349
350define <vscale x 8 x i1> @icmp_ult_vi_nxv8i8_1(<vscale x 8 x i8> %va) {
351; CHECK-LABEL: icmp_ult_vi_nxv8i8_1:
352; CHECK:       # %bb.0:
353; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
354; CHECK-NEXT:    vmsleu.vi v0, v8, -16
355; CHECK-NEXT:    ret
356  %head = insertelement <vscale x 8 x i8> poison, i8 -15, i32 0
357  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
358  %vc = icmp ult <vscale x 8 x i8> %va, %splat
359  ret <vscale x 8 x i1> %vc
360}
361
362define <vscale x 8 x i1> @icmp_ult_iv_nxv8i8_1(<vscale x 8 x i8> %va) {
363; CHECK-LABEL: icmp_ult_iv_nxv8i8_1:
364; CHECK:       # %bb.0:
365; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
366; CHECK-NEXT:    vmsgtu.vi v0, v8, -15
367; CHECK-NEXT:    ret
368  %head = insertelement <vscale x 8 x i8> poison, i8 -15, i32 0
369  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
370  %vc = icmp ult <vscale x 8 x i8> %splat, %va
371  ret <vscale x 8 x i1> %vc
372}
373
374define <vscale x 8 x i1> @icmp_ult_vi_nxv8i8_2(<vscale x 8 x i8> %va) {
375; CHECK-LABEL: icmp_ult_vi_nxv8i8_2:
376; CHECK:       # %bb.0:
377; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
378; CHECK-NEXT:    vmclr.m v0
379; CHECK-NEXT:    ret
380  %head = insertelement <vscale x 8 x i8> poison, i8 0, i32 0
381  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
382  %vc = icmp ult <vscale x 8 x i8> %va, %splat
383  ret <vscale x 8 x i1> %vc
384}
385
386define <vscale x 8 x i1> @icmp_ult_vi_nxv8i8_3(<vscale x 8 x i8> %va) {
387; CHECK-LABEL: icmp_ult_vi_nxv8i8_3:
388; CHECK:       # %bb.0:
389; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
390; CHECK-NEXT:    vmseq.vi v0, v8, 0
391; CHECK-NEXT:    ret
392  %head = insertelement <vscale x 8 x i8> poison, i8 1, i32 0
393  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
394  %vc = icmp ult <vscale x 8 x i8> %va, %splat
395  ret <vscale x 8 x i1> %vc
396}
397
398define <vscale x 8 x i1> @icmp_ult_vi_nxv8i8_4(<vscale x 8 x i8> %va) {
399; CHECK-LABEL: icmp_ult_vi_nxv8i8_4:
400; CHECK:       # %bb.0:
401; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
402; CHECK-NEXT:    vmsleu.vi v0, v8, 15
403; CHECK-NEXT:    ret
404  %head = insertelement <vscale x 8 x i8> poison, i8 16, i32 0
405  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
406  %vc = icmp ult <vscale x 8 x i8> %va, %splat
407  ret <vscale x 8 x i1> %vc
408}
409
410declare <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.iXLen(<vscale x 8 x i8>, i8, iXLen);
411
412; Test that we don't optimize ult x, 0 -> ule x, -1
413define <vscale x 8 x i1> @icmp_ult_vi_nxv8i8_5(<vscale x 8 x i8> %va, iXLen %vl) {
414; CHECK-LABEL: icmp_ult_vi_nxv8i8_5:
415; CHECK:       # %bb.0:
416; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
417; CHECK-NEXT:    vmsltu.vx v0, v8, zero
418; CHECK-NEXT:    ret
419  %splat = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.iXLen(<vscale x 8 x i8> undef, i8 0, iXLen %vl)
420  %vc = icmp ult <vscale x 8 x i8> %va, %splat
421  ret <vscale x 8 x i1> %vc
422}
423
424define <vscale x 8 x i1> @icmp_ule_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
425; CHECK-LABEL: icmp_ule_vv_nxv8i8:
426; CHECK:       # %bb.0:
427; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
428; CHECK-NEXT:    vmsleu.vv v0, v8, v9
429; CHECK-NEXT:    ret
430  %vc = icmp ule <vscale x 8 x i8> %va, %vb
431  ret <vscale x 8 x i1> %vc
432}
433
434define <vscale x 8 x i1> @icmp_ule_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
435; CHECK-LABEL: icmp_ule_vx_nxv8i8:
436; CHECK:       # %bb.0:
437; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
438; CHECK-NEXT:    vmsleu.vx v0, v8, a0
439; CHECK-NEXT:    ret
440  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
441  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
442  %vc = icmp ule <vscale x 8 x i8> %va, %splat
443  ret <vscale x 8 x i1> %vc
444}
445
446define <vscale x 8 x i1> @icmp_ule_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
447; CHECK-LABEL: icmp_ule_xv_nxv8i8:
448; CHECK:       # %bb.0:
449; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
450; CHECK-NEXT:    vmv.v.x v9, a0
451; CHECK-NEXT:    vmsleu.vv v0, v9, v8
452; CHECK-NEXT:    ret
453  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
454  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
455  %vc = icmp ule <vscale x 8 x i8> %splat, %va
456  ret <vscale x 8 x i1> %vc
457}
458
459define <vscale x 8 x i1> @icmp_ule_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
460; CHECK-LABEL: icmp_ule_vi_nxv8i8_0:
461; CHECK:       # %bb.0:
462; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
463; CHECK-NEXT:    vmsleu.vi v0, v8, 5
464; CHECK-NEXT:    ret
465  %head = insertelement <vscale x 8 x i8> poison, i8 5, i32 0
466  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
467  %vc = icmp ule <vscale x 8 x i8> %va, %splat
468  ret <vscale x 8 x i1> %vc
469}
470
471define <vscale x 8 x i1> @icmp_sgt_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
472; CHECK-LABEL: icmp_sgt_vv_nxv8i8:
473; CHECK:       # %bb.0:
474; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
475; CHECK-NEXT:    vmslt.vv v0, v9, v8
476; CHECK-NEXT:    ret
477  %vc = icmp sgt <vscale x 8 x i8> %va, %vb
478  ret <vscale x 8 x i1> %vc
479}
480
481define <vscale x 8 x i1> @icmp_sgt_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
482; CHECK-LABEL: icmp_sgt_vx_nxv8i8:
483; CHECK:       # %bb.0:
484; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
485; CHECK-NEXT:    vmsgt.vx v0, v8, a0
486; CHECK-NEXT:    ret
487  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
488  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
489  %vc = icmp sgt <vscale x 8 x i8> %va, %splat
490  ret <vscale x 8 x i1> %vc
491}
492
493define <vscale x 8 x i1> @icmp_sgt_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
494; CHECK-LABEL: icmp_sgt_xv_nxv8i8:
495; CHECK:       # %bb.0:
496; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
497; CHECK-NEXT:    vmslt.vx v0, v8, a0
498; CHECK-NEXT:    ret
499  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
500  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
501  %vc = icmp sgt <vscale x 8 x i8> %splat, %va
502  ret <vscale x 8 x i1> %vc
503}
504
505define <vscale x 8 x i1> @icmp_sgt_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
506; CHECK-LABEL: icmp_sgt_vi_nxv8i8_0:
507; CHECK:       # %bb.0:
508; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
509; CHECK-NEXT:    vmsgt.vi v0, v8, 5
510; CHECK-NEXT:    ret
511  %head = insertelement <vscale x 8 x i8> poison, i8 5, i32 0
512  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
513  %vc = icmp sgt <vscale x 8 x i8> %va, %splat
514  ret <vscale x 8 x i1> %vc
515}
516
517define <vscale x 8 x i1> @icmp_sge_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
518; CHECK-LABEL: icmp_sge_vv_nxv8i8:
519; CHECK:       # %bb.0:
520; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
521; CHECK-NEXT:    vmsle.vv v0, v9, v8
522; CHECK-NEXT:    ret
523  %vc = icmp sge <vscale x 8 x i8> %va, %vb
524  ret <vscale x 8 x i1> %vc
525}
526
527define <vscale x 8 x i1> @icmp_sge_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
528; CHECK-LABEL: icmp_sge_vx_nxv8i8:
529; CHECK:       # %bb.0:
530; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
531; CHECK-NEXT:    vmv.v.x v9, a0
532; CHECK-NEXT:    vmsle.vv v0, v9, v8
533; CHECK-NEXT:    ret
534  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
535  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
536  %vc = icmp sge <vscale x 8 x i8> %va, %splat
537  ret <vscale x 8 x i1> %vc
538}
539
540define <vscale x 8 x i1> @icmp_sge_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
541; CHECK-LABEL: icmp_sge_xv_nxv8i8:
542; CHECK:       # %bb.0:
543; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
544; CHECK-NEXT:    vmsle.vx v0, v8, a0
545; CHECK-NEXT:    ret
546  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
547  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
548  %vc = icmp sge <vscale x 8 x i8> %splat, %va
549  ret <vscale x 8 x i1> %vc
550}
551
552define <vscale x 8 x i1> @icmp_sge_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
553; CHECK-LABEL: icmp_sge_vi_nxv8i8_0:
554; CHECK:       # %bb.0:
555; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
556; CHECK-NEXT:    vmv.v.i v9, -16
557; CHECK-NEXT:    vmsle.vv v0, v9, v8
558; CHECK-NEXT:    ret
559  %head = insertelement <vscale x 8 x i8> poison, i8 -16, i32 0
560  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
561  %vc = icmp sge <vscale x 8 x i8> %va, %splat
562  ret <vscale x 8 x i1> %vc
563}
564
565define <vscale x 8 x i1> @icmp_sge_vi_nxv8i8_1(<vscale x 8 x i8> %va) {
566; CHECK-LABEL: icmp_sge_vi_nxv8i8_1:
567; CHECK:       # %bb.0:
568; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
569; CHECK-NEXT:    vmsgt.vi v0, v8, -16
570; CHECK-NEXT:    ret
571  %head = insertelement <vscale x 8 x i8> poison, i8 -15, i32 0
572  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
573  %vc = icmp sge <vscale x 8 x i8> %va, %splat
574  ret <vscale x 8 x i1> %vc
575}
576
577define <vscale x 8 x i1> @icmp_sge_iv_nxv8i8_1(<vscale x 8 x i8> %va) {
578; CHECK-LABEL: icmp_sge_iv_nxv8i8_1:
579; CHECK:       # %bb.0:
580; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
581; CHECK-NEXT:    vmsle.vi v0, v8, -15
582; CHECK-NEXT:    ret
583  %head = insertelement <vscale x 8 x i8> poison, i8 -15, i32 0
584  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
585  %vc = icmp sge <vscale x 8 x i8> %splat, %va
586  ret <vscale x 8 x i1> %vc
587}
588
589define <vscale x 8 x i1> @icmp_sge_vi_nxv8i8_2(<vscale x 8 x i8> %va) {
590; CHECK-LABEL: icmp_sge_vi_nxv8i8_2:
591; CHECK:       # %bb.0:
592; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
593; CHECK-NEXT:    vmsgt.vi v0, v8, -1
594; CHECK-NEXT:    ret
595  %head = insertelement <vscale x 8 x i8> poison, i8 0, i32 0
596  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
597  %vc = icmp sge <vscale x 8 x i8> %va, %splat
598  ret <vscale x 8 x i1> %vc
599}
600
601define <vscale x 8 x i1> @icmp_sge_vi_nxv8i8_3(<vscale x 8 x i8> %va) {
602; CHECK-LABEL: icmp_sge_vi_nxv8i8_3:
603; CHECK:       # %bb.0:
604; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
605; CHECK-NEXT:    vmsgt.vi v0, v8, 15
606; CHECK-NEXT:    ret
607  %head = insertelement <vscale x 8 x i8> poison, i8 16, i32 0
608  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
609  %vc = icmp sge <vscale x 8 x i8> %va, %splat
610  ret <vscale x 8 x i1> %vc
611}
612
613define <vscale x 8 x i1> @icmp_slt_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
614; CHECK-LABEL: icmp_slt_vv_nxv8i8:
615; CHECK:       # %bb.0:
616; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
617; CHECK-NEXT:    vmslt.vv v0, v8, v9
618; CHECK-NEXT:    ret
619  %vc = icmp slt <vscale x 8 x i8> %va, %vb
620  ret <vscale x 8 x i1> %vc
621}
622
623define <vscale x 8 x i1> @icmp_slt_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
624; CHECK-LABEL: icmp_slt_vx_nxv8i8:
625; CHECK:       # %bb.0:
626; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
627; CHECK-NEXT:    vmslt.vx v0, v8, a0
628; CHECK-NEXT:    ret
629  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
630  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
631  %vc = icmp slt <vscale x 8 x i8> %va, %splat
632  ret <vscale x 8 x i1> %vc
633}
634
635define <vscale x 8 x i1> @icmp_slt_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
636; CHECK-LABEL: icmp_slt_xv_nxv8i8:
637; CHECK:       # %bb.0:
638; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
639; CHECK-NEXT:    vmsgt.vx v0, v8, a0
640; CHECK-NEXT:    ret
641  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
642  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
643  %vc = icmp slt <vscale x 8 x i8> %splat, %va
644  ret <vscale x 8 x i1> %vc
645}
646
647define <vscale x 8 x i1> @icmp_slt_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
648; CHECK-LABEL: icmp_slt_vi_nxv8i8_0:
649; CHECK:       # %bb.0:
650; CHECK-NEXT:    li a0, -16
651; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
652; CHECK-NEXT:    vmslt.vx v0, v8, a0
653; CHECK-NEXT:    ret
654  %head = insertelement <vscale x 8 x i8> poison, i8 -16, i32 0
655  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
656  %vc = icmp slt <vscale x 8 x i8> %va, %splat
657  ret <vscale x 8 x i1> %vc
658}
659
660define <vscale x 8 x i1> @icmp_slt_vi_nxv8i8_1(<vscale x 8 x i8> %va) {
661; CHECK-LABEL: icmp_slt_vi_nxv8i8_1:
662; CHECK:       # %bb.0:
663; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
664; CHECK-NEXT:    vmsle.vi v0, v8, -16
665; CHECK-NEXT:    ret
666  %head = insertelement <vscale x 8 x i8> poison, i8 -15, i32 0
667  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
668  %vc = icmp slt <vscale x 8 x i8> %va, %splat
669  ret <vscale x 8 x i1> %vc
670}
671
672define <vscale x 8 x i1> @icmp_slt_iv_nxv8i8_1(<vscale x 8 x i8> %va) {
673; CHECK-LABEL: icmp_slt_iv_nxv8i8_1:
674; CHECK:       # %bb.0:
675; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
676; CHECK-NEXT:    vmsgt.vi v0, v8, -15
677; CHECK-NEXT:    ret
678  %head = insertelement <vscale x 8 x i8> poison, i8 -15, i32 0
679  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
680  %vc = icmp slt <vscale x 8 x i8> %splat, %va
681  ret <vscale x 8 x i1> %vc
682}
683
684define <vscale x 8 x i1> @icmp_slt_vi_nxv8i8_2(<vscale x 8 x i8> %va) {
685; CHECK-LABEL: icmp_slt_vi_nxv8i8_2:
686; CHECK:       # %bb.0:
687; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
688; CHECK-NEXT:    vmslt.vx v0, v8, zero
689; CHECK-NEXT:    ret
690  %head = insertelement <vscale x 8 x i8> poison, i8 0, i32 0
691  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
692  %vc = icmp slt <vscale x 8 x i8> %va, %splat
693  ret <vscale x 8 x i1> %vc
694}
695
696define <vscale x 8 x i1> @icmp_slt_vi_nxv8i8_3(<vscale x 8 x i8> %va) {
697; CHECK-LABEL: icmp_slt_vi_nxv8i8_3:
698; CHECK:       # %bb.0:
699; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
700; CHECK-NEXT:    vmsle.vi v0, v8, 15
701; CHECK-NEXT:    ret
702  %head = insertelement <vscale x 8 x i8> poison, i8 16, i32 0
703  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
704  %vc = icmp slt <vscale x 8 x i8> %va, %splat
705  ret <vscale x 8 x i1> %vc
706}
707
708define <vscale x 8 x i1> @icmp_sle_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) {
709; CHECK-LABEL: icmp_sle_vv_nxv8i8:
710; CHECK:       # %bb.0:
711; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
712; CHECK-NEXT:    vmsle.vv v0, v8, v9
713; CHECK-NEXT:    ret
714  %vc = icmp sle <vscale x 8 x i8> %va, %vb
715  ret <vscale x 8 x i1> %vc
716}
717
718define <vscale x 8 x i1> @icmp_sle_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
719; CHECK-LABEL: icmp_sle_vx_nxv8i8:
720; CHECK:       # %bb.0:
721; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
722; CHECK-NEXT:    vmsle.vx v0, v8, a0
723; CHECK-NEXT:    ret
724  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
725  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
726  %vc = icmp sle <vscale x 8 x i8> %va, %splat
727  ret <vscale x 8 x i1> %vc
728}
729
730define <vscale x 8 x i1> @icmp_sle_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) {
731; CHECK-LABEL: icmp_sle_xv_nxv8i8:
732; CHECK:       # %bb.0:
733; CHECK-NEXT:    vsetvli a1, zero, e8, m1, ta, mu
734; CHECK-NEXT:    vmv.v.x v9, a0
735; CHECK-NEXT:    vmsle.vv v0, v9, v8
736; CHECK-NEXT:    ret
737  %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0
738  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
739  %vc = icmp sle <vscale x 8 x i8> %splat, %va
740  ret <vscale x 8 x i1> %vc
741}
742
743define <vscale x 8 x i1> @icmp_sle_vi_nxv8i8_0(<vscale x 8 x i8> %va) {
744; CHECK-LABEL: icmp_sle_vi_nxv8i8_0:
745; CHECK:       # %bb.0:
746; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
747; CHECK-NEXT:    vmsle.vi v0, v8, 5
748; CHECK-NEXT:    ret
749  %head = insertelement <vscale x 8 x i8> poison, i8 5, i32 0
750  %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
751  %vc = icmp sle <vscale x 8 x i8> %va, %splat
752  ret <vscale x 8 x i1> %vc
753}
754
755define <vscale x 8 x i1> @icmp_eq_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
756; CHECK-LABEL: icmp_eq_vv_nxv8i16:
757; CHECK:       # %bb.0:
758; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
759; CHECK-NEXT:    vmseq.vv v0, v8, v10
760; CHECK-NEXT:    ret
761  %vc = icmp eq <vscale x 8 x i16> %va, %vb
762  ret <vscale x 8 x i1> %vc
763}
764
765define <vscale x 8 x i1> @icmp_eq_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
766; CHECK-LABEL: icmp_eq_vx_nxv8i16:
767; CHECK:       # %bb.0:
768; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
769; CHECK-NEXT:    vmseq.vx v0, v8, a0
770; CHECK-NEXT:    ret
771  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
772  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
773  %vc = icmp eq <vscale x 8 x i16> %va, %splat
774  ret <vscale x 8 x i1> %vc
775}
776
777define <vscale x 8 x i1> @icmp_eq_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
778; CHECK-LABEL: icmp_eq_xv_nxv8i16:
779; CHECK:       # %bb.0:
780; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
781; CHECK-NEXT:    vmseq.vx v0, v8, a0
782; CHECK-NEXT:    ret
783  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
784  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
785  %vc = icmp eq <vscale x 8 x i16> %splat, %va
786  ret <vscale x 8 x i1> %vc
787}
788
789define <vscale x 8 x i1> @icmp_eq_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
790; CHECK-LABEL: icmp_eq_vi_nxv8i16_0:
791; CHECK:       # %bb.0:
792; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
793; CHECK-NEXT:    vmseq.vi v0, v8, 0
794; CHECK-NEXT:    ret
795  %head = insertelement <vscale x 8 x i16> poison, i16 0, i32 0
796  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
797  %vc = icmp eq <vscale x 8 x i16> %va, %splat
798  ret <vscale x 8 x i1> %vc
799}
800
801define <vscale x 8 x i1> @icmp_eq_vi_nxv8i16_1(<vscale x 8 x i16> %va) {
802; CHECK-LABEL: icmp_eq_vi_nxv8i16_1:
803; CHECK:       # %bb.0:
804; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
805; CHECK-NEXT:    vmseq.vi v0, v8, 5
806; CHECK-NEXT:    ret
807  %head = insertelement <vscale x 8 x i16> poison, i16 5, i32 0
808  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
809  %vc = icmp eq <vscale x 8 x i16> %va, %splat
810  ret <vscale x 8 x i1> %vc
811}
812
813define <vscale x 8 x i1> @icmp_eq_iv_nxv8i16_1(<vscale x 8 x i16> %va) {
814; CHECK-LABEL: icmp_eq_iv_nxv8i16_1:
815; CHECK:       # %bb.0:
816; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
817; CHECK-NEXT:    vmseq.vi v0, v8, 5
818; CHECK-NEXT:    ret
819  %head = insertelement <vscale x 8 x i16> poison, i16 5, i32 0
820  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
821  %vc = icmp eq <vscale x 8 x i16> %splat, %va
822  ret <vscale x 8 x i1> %vc
823}
824
825define <vscale x 8 x i1> @icmp_ne_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
826; CHECK-LABEL: icmp_ne_vv_nxv8i16:
827; CHECK:       # %bb.0:
828; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
829; CHECK-NEXT:    vmsne.vv v0, v8, v10
830; CHECK-NEXT:    ret
831  %vc = icmp ne <vscale x 8 x i16> %va, %vb
832  ret <vscale x 8 x i1> %vc
833}
834
835define <vscale x 8 x i1> @icmp_ne_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
836; CHECK-LABEL: icmp_ne_vx_nxv8i16:
837; CHECK:       # %bb.0:
838; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
839; CHECK-NEXT:    vmsne.vx v0, v8, a0
840; CHECK-NEXT:    ret
841  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
842  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
843  %vc = icmp ne <vscale x 8 x i16> %va, %splat
844  ret <vscale x 8 x i1> %vc
845}
846
847define <vscale x 8 x i1> @icmp_ne_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
848; CHECK-LABEL: icmp_ne_xv_nxv8i16:
849; CHECK:       # %bb.0:
850; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
851; CHECK-NEXT:    vmsne.vx v0, v8, a0
852; CHECK-NEXT:    ret
853  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
854  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
855  %vc = icmp ne <vscale x 8 x i16> %splat, %va
856  ret <vscale x 8 x i1> %vc
857}
858
859define <vscale x 8 x i1> @icmp_ne_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
860; CHECK-LABEL: icmp_ne_vi_nxv8i16_0:
861; CHECK:       # %bb.0:
862; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
863; CHECK-NEXT:    vmsne.vi v0, v8, 5
864; CHECK-NEXT:    ret
865  %head = insertelement <vscale x 8 x i16> poison, i16 5, i32 0
866  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
867  %vc = icmp ne <vscale x 8 x i16> %va, %splat
868  ret <vscale x 8 x i1> %vc
869}
870
871define <vscale x 8 x i1> @icmp_ugt_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
872; CHECK-LABEL: icmp_ugt_vv_nxv8i16:
873; CHECK:       # %bb.0:
874; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
875; CHECK-NEXT:    vmsltu.vv v0, v10, v8
876; CHECK-NEXT:    ret
877  %vc = icmp ugt <vscale x 8 x i16> %va, %vb
878  ret <vscale x 8 x i1> %vc
879}
880
881define <vscale x 8 x i1> @icmp_ugt_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
882; CHECK-LABEL: icmp_ugt_vx_nxv8i16:
883; CHECK:       # %bb.0:
884; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
885; CHECK-NEXT:    vmsgtu.vx v0, v8, a0
886; CHECK-NEXT:    ret
887  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
888  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
889  %vc = icmp ugt <vscale x 8 x i16> %va, %splat
890  ret <vscale x 8 x i1> %vc
891}
892
893define <vscale x 8 x i1> @icmp_ugt_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
894; CHECK-LABEL: icmp_ugt_xv_nxv8i16:
895; CHECK:       # %bb.0:
896; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
897; CHECK-NEXT:    vmsltu.vx v0, v8, a0
898; CHECK-NEXT:    ret
899  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
900  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
901  %vc = icmp ugt <vscale x 8 x i16> %splat, %va
902  ret <vscale x 8 x i1> %vc
903}
904
905define <vscale x 8 x i1> @icmp_ugt_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
906; CHECK-LABEL: icmp_ugt_vi_nxv8i16_0:
907; CHECK:       # %bb.0:
908; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
909; CHECK-NEXT:    vmsgtu.vi v0, v8, 5
910; CHECK-NEXT:    ret
911  %head = insertelement <vscale x 8 x i16> poison, i16 5, i32 0
912  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
913  %vc = icmp ugt <vscale x 8 x i16> %va, %splat
914  ret <vscale x 8 x i1> %vc
915}
916
917define <vscale x 8 x i1> @icmp_uge_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
918; CHECK-LABEL: icmp_uge_vv_nxv8i16:
919; CHECK:       # %bb.0:
920; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
921; CHECK-NEXT:    vmsleu.vv v0, v10, v8
922; CHECK-NEXT:    ret
923  %vc = icmp uge <vscale x 8 x i16> %va, %vb
924  ret <vscale x 8 x i1> %vc
925}
926
927define <vscale x 8 x i1> @icmp_uge_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
928; CHECK-LABEL: icmp_uge_vx_nxv8i16:
929; CHECK:       # %bb.0:
930; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
931; CHECK-NEXT:    vmv.v.x v10, a0
932; CHECK-NEXT:    vmsleu.vv v0, v10, v8
933; CHECK-NEXT:    ret
934  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
935  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
936  %vc = icmp uge <vscale x 8 x i16> %va, %splat
937  ret <vscale x 8 x i1> %vc
938}
939
940define <vscale x 8 x i1> @icmp_uge_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
941; CHECK-LABEL: icmp_uge_xv_nxv8i16:
942; CHECK:       # %bb.0:
943; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
944; CHECK-NEXT:    vmsleu.vx v0, v8, a0
945; CHECK-NEXT:    ret
946  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
947  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
948  %vc = icmp uge <vscale x 8 x i16> %splat, %va
949  ret <vscale x 8 x i1> %vc
950}
951
952define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
953; CHECK-LABEL: icmp_uge_vi_nxv8i16_0:
954; CHECK:       # %bb.0:
955; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
956; CHECK-NEXT:    vmv.v.i v10, -16
957; CHECK-NEXT:    vmsleu.vv v0, v10, v8
958; CHECK-NEXT:    ret
959  %head = insertelement <vscale x 8 x i16> poison, i16 -16, i32 0
960  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
961  %vc = icmp uge <vscale x 8 x i16> %va, %splat
962  ret <vscale x 8 x i1> %vc
963}
964
965define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_1(<vscale x 8 x i16> %va) {
966; CHECK-LABEL: icmp_uge_vi_nxv8i16_1:
967; CHECK:       # %bb.0:
968; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
969; CHECK-NEXT:    vmsgtu.vi v0, v8, 14
970; CHECK-NEXT:    ret
971  %head = insertelement <vscale x 8 x i16> poison, i16 15, i32 0
972  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
973  %vc = icmp uge <vscale x 8 x i16> %va, %splat
974  ret <vscale x 8 x i1> %vc
975}
976
977define <vscale x 8 x i1> @icmp_uge_iv_nxv8i16_1(<vscale x 8 x i16> %va) {
978; CHECK-LABEL: icmp_uge_iv_nxv8i16_1:
979; CHECK:       # %bb.0:
980; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
981; CHECK-NEXT:    vmsleu.vi v0, v8, 15
982; CHECK-NEXT:    ret
983  %head = insertelement <vscale x 8 x i16> poison, i16 15, i32 0
984  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
985  %vc = icmp uge <vscale x 8 x i16> %splat, %va
986  ret <vscale x 8 x i1> %vc
987}
988
989define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_2(<vscale x 8 x i16> %va) {
990; CHECK-LABEL: icmp_uge_vi_nxv8i16_2:
991; CHECK:       # %bb.0:
992; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
993; CHECK-NEXT:    vmset.m v0
994; CHECK-NEXT:    ret
995  %head = insertelement <vscale x 8 x i16> poison, i16 0, i32 0
996  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
997  %vc = icmp uge <vscale x 8 x i16> %va, %splat
998  ret <vscale x 8 x i1> %vc
999}
1000
1001define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_3(<vscale x 8 x i16> %va) {
1002; CHECK-LABEL: icmp_uge_vi_nxv8i16_3:
1003; CHECK:       # %bb.0:
1004; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
1005; CHECK-NEXT:    vmsgtu.vi v0, v8, 0
1006; CHECK-NEXT:    ret
1007  %head = insertelement <vscale x 8 x i16> poison, i16 1, i32 0
1008  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
1009  %vc = icmp uge <vscale x 8 x i16> %va, %splat
1010  ret <vscale x 8 x i1> %vc
1011}
1012
1013define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_4(<vscale x 8 x i16> %va) {
1014; CHECK-LABEL: icmp_uge_vi_nxv8i16_4:
1015; CHECK:       # %bb.0:
1016; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
1017; CHECK-NEXT:    vmsgtu.vi v0, v8, -16
1018; CHECK-NEXT:    ret
1019  %head = insertelement <vscale x 8 x i16> poison, i16 -15, i32 0
1020  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
1021  %vc = icmp uge <vscale x 8 x i16> %va, %splat
1022  ret <vscale x 8 x i1> %vc
1023}
1024
1025define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_5(<vscale x 8 x i16> %va) {
1026; CHECK-LABEL: icmp_uge_vi_nxv8i16_5:
1027; CHECK:       # %bb.0:
1028; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
1029; CHECK-NEXT:    vmsgtu.vi v0, v8, 15
1030; CHECK-NEXT:    ret
1031  %head = insertelement <vscale x 8 x i16> poison, i16 16, i32 0
1032  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
1033  %vc = icmp uge <vscale x 8 x i16> %va, %splat
1034  ret <vscale x 8 x i1> %vc
1035}
1036
1037define <vscale x 8 x i1> @icmp_ult_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
1038; CHECK-LABEL: icmp_ult_vv_nxv8i16:
1039; CHECK:       # %bb.0:
1040; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
1041; CHECK-NEXT:    vmsltu.vv v0, v8, v10
1042; CHECK-NEXT:    ret
1043  %vc = icmp ult <vscale x 8 x i16> %va, %vb
1044  ret <vscale x 8 x i1> %vc
1045}
1046
1047define <vscale x 8 x i1> @icmp_ult_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
1048; CHECK-LABEL: icmp_ult_vx_nxv8i16:
1049; CHECK:       # %bb.0:
1050; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
1051; CHECK-NEXT:    vmsltu.vx v0, v8, a0
1052; CHECK-NEXT:    ret
1053  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
1054  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
1055  %vc = icmp ult <vscale x 8 x i16> %va, %splat
1056  ret <vscale x 8 x i1> %vc
1057}
1058
1059define <vscale x 8 x i1> @icmp_ult_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
1060; CHECK-LABEL: icmp_ult_xv_nxv8i16:
1061; CHECK:       # %bb.0:
1062; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
1063; CHECK-NEXT:    vmsgtu.vx v0, v8, a0
1064; CHECK-NEXT:    ret
1065  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
1066  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
1067  %vc = icmp ult <vscale x 8 x i16> %splat, %va
1068  ret <vscale x 8 x i1> %vc
1069}
1070
1071define <vscale x 8 x i1> @icmp_ult_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
1072; CHECK-LABEL: icmp_ult_vi_nxv8i16_0:
1073; CHECK:       # %bb.0:
1074; CHECK-NEXT:    li a0, -16
1075; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
1076; CHECK-NEXT:    vmsltu.vx v0, v8, a0
1077; CHECK-NEXT:    ret
1078  %head = insertelement <vscale x 8 x i16> poison, i16 -16, i32 0
1079  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
1080  %vc = icmp ult <vscale x 8 x i16> %va, %splat
1081  ret <vscale x 8 x i1> %vc
1082}
1083
1084define <vscale x 8 x i1> @icmp_ult_vi_nxv8i16_1(<vscale x 8 x i16> %va) {
1085; CHECK-LABEL: icmp_ult_vi_nxv8i16_1:
1086; CHECK:       # %bb.0:
1087; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
1088; CHECK-NEXT:    vmsleu.vi v0, v8, -16
1089; CHECK-NEXT:    ret
1090  %head = insertelement <vscale x 8 x i16> poison, i16 -15, i32 0
1091  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
1092  %vc = icmp ult <vscale x 8 x i16> %va, %splat
1093  ret <vscale x 8 x i1> %vc
1094}
1095
1096define <vscale x 8 x i1> @icmp_ult_iv_nxv8i16_1(<vscale x 8 x i16> %va) {
1097; CHECK-LABEL: icmp_ult_iv_nxv8i16_1:
1098; CHECK:       # %bb.0:
1099; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
1100; CHECK-NEXT:    vmsgtu.vi v0, v8, -15
1101; CHECK-NEXT:    ret
1102  %head = insertelement <vscale x 8 x i16> poison, i16 -15, i32 0
1103  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
1104  %vc = icmp ult <vscale x 8 x i16> %splat, %va
1105  ret <vscale x 8 x i1> %vc
1106}
1107
1108define <vscale x 8 x i1> @icmp_ult_vi_nxv8i16_2(<vscale x 8 x i16> %va) {
1109; CHECK-LABEL: icmp_ult_vi_nxv8i16_2:
1110; CHECK:       # %bb.0:
1111; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
1112; CHECK-NEXT:    vmclr.m v0
1113; CHECK-NEXT:    ret
1114  %head = insertelement <vscale x 8 x i16> poison, i16 0, i32 0
1115  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
1116  %vc = icmp ult <vscale x 8 x i16> %va, %splat
1117  ret <vscale x 8 x i1> %vc
1118}
1119
1120define <vscale x 8 x i1> @icmp_ult_vi_nxv8i16_3(<vscale x 8 x i16> %va) {
1121; CHECK-LABEL: icmp_ult_vi_nxv8i16_3:
1122; CHECK:       # %bb.0:
1123; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
1124; CHECK-NEXT:    vmseq.vi v0, v8, 0
1125; CHECK-NEXT:    ret
1126  %head = insertelement <vscale x 8 x i16> poison, i16 1, i32 0
1127  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
1128  %vc = icmp ult <vscale x 8 x i16> %va, %splat
1129  ret <vscale x 8 x i1> %vc
1130}
1131
1132define <vscale x 8 x i1> @icmp_ult_vi_nxv8i16_4(<vscale x 8 x i16> %va) {
1133; CHECK-LABEL: icmp_ult_vi_nxv8i16_4:
1134; CHECK:       # %bb.0:
1135; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
1136; CHECK-NEXT:    vmsleu.vi v0, v8, 15
1137; CHECK-NEXT:    ret
1138  %head = insertelement <vscale x 8 x i16> poison, i16 16, i32 0
1139  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
1140  %vc = icmp ult <vscale x 8 x i16> %va, %splat
1141  ret <vscale x 8 x i1> %vc
1142}
1143
1144define <vscale x 8 x i1> @icmp_ule_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
1145; CHECK-LABEL: icmp_ule_vv_nxv8i16:
1146; CHECK:       # %bb.0:
1147; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
1148; CHECK-NEXT:    vmsleu.vv v0, v8, v10
1149; CHECK-NEXT:    ret
1150  %vc = icmp ule <vscale x 8 x i16> %va, %vb
1151  ret <vscale x 8 x i1> %vc
1152}
1153
1154define <vscale x 8 x i1> @icmp_ule_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
1155; CHECK-LABEL: icmp_ule_vx_nxv8i16:
1156; CHECK:       # %bb.0:
1157; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
1158; CHECK-NEXT:    vmsleu.vx v0, v8, a0
1159; CHECK-NEXT:    ret
1160  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
1161  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
1162  %vc = icmp ule <vscale x 8 x i16> %va, %splat
1163  ret <vscale x 8 x i1> %vc
1164}
1165
1166define <vscale x 8 x i1> @icmp_ule_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
1167; CHECK-LABEL: icmp_ule_xv_nxv8i16:
1168; CHECK:       # %bb.0:
1169; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
1170; CHECK-NEXT:    vmv.v.x v10, a0
1171; CHECK-NEXT:    vmsleu.vv v0, v10, v8
1172; CHECK-NEXT:    ret
1173  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
1174  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
1175  %vc = icmp ule <vscale x 8 x i16> %splat, %va
1176  ret <vscale x 8 x i1> %vc
1177}
1178
1179define <vscale x 8 x i1> @icmp_ule_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
1180; CHECK-LABEL: icmp_ule_vi_nxv8i16_0:
1181; CHECK:       # %bb.0:
1182; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
1183; CHECK-NEXT:    vmsleu.vi v0, v8, 5
1184; CHECK-NEXT:    ret
1185  %head = insertelement <vscale x 8 x i16> poison, i16 5, i32 0
1186  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
1187  %vc = icmp ule <vscale x 8 x i16> %va, %splat
1188  ret <vscale x 8 x i1> %vc
1189}
1190
1191define <vscale x 8 x i1> @icmp_sgt_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
1192; CHECK-LABEL: icmp_sgt_vv_nxv8i16:
1193; CHECK:       # %bb.0:
1194; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
1195; CHECK-NEXT:    vmslt.vv v0, v10, v8
1196; CHECK-NEXT:    ret
1197  %vc = icmp sgt <vscale x 8 x i16> %va, %vb
1198  ret <vscale x 8 x i1> %vc
1199}
1200
1201define <vscale x 8 x i1> @icmp_sgt_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
1202; CHECK-LABEL: icmp_sgt_vx_nxv8i16:
1203; CHECK:       # %bb.0:
1204; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
1205; CHECK-NEXT:    vmsgt.vx v0, v8, a0
1206; CHECK-NEXT:    ret
1207  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
1208  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
1209  %vc = icmp sgt <vscale x 8 x i16> %va, %splat
1210  ret <vscale x 8 x i1> %vc
1211}
1212
1213define <vscale x 8 x i1> @icmp_sgt_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
1214; CHECK-LABEL: icmp_sgt_xv_nxv8i16:
1215; CHECK:       # %bb.0:
1216; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
1217; CHECK-NEXT:    vmslt.vx v0, v8, a0
1218; CHECK-NEXT:    ret
1219  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
1220  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
1221  %vc = icmp sgt <vscale x 8 x i16> %splat, %va
1222  ret <vscale x 8 x i1> %vc
1223}
1224
1225define <vscale x 8 x i1> @icmp_sgt_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
1226; CHECK-LABEL: icmp_sgt_vi_nxv8i16_0:
1227; CHECK:       # %bb.0:
1228; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
1229; CHECK-NEXT:    vmsgt.vi v0, v8, 5
1230; CHECK-NEXT:    ret
1231  %head = insertelement <vscale x 8 x i16> poison, i16 5, i32 0
1232  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
1233  %vc = icmp sgt <vscale x 8 x i16> %va, %splat
1234  ret <vscale x 8 x i1> %vc
1235}
1236
1237define <vscale x 8 x i1> @icmp_sge_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
1238; CHECK-LABEL: icmp_sge_vv_nxv8i16:
1239; CHECK:       # %bb.0:
1240; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
1241; CHECK-NEXT:    vmsle.vv v0, v10, v8
1242; CHECK-NEXT:    ret
1243  %vc = icmp sge <vscale x 8 x i16> %va, %vb
1244  ret <vscale x 8 x i1> %vc
1245}
1246
1247define <vscale x 8 x i1> @icmp_sge_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
1248; CHECK-LABEL: icmp_sge_vx_nxv8i16:
1249; CHECK:       # %bb.0:
1250; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
1251; CHECK-NEXT:    vmv.v.x v10, a0
1252; CHECK-NEXT:    vmsle.vv v0, v10, v8
1253; CHECK-NEXT:    ret
1254  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
1255  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
1256  %vc = icmp sge <vscale x 8 x i16> %va, %splat
1257  ret <vscale x 8 x i1> %vc
1258}
1259
1260define <vscale x 8 x i1> @icmp_sge_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
1261; CHECK-LABEL: icmp_sge_xv_nxv8i16:
1262; CHECK:       # %bb.0:
1263; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
1264; CHECK-NEXT:    vmsle.vx v0, v8, a0
1265; CHECK-NEXT:    ret
1266  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
1267  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
1268  %vc = icmp sge <vscale x 8 x i16> %splat, %va
1269  ret <vscale x 8 x i1> %vc
1270}
1271
1272define <vscale x 8 x i1> @icmp_sge_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
1273; CHECK-LABEL: icmp_sge_vi_nxv8i16_0:
1274; CHECK:       # %bb.0:
1275; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
1276; CHECK-NEXT:    vmv.v.i v10, -16
1277; CHECK-NEXT:    vmsle.vv v0, v10, v8
1278; CHECK-NEXT:    ret
1279  %head = insertelement <vscale x 8 x i16> poison, i16 -16, i32 0
1280  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
1281  %vc = icmp sge <vscale x 8 x i16> %va, %splat
1282  ret <vscale x 8 x i1> %vc
1283}
1284
1285define <vscale x 8 x i1> @icmp_sge_vi_nxv8i16_1(<vscale x 8 x i16> %va) {
1286; CHECK-LABEL: icmp_sge_vi_nxv8i16_1:
1287; CHECK:       # %bb.0:
1288; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
1289; CHECK-NEXT:    vmsgt.vi v0, v8, -16
1290; CHECK-NEXT:    ret
1291  %head = insertelement <vscale x 8 x i16> poison, i16 -15, i32 0
1292  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
1293  %vc = icmp sge <vscale x 8 x i16> %va, %splat
1294  ret <vscale x 8 x i1> %vc
1295}
1296
1297define <vscale x 8 x i1> @icmp_sge_iv_nxv8i16_1(<vscale x 8 x i16> %va) {
1298; CHECK-LABEL: icmp_sge_iv_nxv8i16_1:
1299; CHECK:       # %bb.0:
1300; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
1301; CHECK-NEXT:    vmsle.vi v0, v8, -15
1302; CHECK-NEXT:    ret
1303  %head = insertelement <vscale x 8 x i16> poison, i16 -15, i32 0
1304  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
1305  %vc = icmp sge <vscale x 8 x i16> %splat, %va
1306  ret <vscale x 8 x i1> %vc
1307}
1308
1309define <vscale x 8 x i1> @icmp_sge_vi_nxv8i16_2(<vscale x 8 x i16> %va) {
1310; CHECK-LABEL: icmp_sge_vi_nxv8i16_2:
1311; CHECK:       # %bb.0:
1312; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
1313; CHECK-NEXT:    vmsgt.vi v0, v8, -1
1314; CHECK-NEXT:    ret
1315  %head = insertelement <vscale x 8 x i16> poison, i16 0, i32 0
1316  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
1317  %vc = icmp sge <vscale x 8 x i16> %va, %splat
1318  ret <vscale x 8 x i1> %vc
1319}
1320
1321define <vscale x 8 x i1> @icmp_sge_vi_nxv8i16_3(<vscale x 8 x i16> %va) {
1322; CHECK-LABEL: icmp_sge_vi_nxv8i16_3:
1323; CHECK:       # %bb.0:
1324; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
1325; CHECK-NEXT:    vmsgt.vi v0, v8, 15
1326; CHECK-NEXT:    ret
1327  %head = insertelement <vscale x 8 x i16> poison, i16 16, i32 0
1328  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
1329  %vc = icmp sge <vscale x 8 x i16> %va, %splat
1330  ret <vscale x 8 x i1> %vc
1331}
1332
1333define <vscale x 8 x i1> @icmp_slt_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
1334; CHECK-LABEL: icmp_slt_vv_nxv8i16:
1335; CHECK:       # %bb.0:
1336; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
1337; CHECK-NEXT:    vmslt.vv v0, v8, v10
1338; CHECK-NEXT:    ret
1339  %vc = icmp slt <vscale x 8 x i16> %va, %vb
1340  ret <vscale x 8 x i1> %vc
1341}
1342
1343define <vscale x 8 x i1> @icmp_slt_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
1344; CHECK-LABEL: icmp_slt_vx_nxv8i16:
1345; CHECK:       # %bb.0:
1346; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
1347; CHECK-NEXT:    vmslt.vx v0, v8, a0
1348; CHECK-NEXT:    ret
1349  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
1350  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
1351  %vc = icmp slt <vscale x 8 x i16> %va, %splat
1352  ret <vscale x 8 x i1> %vc
1353}
1354
1355define <vscale x 8 x i1> @icmp_slt_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
1356; CHECK-LABEL: icmp_slt_xv_nxv8i16:
1357; CHECK:       # %bb.0:
1358; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
1359; CHECK-NEXT:    vmsgt.vx v0, v8, a0
1360; CHECK-NEXT:    ret
1361  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
1362  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
1363  %vc = icmp slt <vscale x 8 x i16> %splat, %va
1364  ret <vscale x 8 x i1> %vc
1365}
1366
1367define <vscale x 8 x i1> @icmp_slt_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
1368; CHECK-LABEL: icmp_slt_vi_nxv8i16_0:
1369; CHECK:       # %bb.0:
1370; CHECK-NEXT:    li a0, -16
1371; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
1372; CHECK-NEXT:    vmslt.vx v0, v8, a0
1373; CHECK-NEXT:    ret
1374  %head = insertelement <vscale x 8 x i16> poison, i16 -16, i32 0
1375  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
1376  %vc = icmp slt <vscale x 8 x i16> %va, %splat
1377  ret <vscale x 8 x i1> %vc
1378}
1379
1380define <vscale x 8 x i1> @icmp_slt_vi_nxv8i16_1(<vscale x 8 x i16> %va) {
1381; CHECK-LABEL: icmp_slt_vi_nxv8i16_1:
1382; CHECK:       # %bb.0:
1383; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
1384; CHECK-NEXT:    vmsle.vi v0, v8, -16
1385; CHECK-NEXT:    ret
1386  %head = insertelement <vscale x 8 x i16> poison, i16 -15, i32 0
1387  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
1388  %vc = icmp slt <vscale x 8 x i16> %va, %splat
1389  ret <vscale x 8 x i1> %vc
1390}
1391
1392define <vscale x 8 x i1> @icmp_slt_iv_nxv8i16_1(<vscale x 8 x i16> %va) {
1393; CHECK-LABEL: icmp_slt_iv_nxv8i16_1:
1394; CHECK:       # %bb.0:
1395; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
1396; CHECK-NEXT:    vmsgt.vi v0, v8, -15
1397; CHECK-NEXT:    ret
1398  %head = insertelement <vscale x 8 x i16> poison, i16 -15, i32 0
1399  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
1400  %vc = icmp slt <vscale x 8 x i16> %splat, %va
1401  ret <vscale x 8 x i1> %vc
1402}
1403
1404define <vscale x 8 x i1> @icmp_slt_vi_nxv8i16_2(<vscale x 8 x i16> %va) {
1405; CHECK-LABEL: icmp_slt_vi_nxv8i16_2:
1406; CHECK:       # %bb.0:
1407; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
1408; CHECK-NEXT:    vmslt.vx v0, v8, zero
1409; CHECK-NEXT:    ret
1410  %head = insertelement <vscale x 8 x i16> poison, i16 0, i32 0
1411  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
1412  %vc = icmp slt <vscale x 8 x i16> %va, %splat
1413  ret <vscale x 8 x i1> %vc
1414}
1415
1416define <vscale x 8 x i1> @icmp_slt_vi_nxv8i16_3(<vscale x 8 x i16> %va) {
1417; CHECK-LABEL: icmp_slt_vi_nxv8i16_3:
1418; CHECK:       # %bb.0:
1419; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
1420; CHECK-NEXT:    vmsle.vi v0, v8, 15
1421; CHECK-NEXT:    ret
1422  %head = insertelement <vscale x 8 x i16> poison, i16 16, i32 0
1423  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
1424  %vc = icmp slt <vscale x 8 x i16> %va, %splat
1425  ret <vscale x 8 x i1> %vc
1426}
1427
1428define <vscale x 8 x i1> @icmp_sle_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) {
1429; CHECK-LABEL: icmp_sle_vv_nxv8i16:
1430; CHECK:       # %bb.0:
1431; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
1432; CHECK-NEXT:    vmsle.vv v0, v8, v10
1433; CHECK-NEXT:    ret
1434  %vc = icmp sle <vscale x 8 x i16> %va, %vb
1435  ret <vscale x 8 x i1> %vc
1436}
1437
1438define <vscale x 8 x i1> @icmp_sle_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
1439; CHECK-LABEL: icmp_sle_vx_nxv8i16:
1440; CHECK:       # %bb.0:
1441; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
1442; CHECK-NEXT:    vmsle.vx v0, v8, a0
1443; CHECK-NEXT:    ret
1444  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
1445  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
1446  %vc = icmp sle <vscale x 8 x i16> %va, %splat
1447  ret <vscale x 8 x i1> %vc
1448}
1449
1450define <vscale x 8 x i1> @icmp_sle_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) {
1451; CHECK-LABEL: icmp_sle_xv_nxv8i16:
1452; CHECK:       # %bb.0:
1453; CHECK-NEXT:    vsetvli a1, zero, e16, m2, ta, mu
1454; CHECK-NEXT:    vmv.v.x v10, a0
1455; CHECK-NEXT:    vmsle.vv v0, v10, v8
1456; CHECK-NEXT:    ret
1457  %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0
1458  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
1459  %vc = icmp sle <vscale x 8 x i16> %splat, %va
1460  ret <vscale x 8 x i1> %vc
1461}
1462
1463define <vscale x 8 x i1> @icmp_sle_vi_nxv8i16_0(<vscale x 8 x i16> %va) {
1464; CHECK-LABEL: icmp_sle_vi_nxv8i16_0:
1465; CHECK:       # %bb.0:
1466; CHECK-NEXT:    vsetvli a0, zero, e16, m2, ta, mu
1467; CHECK-NEXT:    vmsle.vi v0, v8, 5
1468; CHECK-NEXT:    ret
1469  %head = insertelement <vscale x 8 x i16> poison, i16 5, i32 0
1470  %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer
1471  %vc = icmp sle <vscale x 8 x i16> %va, %splat
1472  ret <vscale x 8 x i1> %vc
1473}
1474
1475define <vscale x 8 x i1> @icmp_eq_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
1476; CHECK-LABEL: icmp_eq_vv_nxv8i32:
1477; CHECK:       # %bb.0:
1478; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
1479; CHECK-NEXT:    vmseq.vv v0, v8, v12
1480; CHECK-NEXT:    ret
1481  %vc = icmp eq <vscale x 8 x i32> %va, %vb
1482  ret <vscale x 8 x i1> %vc
1483}
1484
1485define <vscale x 8 x i1> @icmp_eq_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
1486; CHECK-LABEL: icmp_eq_vx_nxv8i32:
1487; CHECK:       # %bb.0:
1488; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
1489; CHECK-NEXT:    vmseq.vx v0, v8, a0
1490; CHECK-NEXT:    ret
1491  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
1492  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
1493  %vc = icmp eq <vscale x 8 x i32> %va, %splat
1494  ret <vscale x 8 x i1> %vc
1495}
1496
1497define <vscale x 8 x i1> @icmp_eq_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
1498; CHECK-LABEL: icmp_eq_xv_nxv8i32:
1499; CHECK:       # %bb.0:
1500; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
1501; CHECK-NEXT:    vmseq.vx v0, v8, a0
1502; CHECK-NEXT:    ret
1503  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
1504  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
1505  %vc = icmp eq <vscale x 8 x i32> %splat, %va
1506  ret <vscale x 8 x i1> %vc
1507}
1508
1509define <vscale x 8 x i1> @icmp_eq_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
1510; CHECK-LABEL: icmp_eq_vi_nxv8i32_0:
1511; CHECK:       # %bb.0:
1512; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
1513; CHECK-NEXT:    vmseq.vi v0, v8, 0
1514; CHECK-NEXT:    ret
1515  %head = insertelement <vscale x 8 x i32> poison, i32 0, i32 0
1516  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
1517  %vc = icmp eq <vscale x 8 x i32> %va, %splat
1518  ret <vscale x 8 x i1> %vc
1519}
1520
1521define <vscale x 8 x i1> @icmp_eq_vi_nxv8i32_1(<vscale x 8 x i32> %va) {
1522; CHECK-LABEL: icmp_eq_vi_nxv8i32_1:
1523; CHECK:       # %bb.0:
1524; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
1525; CHECK-NEXT:    vmseq.vi v0, v8, 5
1526; CHECK-NEXT:    ret
1527  %head = insertelement <vscale x 8 x i32> poison, i32 5, i32 0
1528  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
1529  %vc = icmp eq <vscale x 8 x i32> %va, %splat
1530  ret <vscale x 8 x i1> %vc
1531}
1532
1533define <vscale x 8 x i1> @icmp_eq_iv_nxv8i32_1(<vscale x 8 x i32> %va) {
1534; CHECK-LABEL: icmp_eq_iv_nxv8i32_1:
1535; CHECK:       # %bb.0:
1536; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
1537; CHECK-NEXT:    vmseq.vi v0, v8, 5
1538; CHECK-NEXT:    ret
1539  %head = insertelement <vscale x 8 x i32> poison, i32 5, i32 0
1540  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
1541  %vc = icmp eq <vscale x 8 x i32> %splat, %va
1542  ret <vscale x 8 x i1> %vc
1543}
1544
1545define <vscale x 8 x i1> @icmp_ne_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
1546; CHECK-LABEL: icmp_ne_vv_nxv8i32:
1547; CHECK:       # %bb.0:
1548; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
1549; CHECK-NEXT:    vmsne.vv v0, v8, v12
1550; CHECK-NEXT:    ret
1551  %vc = icmp ne <vscale x 8 x i32> %va, %vb
1552  ret <vscale x 8 x i1> %vc
1553}
1554
1555define <vscale x 8 x i1> @icmp_ne_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
1556; CHECK-LABEL: icmp_ne_vx_nxv8i32:
1557; CHECK:       # %bb.0:
1558; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
1559; CHECK-NEXT:    vmsne.vx v0, v8, a0
1560; CHECK-NEXT:    ret
1561  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
1562  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
1563  %vc = icmp ne <vscale x 8 x i32> %va, %splat
1564  ret <vscale x 8 x i1> %vc
1565}
1566
1567define <vscale x 8 x i1> @icmp_ne_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
1568; CHECK-LABEL: icmp_ne_xv_nxv8i32:
1569; CHECK:       # %bb.0:
1570; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
1571; CHECK-NEXT:    vmsne.vx v0, v8, a0
1572; CHECK-NEXT:    ret
1573  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
1574  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
1575  %vc = icmp ne <vscale x 8 x i32> %splat, %va
1576  ret <vscale x 8 x i1> %vc
1577}
1578
1579define <vscale x 8 x i1> @icmp_ne_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
1580; CHECK-LABEL: icmp_ne_vi_nxv8i32_0:
1581; CHECK:       # %bb.0:
1582; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
1583; CHECK-NEXT:    vmsne.vi v0, v8, 5
1584; CHECK-NEXT:    ret
1585  %head = insertelement <vscale x 8 x i32> poison, i32 5, i32 0
1586  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
1587  %vc = icmp ne <vscale x 8 x i32> %va, %splat
1588  ret <vscale x 8 x i1> %vc
1589}
1590
1591define <vscale x 8 x i1> @icmp_ugt_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
1592; CHECK-LABEL: icmp_ugt_vv_nxv8i32:
1593; CHECK:       # %bb.0:
1594; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
1595; CHECK-NEXT:    vmsltu.vv v0, v12, v8
1596; CHECK-NEXT:    ret
1597  %vc = icmp ugt <vscale x 8 x i32> %va, %vb
1598  ret <vscale x 8 x i1> %vc
1599}
1600
1601define <vscale x 8 x i1> @icmp_ugt_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
1602; CHECK-LABEL: icmp_ugt_vx_nxv8i32:
1603; CHECK:       # %bb.0:
1604; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
1605; CHECK-NEXT:    vmsgtu.vx v0, v8, a0
1606; CHECK-NEXT:    ret
1607  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
1608  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
1609  %vc = icmp ugt <vscale x 8 x i32> %va, %splat
1610  ret <vscale x 8 x i1> %vc
1611}
1612
1613define <vscale x 8 x i1> @icmp_ugt_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
1614; CHECK-LABEL: icmp_ugt_xv_nxv8i32:
1615; CHECK:       # %bb.0:
1616; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
1617; CHECK-NEXT:    vmsltu.vx v0, v8, a0
1618; CHECK-NEXT:    ret
1619  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
1620  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
1621  %vc = icmp ugt <vscale x 8 x i32> %splat, %va
1622  ret <vscale x 8 x i1> %vc
1623}
1624
1625define <vscale x 8 x i1> @icmp_ugt_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
1626; CHECK-LABEL: icmp_ugt_vi_nxv8i32_0:
1627; CHECK:       # %bb.0:
1628; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
1629; CHECK-NEXT:    vmsgtu.vi v0, v8, 5
1630; CHECK-NEXT:    ret
1631  %head = insertelement <vscale x 8 x i32> poison, i32 5, i32 0
1632  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
1633  %vc = icmp ugt <vscale x 8 x i32> %va, %splat
1634  ret <vscale x 8 x i1> %vc
1635}
1636
1637define <vscale x 8 x i1> @icmp_uge_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
1638; CHECK-LABEL: icmp_uge_vv_nxv8i32:
1639; CHECK:       # %bb.0:
1640; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
1641; CHECK-NEXT:    vmsleu.vv v0, v12, v8
1642; CHECK-NEXT:    ret
1643  %vc = icmp uge <vscale x 8 x i32> %va, %vb
1644  ret <vscale x 8 x i1> %vc
1645}
1646
1647define <vscale x 8 x i1> @icmp_uge_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
1648; CHECK-LABEL: icmp_uge_vx_nxv8i32:
1649; CHECK:       # %bb.0:
1650; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
1651; CHECK-NEXT:    vmv.v.x v12, a0
1652; CHECK-NEXT:    vmsleu.vv v0, v12, v8
1653; CHECK-NEXT:    ret
1654  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
1655  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
1656  %vc = icmp uge <vscale x 8 x i32> %va, %splat
1657  ret <vscale x 8 x i1> %vc
1658}
1659
1660define <vscale x 8 x i1> @icmp_uge_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
1661; CHECK-LABEL: icmp_uge_xv_nxv8i32:
1662; CHECK:       # %bb.0:
1663; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
1664; CHECK-NEXT:    vmsleu.vx v0, v8, a0
1665; CHECK-NEXT:    ret
1666  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
1667  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
1668  %vc = icmp uge <vscale x 8 x i32> %splat, %va
1669  ret <vscale x 8 x i1> %vc
1670}
1671
1672define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
1673; CHECK-LABEL: icmp_uge_vi_nxv8i32_0:
1674; CHECK:       # %bb.0:
1675; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
1676; CHECK-NEXT:    vmv.v.i v12, -16
1677; CHECK-NEXT:    vmsleu.vv v0, v12, v8
1678; CHECK-NEXT:    ret
1679  %head = insertelement <vscale x 8 x i32> poison, i32 -16, i32 0
1680  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
1681  %vc = icmp uge <vscale x 8 x i32> %va, %splat
1682  ret <vscale x 8 x i1> %vc
1683}
1684
1685define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_1(<vscale x 8 x i32> %va) {
1686; CHECK-LABEL: icmp_uge_vi_nxv8i32_1:
1687; CHECK:       # %bb.0:
1688; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
1689; CHECK-NEXT:    vmsgtu.vi v0, v8, 14
1690; CHECK-NEXT:    ret
1691  %head = insertelement <vscale x 8 x i32> poison, i32 15, i32 0
1692  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
1693  %vc = icmp uge <vscale x 8 x i32> %va, %splat
1694  ret <vscale x 8 x i1> %vc
1695}
1696
1697define <vscale x 8 x i1> @icmp_uge_iv_nxv8i32_1(<vscale x 8 x i32> %va) {
1698; CHECK-LABEL: icmp_uge_iv_nxv8i32_1:
1699; CHECK:       # %bb.0:
1700; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
1701; CHECK-NEXT:    vmsleu.vi v0, v8, 15
1702; CHECK-NEXT:    ret
1703  %head = insertelement <vscale x 8 x i32> poison, i32 15, i32 0
1704  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
1705  %vc = icmp uge <vscale x 8 x i32> %splat, %va
1706  ret <vscale x 8 x i1> %vc
1707}
1708
1709define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_2(<vscale x 8 x i32> %va) {
1710; CHECK-LABEL: icmp_uge_vi_nxv8i32_2:
1711; CHECK:       # %bb.0:
1712; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
1713; CHECK-NEXT:    vmset.m v0
1714; CHECK-NEXT:    ret
1715  %head = insertelement <vscale x 8 x i32> poison, i32 0, i32 0
1716  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
1717  %vc = icmp uge <vscale x 8 x i32> %va, %splat
1718  ret <vscale x 8 x i1> %vc
1719}
1720
1721define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_3(<vscale x 8 x i32> %va) {
1722; CHECK-LABEL: icmp_uge_vi_nxv8i32_3:
1723; CHECK:       # %bb.0:
1724; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
1725; CHECK-NEXT:    vmsgtu.vi v0, v8, 0
1726; CHECK-NEXT:    ret
1727  %head = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
1728  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
1729  %vc = icmp uge <vscale x 8 x i32> %va, %splat
1730  ret <vscale x 8 x i1> %vc
1731}
1732
1733define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_4(<vscale x 8 x i32> %va) {
1734; CHECK-LABEL: icmp_uge_vi_nxv8i32_4:
1735; CHECK:       # %bb.0:
1736; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
1737; CHECK-NEXT:    vmsgtu.vi v0, v8, -16
1738; CHECK-NEXT:    ret
1739  %head = insertelement <vscale x 8 x i32> poison, i32 -15, i32 0
1740  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
1741  %vc = icmp uge <vscale x 8 x i32> %va, %splat
1742  ret <vscale x 8 x i1> %vc
1743}
1744
1745define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_5(<vscale x 8 x i32> %va) {
1746; CHECK-LABEL: icmp_uge_vi_nxv8i32_5:
1747; CHECK:       # %bb.0:
1748; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
1749; CHECK-NEXT:    vmsgtu.vi v0, v8, 15
1750; CHECK-NEXT:    ret
1751  %head = insertelement <vscale x 8 x i32> poison, i32 16, i32 0
1752  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
1753  %vc = icmp uge <vscale x 8 x i32> %va, %splat
1754  ret <vscale x 8 x i1> %vc
1755}
1756
1757define <vscale x 8 x i1> @icmp_ult_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
1758; CHECK-LABEL: icmp_ult_vv_nxv8i32:
1759; CHECK:       # %bb.0:
1760; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
1761; CHECK-NEXT:    vmsltu.vv v0, v8, v12
1762; CHECK-NEXT:    ret
1763  %vc = icmp ult <vscale x 8 x i32> %va, %vb
1764  ret <vscale x 8 x i1> %vc
1765}
1766
1767define <vscale x 8 x i1> @icmp_ult_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
1768; CHECK-LABEL: icmp_ult_vx_nxv8i32:
1769; CHECK:       # %bb.0:
1770; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
1771; CHECK-NEXT:    vmsltu.vx v0, v8, a0
1772; CHECK-NEXT:    ret
1773  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
1774  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
1775  %vc = icmp ult <vscale x 8 x i32> %va, %splat
1776  ret <vscale x 8 x i1> %vc
1777}
1778
1779define <vscale x 8 x i1> @icmp_ult_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
1780; CHECK-LABEL: icmp_ult_xv_nxv8i32:
1781; CHECK:       # %bb.0:
1782; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
1783; CHECK-NEXT:    vmsgtu.vx v0, v8, a0
1784; CHECK-NEXT:    ret
1785  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
1786  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
1787  %vc = icmp ult <vscale x 8 x i32> %splat, %va
1788  ret <vscale x 8 x i1> %vc
1789}
1790
1791define <vscale x 8 x i1> @icmp_ult_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
1792; CHECK-LABEL: icmp_ult_vi_nxv8i32_0:
1793; CHECK:       # %bb.0:
1794; CHECK-NEXT:    li a0, -16
1795; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
1796; CHECK-NEXT:    vmsltu.vx v0, v8, a0
1797; CHECK-NEXT:    ret
1798  %head = insertelement <vscale x 8 x i32> poison, i32 -16, i32 0
1799  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
1800  %vc = icmp ult <vscale x 8 x i32> %va, %splat
1801  ret <vscale x 8 x i1> %vc
1802}
1803
1804define <vscale x 8 x i1> @icmp_ult_vi_nxv8i32_1(<vscale x 8 x i32> %va) {
1805; CHECK-LABEL: icmp_ult_vi_nxv8i32_1:
1806; CHECK:       # %bb.0:
1807; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
1808; CHECK-NEXT:    vmsleu.vi v0, v8, -16
1809; CHECK-NEXT:    ret
1810  %head = insertelement <vscale x 8 x i32> poison, i32 -15, i32 0
1811  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
1812  %vc = icmp ult <vscale x 8 x i32> %va, %splat
1813  ret <vscale x 8 x i1> %vc
1814}
1815
1816define <vscale x 8 x i1> @icmp_ult_iv_nxv8i32_1(<vscale x 8 x i32> %va) {
1817; CHECK-LABEL: icmp_ult_iv_nxv8i32_1:
1818; CHECK:       # %bb.0:
1819; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
1820; CHECK-NEXT:    vmsgtu.vi v0, v8, -15
1821; CHECK-NEXT:    ret
1822  %head = insertelement <vscale x 8 x i32> poison, i32 -15, i32 0
1823  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
1824  %vc = icmp ult <vscale x 8 x i32> %splat, %va
1825  ret <vscale x 8 x i1> %vc
1826}
1827
1828define <vscale x 8 x i1> @icmp_ult_vi_nxv8i32_2(<vscale x 8 x i32> %va) {
1829; CHECK-LABEL: icmp_ult_vi_nxv8i32_2:
1830; CHECK:       # %bb.0:
1831; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
1832; CHECK-NEXT:    vmclr.m v0
1833; CHECK-NEXT:    ret
1834  %head = insertelement <vscale x 8 x i32> poison, i32 0, i32 0
1835  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
1836  %vc = icmp ult <vscale x 8 x i32> %va, %splat
1837  ret <vscale x 8 x i1> %vc
1838}
1839
1840define <vscale x 8 x i1> @icmp_ult_vi_nxv8i32_3(<vscale x 8 x i32> %va) {
1841; CHECK-LABEL: icmp_ult_vi_nxv8i32_3:
1842; CHECK:       # %bb.0:
1843; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
1844; CHECK-NEXT:    vmseq.vi v0, v8, 0
1845; CHECK-NEXT:    ret
1846  %head = insertelement <vscale x 8 x i32> poison, i32 1, i32 0
1847  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
1848  %vc = icmp ult <vscale x 8 x i32> %va, %splat
1849  ret <vscale x 8 x i1> %vc
1850}
1851
1852define <vscale x 8 x i1> @icmp_ult_vi_nxv8i32_4(<vscale x 8 x i32> %va) {
1853; CHECK-LABEL: icmp_ult_vi_nxv8i32_4:
1854; CHECK:       # %bb.0:
1855; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
1856; CHECK-NEXT:    vmsleu.vi v0, v8, 15
1857; CHECK-NEXT:    ret
1858  %head = insertelement <vscale x 8 x i32> poison, i32 16, i32 0
1859  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
1860  %vc = icmp ult <vscale x 8 x i32> %va, %splat
1861  ret <vscale x 8 x i1> %vc
1862}
1863
1864define <vscale x 8 x i1> @icmp_ule_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
1865; CHECK-LABEL: icmp_ule_vv_nxv8i32:
1866; CHECK:       # %bb.0:
1867; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
1868; CHECK-NEXT:    vmsleu.vv v0, v8, v12
1869; CHECK-NEXT:    ret
1870  %vc = icmp ule <vscale x 8 x i32> %va, %vb
1871  ret <vscale x 8 x i1> %vc
1872}
1873
1874define <vscale x 8 x i1> @icmp_ule_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
1875; CHECK-LABEL: icmp_ule_vx_nxv8i32:
1876; CHECK:       # %bb.0:
1877; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
1878; CHECK-NEXT:    vmsleu.vx v0, v8, a0
1879; CHECK-NEXT:    ret
1880  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
1881  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
1882  %vc = icmp ule <vscale x 8 x i32> %va, %splat
1883  ret <vscale x 8 x i1> %vc
1884}
1885
1886define <vscale x 8 x i1> @icmp_ule_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
1887; CHECK-LABEL: icmp_ule_xv_nxv8i32:
1888; CHECK:       # %bb.0:
1889; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
1890; CHECK-NEXT:    vmv.v.x v12, a0
1891; CHECK-NEXT:    vmsleu.vv v0, v12, v8
1892; CHECK-NEXT:    ret
1893  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
1894  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
1895  %vc = icmp ule <vscale x 8 x i32> %splat, %va
1896  ret <vscale x 8 x i1> %vc
1897}
1898
1899define <vscale x 8 x i1> @icmp_ule_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
1900; CHECK-LABEL: icmp_ule_vi_nxv8i32_0:
1901; CHECK:       # %bb.0:
1902; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
1903; CHECK-NEXT:    vmsleu.vi v0, v8, 5
1904; CHECK-NEXT:    ret
1905  %head = insertelement <vscale x 8 x i32> poison, i32 5, i32 0
1906  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
1907  %vc = icmp ule <vscale x 8 x i32> %va, %splat
1908  ret <vscale x 8 x i1> %vc
1909}
1910
1911define <vscale x 8 x i1> @icmp_sgt_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
1912; CHECK-LABEL: icmp_sgt_vv_nxv8i32:
1913; CHECK:       # %bb.0:
1914; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
1915; CHECK-NEXT:    vmslt.vv v0, v12, v8
1916; CHECK-NEXT:    ret
1917  %vc = icmp sgt <vscale x 8 x i32> %va, %vb
1918  ret <vscale x 8 x i1> %vc
1919}
1920
1921define <vscale x 8 x i1> @icmp_sgt_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
1922; CHECK-LABEL: icmp_sgt_vx_nxv8i32:
1923; CHECK:       # %bb.0:
1924; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
1925; CHECK-NEXT:    vmsgt.vx v0, v8, a0
1926; CHECK-NEXT:    ret
1927  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
1928  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
1929  %vc = icmp sgt <vscale x 8 x i32> %va, %splat
1930  ret <vscale x 8 x i1> %vc
1931}
1932
1933define <vscale x 8 x i1> @icmp_sgt_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
1934; CHECK-LABEL: icmp_sgt_xv_nxv8i32:
1935; CHECK:       # %bb.0:
1936; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
1937; CHECK-NEXT:    vmslt.vx v0, v8, a0
1938; CHECK-NEXT:    ret
1939  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
1940  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
1941  %vc = icmp sgt <vscale x 8 x i32> %splat, %va
1942  ret <vscale x 8 x i1> %vc
1943}
1944
1945define <vscale x 8 x i1> @icmp_sgt_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
1946; CHECK-LABEL: icmp_sgt_vi_nxv8i32_0:
1947; CHECK:       # %bb.0:
1948; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
1949; CHECK-NEXT:    vmsgt.vi v0, v8, 5
1950; CHECK-NEXT:    ret
1951  %head = insertelement <vscale x 8 x i32> poison, i32 5, i32 0
1952  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
1953  %vc = icmp sgt <vscale x 8 x i32> %va, %splat
1954  ret <vscale x 8 x i1> %vc
1955}
1956
1957define <vscale x 8 x i1> @icmp_sge_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
1958; CHECK-LABEL: icmp_sge_vv_nxv8i32:
1959; CHECK:       # %bb.0:
1960; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
1961; CHECK-NEXT:    vmsle.vv v0, v12, v8
1962; CHECK-NEXT:    ret
1963  %vc = icmp sge <vscale x 8 x i32> %va, %vb
1964  ret <vscale x 8 x i1> %vc
1965}
1966
1967define <vscale x 8 x i1> @icmp_sge_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
1968; CHECK-LABEL: icmp_sge_vx_nxv8i32:
1969; CHECK:       # %bb.0:
1970; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
1971; CHECK-NEXT:    vmv.v.x v12, a0
1972; CHECK-NEXT:    vmsle.vv v0, v12, v8
1973; CHECK-NEXT:    ret
1974  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
1975  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
1976  %vc = icmp sge <vscale x 8 x i32> %va, %splat
1977  ret <vscale x 8 x i1> %vc
1978}
1979
1980define <vscale x 8 x i1> @icmp_sge_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
1981; CHECK-LABEL: icmp_sge_xv_nxv8i32:
1982; CHECK:       # %bb.0:
1983; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
1984; CHECK-NEXT:    vmsle.vx v0, v8, a0
1985; CHECK-NEXT:    ret
1986  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
1987  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
1988  %vc = icmp sge <vscale x 8 x i32> %splat, %va
1989  ret <vscale x 8 x i1> %vc
1990}
1991
1992define <vscale x 8 x i1> @icmp_sge_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
1993; CHECK-LABEL: icmp_sge_vi_nxv8i32_0:
1994; CHECK:       # %bb.0:
1995; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
1996; CHECK-NEXT:    vmv.v.i v12, -16
1997; CHECK-NEXT:    vmsle.vv v0, v12, v8
1998; CHECK-NEXT:    ret
1999  %head = insertelement <vscale x 8 x i32> poison, i32 -16, i32 0
2000  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
2001  %vc = icmp sge <vscale x 8 x i32> %va, %splat
2002  ret <vscale x 8 x i1> %vc
2003}
2004
2005define <vscale x 8 x i1> @icmp_sge_vi_nxv8i32_1(<vscale x 8 x i32> %va) {
2006; CHECK-LABEL: icmp_sge_vi_nxv8i32_1:
2007; CHECK:       # %bb.0:
2008; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
2009; CHECK-NEXT:    vmsgt.vi v0, v8, -16
2010; CHECK-NEXT:    ret
2011  %head = insertelement <vscale x 8 x i32> poison, i32 -15, i32 0
2012  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
2013  %vc = icmp sge <vscale x 8 x i32> %va, %splat
2014  ret <vscale x 8 x i1> %vc
2015}
2016
2017define <vscale x 8 x i1> @icmp_sge_iv_nxv8i32_1(<vscale x 8 x i32> %va) {
2018; CHECK-LABEL: icmp_sge_iv_nxv8i32_1:
2019; CHECK:       # %bb.0:
2020; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
2021; CHECK-NEXT:    vmsle.vi v0, v8, -15
2022; CHECK-NEXT:    ret
2023  %head = insertelement <vscale x 8 x i32> poison, i32 -15, i32 0
2024  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
2025  %vc = icmp sge <vscale x 8 x i32> %splat, %va
2026  ret <vscale x 8 x i1> %vc
2027}
2028
2029define <vscale x 8 x i1> @icmp_sge_vi_nxv8i32_2(<vscale x 8 x i32> %va) {
2030; CHECK-LABEL: icmp_sge_vi_nxv8i32_2:
2031; CHECK:       # %bb.0:
2032; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
2033; CHECK-NEXT:    vmsgt.vi v0, v8, -1
2034; CHECK-NEXT:    ret
2035  %head = insertelement <vscale x 8 x i32> poison, i32 0, i32 0
2036  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
2037  %vc = icmp sge <vscale x 8 x i32> %va, %splat
2038  ret <vscale x 8 x i1> %vc
2039}
2040
2041define <vscale x 8 x i1> @icmp_sge_vi_nxv8i32_3(<vscale x 8 x i32> %va) {
2042; CHECK-LABEL: icmp_sge_vi_nxv8i32_3:
2043; CHECK:       # %bb.0:
2044; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
2045; CHECK-NEXT:    vmsgt.vi v0, v8, 15
2046; CHECK-NEXT:    ret
2047  %head = insertelement <vscale x 8 x i32> poison, i32 16, i32 0
2048  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
2049  %vc = icmp sge <vscale x 8 x i32> %va, %splat
2050  ret <vscale x 8 x i1> %vc
2051}
2052
2053define <vscale x 8 x i1> @icmp_slt_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
2054; CHECK-LABEL: icmp_slt_vv_nxv8i32:
2055; CHECK:       # %bb.0:
2056; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
2057; CHECK-NEXT:    vmslt.vv v0, v8, v12
2058; CHECK-NEXT:    ret
2059  %vc = icmp slt <vscale x 8 x i32> %va, %vb
2060  ret <vscale x 8 x i1> %vc
2061}
2062
2063define <vscale x 8 x i1> @icmp_slt_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
2064; CHECK-LABEL: icmp_slt_vx_nxv8i32:
2065; CHECK:       # %bb.0:
2066; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
2067; CHECK-NEXT:    vmslt.vx v0, v8, a0
2068; CHECK-NEXT:    ret
2069  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
2070  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
2071  %vc = icmp slt <vscale x 8 x i32> %va, %splat
2072  ret <vscale x 8 x i1> %vc
2073}
2074
2075define <vscale x 8 x i1> @icmp_slt_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
2076; CHECK-LABEL: icmp_slt_xv_nxv8i32:
2077; CHECK:       # %bb.0:
2078; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
2079; CHECK-NEXT:    vmsgt.vx v0, v8, a0
2080; CHECK-NEXT:    ret
2081  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
2082  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
2083  %vc = icmp slt <vscale x 8 x i32> %splat, %va
2084  ret <vscale x 8 x i1> %vc
2085}
2086
2087define <vscale x 8 x i1> @icmp_slt_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
2088; CHECK-LABEL: icmp_slt_vi_nxv8i32_0:
2089; CHECK:       # %bb.0:
2090; CHECK-NEXT:    li a0, -16
2091; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
2092; CHECK-NEXT:    vmslt.vx v0, v8, a0
2093; CHECK-NEXT:    ret
2094  %head = insertelement <vscale x 8 x i32> poison, i32 -16, i32 0
2095  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
2096  %vc = icmp slt <vscale x 8 x i32> %va, %splat
2097  ret <vscale x 8 x i1> %vc
2098}
2099
2100define <vscale x 8 x i1> @icmp_slt_vi_nxv8i32_1(<vscale x 8 x i32> %va) {
2101; CHECK-LABEL: icmp_slt_vi_nxv8i32_1:
2102; CHECK:       # %bb.0:
2103; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
2104; CHECK-NEXT:    vmsle.vi v0, v8, -16
2105; CHECK-NEXT:    ret
2106  %head = insertelement <vscale x 8 x i32> poison, i32 -15, i32 0
2107  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
2108  %vc = icmp slt <vscale x 8 x i32> %va, %splat
2109  ret <vscale x 8 x i1> %vc
2110}
2111
2112define <vscale x 8 x i1> @icmp_slt_iv_nxv8i32_1(<vscale x 8 x i32> %va) {
2113; CHECK-LABEL: icmp_slt_iv_nxv8i32_1:
2114; CHECK:       # %bb.0:
2115; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
2116; CHECK-NEXT:    vmsgt.vi v0, v8, -15
2117; CHECK-NEXT:    ret
2118  %head = insertelement <vscale x 8 x i32> poison, i32 -15, i32 0
2119  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
2120  %vc = icmp slt <vscale x 8 x i32> %splat, %va
2121  ret <vscale x 8 x i1> %vc
2122}
2123
2124define <vscale x 8 x i1> @icmp_slt_vi_nxv8i32_2(<vscale x 8 x i32> %va) {
2125; CHECK-LABEL: icmp_slt_vi_nxv8i32_2:
2126; CHECK:       # %bb.0:
2127; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
2128; CHECK-NEXT:    vmslt.vx v0, v8, zero
2129; CHECK-NEXT:    ret
2130  %head = insertelement <vscale x 8 x i32> poison, i32 0, i32 0
2131  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
2132  %vc = icmp slt <vscale x 8 x i32> %va, %splat
2133  ret <vscale x 8 x i1> %vc
2134}
2135
2136define <vscale x 8 x i1> @icmp_slt_vi_nxv8i32_3(<vscale x 8 x i32> %va) {
2137; CHECK-LABEL: icmp_slt_vi_nxv8i32_3:
2138; CHECK:       # %bb.0:
2139; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
2140; CHECK-NEXT:    vmsle.vi v0, v8, 15
2141; CHECK-NEXT:    ret
2142  %head = insertelement <vscale x 8 x i32> poison, i32 16, i32 0
2143  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
2144  %vc = icmp slt <vscale x 8 x i32> %va, %splat
2145  ret <vscale x 8 x i1> %vc
2146}
2147
2148define <vscale x 8 x i1> @icmp_sle_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) {
2149; CHECK-LABEL: icmp_sle_vv_nxv8i32:
2150; CHECK:       # %bb.0:
2151; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
2152; CHECK-NEXT:    vmsle.vv v0, v8, v12
2153; CHECK-NEXT:    ret
2154  %vc = icmp sle <vscale x 8 x i32> %va, %vb
2155  ret <vscale x 8 x i1> %vc
2156}
2157
2158define <vscale x 8 x i1> @icmp_sle_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
2159; CHECK-LABEL: icmp_sle_vx_nxv8i32:
2160; CHECK:       # %bb.0:
2161; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
2162; CHECK-NEXT:    vmsle.vx v0, v8, a0
2163; CHECK-NEXT:    ret
2164  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
2165  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
2166  %vc = icmp sle <vscale x 8 x i32> %va, %splat
2167  ret <vscale x 8 x i1> %vc
2168}
2169
2170define <vscale x 8 x i1> @icmp_sle_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) {
2171; CHECK-LABEL: icmp_sle_xv_nxv8i32:
2172; CHECK:       # %bb.0:
2173; CHECK-NEXT:    vsetvli a1, zero, e32, m4, ta, mu
2174; CHECK-NEXT:    vmv.v.x v12, a0
2175; CHECK-NEXT:    vmsle.vv v0, v12, v8
2176; CHECK-NEXT:    ret
2177  %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0
2178  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
2179  %vc = icmp sle <vscale x 8 x i32> %splat, %va
2180  ret <vscale x 8 x i1> %vc
2181}
2182
2183define <vscale x 8 x i1> @icmp_sle_vi_nxv8i32_0(<vscale x 8 x i32> %va) {
2184; CHECK-LABEL: icmp_sle_vi_nxv8i32_0:
2185; CHECK:       # %bb.0:
2186; CHECK-NEXT:    vsetvli a0, zero, e32, m4, ta, mu
2187; CHECK-NEXT:    vmsle.vi v0, v8, 5
2188; CHECK-NEXT:    ret
2189  %head = insertelement <vscale x 8 x i32> poison, i32 5, i32 0
2190  %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer
2191  %vc = icmp sle <vscale x 8 x i32> %va, %splat
2192  ret <vscale x 8 x i1> %vc
2193}
2194
2195define <vscale x 8 x i1> @icmp_eq_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
2196; CHECK-LABEL: icmp_eq_vv_nxv8i64:
2197; CHECK:       # %bb.0:
2198; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
2199; CHECK-NEXT:    vmseq.vv v0, v8, v16
2200; CHECK-NEXT:    ret
2201  %vc = icmp eq <vscale x 8 x i64> %va, %vb
2202  ret <vscale x 8 x i1> %vc
2203}
2204
2205define <vscale x 8 x i1> @icmp_eq_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
2206; RV32-LABEL: icmp_eq_vx_nxv8i64:
2207; RV32:       # %bb.0:
2208; RV32-NEXT:    addi sp, sp, -16
2209; RV32-NEXT:    .cfi_def_cfa_offset 16
2210; RV32-NEXT:    sw a1, 12(sp)
2211; RV32-NEXT:    sw a0, 8(sp)
2212; RV32-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
2213; RV32-NEXT:    addi a0, sp, 8
2214; RV32-NEXT:    vlse64.v v16, (a0), zero
2215; RV32-NEXT:    vmseq.vv v0, v8, v16
2216; RV32-NEXT:    addi sp, sp, 16
2217; RV32-NEXT:    ret
2218;
2219; RV64-LABEL: icmp_eq_vx_nxv8i64:
2220; RV64:       # %bb.0:
2221; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
2222; RV64-NEXT:    vmseq.vx v0, v8, a0
2223; RV64-NEXT:    ret
2224  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
2225  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
2226  %vc = icmp eq <vscale x 8 x i64> %va, %splat
2227  ret <vscale x 8 x i1> %vc
2228}
2229
2230define <vscale x 8 x i1> @icmp_eq_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
2231; RV32-LABEL: icmp_eq_xv_nxv8i64:
2232; RV32:       # %bb.0:
2233; RV32-NEXT:    addi sp, sp, -16
2234; RV32-NEXT:    .cfi_def_cfa_offset 16
2235; RV32-NEXT:    sw a1, 12(sp)
2236; RV32-NEXT:    sw a0, 8(sp)
2237; RV32-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
2238; RV32-NEXT:    addi a0, sp, 8
2239; RV32-NEXT:    vlse64.v v16, (a0), zero
2240; RV32-NEXT:    vmseq.vv v0, v16, v8
2241; RV32-NEXT:    addi sp, sp, 16
2242; RV32-NEXT:    ret
2243;
2244; RV64-LABEL: icmp_eq_xv_nxv8i64:
2245; RV64:       # %bb.0:
2246; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
2247; RV64-NEXT:    vmseq.vx v0, v8, a0
2248; RV64-NEXT:    ret
2249  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
2250  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
2251  %vc = icmp eq <vscale x 8 x i64> %splat, %va
2252  ret <vscale x 8 x i1> %vc
2253}
2254
2255define <vscale x 8 x i1> @icmp_eq_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
2256; CHECK-LABEL: icmp_eq_vi_nxv8i64_0:
2257; CHECK:       # %bb.0:
2258; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
2259; CHECK-NEXT:    vmseq.vi v0, v8, 0
2260; CHECK-NEXT:    ret
2261  %head = insertelement <vscale x 8 x i64> poison, i64 0, i32 0
2262  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
2263  %vc = icmp eq <vscale x 8 x i64> %va, %splat
2264  ret <vscale x 8 x i1> %vc
2265}
2266
2267define <vscale x 8 x i1> @icmp_eq_vi_nxv8i64_1(<vscale x 8 x i64> %va) {
2268; CHECK-LABEL: icmp_eq_vi_nxv8i64_1:
2269; CHECK:       # %bb.0:
2270; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
2271; CHECK-NEXT:    vmseq.vi v0, v8, 5
2272; CHECK-NEXT:    ret
2273  %head = insertelement <vscale x 8 x i64> poison, i64 5, i32 0
2274  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
2275  %vc = icmp eq <vscale x 8 x i64> %va, %splat
2276  ret <vscale x 8 x i1> %vc
2277}
2278
2279define <vscale x 8 x i1> @icmp_eq_iv_nxv8i64_1(<vscale x 8 x i64> %va) {
2280; CHECK-LABEL: icmp_eq_iv_nxv8i64_1:
2281; CHECK:       # %bb.0:
2282; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
2283; CHECK-NEXT:    vmseq.vi v0, v8, 5
2284; CHECK-NEXT:    ret
2285  %head = insertelement <vscale x 8 x i64> poison, i64 5, i32 0
2286  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
2287  %vc = icmp eq <vscale x 8 x i64> %splat, %va
2288  ret <vscale x 8 x i1> %vc
2289}
2290
2291define <vscale x 8 x i1> @icmp_ne_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
2292; CHECK-LABEL: icmp_ne_vv_nxv8i64:
2293; CHECK:       # %bb.0:
2294; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
2295; CHECK-NEXT:    vmsne.vv v0, v8, v16
2296; CHECK-NEXT:    ret
2297  %vc = icmp ne <vscale x 8 x i64> %va, %vb
2298  ret <vscale x 8 x i1> %vc
2299}
2300
2301define <vscale x 8 x i1> @icmp_ne_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
2302; RV32-LABEL: icmp_ne_vx_nxv8i64:
2303; RV32:       # %bb.0:
2304; RV32-NEXT:    addi sp, sp, -16
2305; RV32-NEXT:    .cfi_def_cfa_offset 16
2306; RV32-NEXT:    sw a1, 12(sp)
2307; RV32-NEXT:    sw a0, 8(sp)
2308; RV32-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
2309; RV32-NEXT:    addi a0, sp, 8
2310; RV32-NEXT:    vlse64.v v16, (a0), zero
2311; RV32-NEXT:    vmsne.vv v0, v8, v16
2312; RV32-NEXT:    addi sp, sp, 16
2313; RV32-NEXT:    ret
2314;
2315; RV64-LABEL: icmp_ne_vx_nxv8i64:
2316; RV64:       # %bb.0:
2317; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
2318; RV64-NEXT:    vmsne.vx v0, v8, a0
2319; RV64-NEXT:    ret
2320  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
2321  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
2322  %vc = icmp ne <vscale x 8 x i64> %va, %splat
2323  ret <vscale x 8 x i1> %vc
2324}
2325
2326define <vscale x 8 x i1> @icmp_ne_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
2327; RV32-LABEL: icmp_ne_xv_nxv8i64:
2328; RV32:       # %bb.0:
2329; RV32-NEXT:    addi sp, sp, -16
2330; RV32-NEXT:    .cfi_def_cfa_offset 16
2331; RV32-NEXT:    sw a1, 12(sp)
2332; RV32-NEXT:    sw a0, 8(sp)
2333; RV32-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
2334; RV32-NEXT:    addi a0, sp, 8
2335; RV32-NEXT:    vlse64.v v16, (a0), zero
2336; RV32-NEXT:    vmsne.vv v0, v16, v8
2337; RV32-NEXT:    addi sp, sp, 16
2338; RV32-NEXT:    ret
2339;
2340; RV64-LABEL: icmp_ne_xv_nxv8i64:
2341; RV64:       # %bb.0:
2342; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
2343; RV64-NEXT:    vmsne.vx v0, v8, a0
2344; RV64-NEXT:    ret
2345  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
2346  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
2347  %vc = icmp ne <vscale x 8 x i64> %splat, %va
2348  ret <vscale x 8 x i1> %vc
2349}
2350
2351define <vscale x 8 x i1> @icmp_ne_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
2352; CHECK-LABEL: icmp_ne_vi_nxv8i64_0:
2353; CHECK:       # %bb.0:
2354; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
2355; CHECK-NEXT:    vmsne.vi v0, v8, 5
2356; CHECK-NEXT:    ret
2357  %head = insertelement <vscale x 8 x i64> poison, i64 5, i32 0
2358  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
2359  %vc = icmp ne <vscale x 8 x i64> %va, %splat
2360  ret <vscale x 8 x i1> %vc
2361}
2362
2363define <vscale x 8 x i1> @icmp_ugt_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
2364; CHECK-LABEL: icmp_ugt_vv_nxv8i64:
2365; CHECK:       # %bb.0:
2366; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
2367; CHECK-NEXT:    vmsltu.vv v0, v16, v8
2368; CHECK-NEXT:    ret
2369  %vc = icmp ugt <vscale x 8 x i64> %va, %vb
2370  ret <vscale x 8 x i1> %vc
2371}
2372
2373define <vscale x 8 x i1> @icmp_ugt_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
2374; RV32-LABEL: icmp_ugt_vx_nxv8i64:
2375; RV32:       # %bb.0:
2376; RV32-NEXT:    addi sp, sp, -16
2377; RV32-NEXT:    .cfi_def_cfa_offset 16
2378; RV32-NEXT:    sw a1, 12(sp)
2379; RV32-NEXT:    sw a0, 8(sp)
2380; RV32-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
2381; RV32-NEXT:    addi a0, sp, 8
2382; RV32-NEXT:    vlse64.v v16, (a0), zero
2383; RV32-NEXT:    vmsltu.vv v0, v16, v8
2384; RV32-NEXT:    addi sp, sp, 16
2385; RV32-NEXT:    ret
2386;
2387; RV64-LABEL: icmp_ugt_vx_nxv8i64:
2388; RV64:       # %bb.0:
2389; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
2390; RV64-NEXT:    vmsgtu.vx v0, v8, a0
2391; RV64-NEXT:    ret
2392  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
2393  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
2394  %vc = icmp ugt <vscale x 8 x i64> %va, %splat
2395  ret <vscale x 8 x i1> %vc
2396}
2397
2398define <vscale x 8 x i1> @icmp_ugt_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
2399; RV32-LABEL: icmp_ugt_xv_nxv8i64:
2400; RV32:       # %bb.0:
2401; RV32-NEXT:    addi sp, sp, -16
2402; RV32-NEXT:    .cfi_def_cfa_offset 16
2403; RV32-NEXT:    sw a1, 12(sp)
2404; RV32-NEXT:    sw a0, 8(sp)
2405; RV32-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
2406; RV32-NEXT:    addi a0, sp, 8
2407; RV32-NEXT:    vlse64.v v16, (a0), zero
2408; RV32-NEXT:    vmsltu.vv v0, v8, v16
2409; RV32-NEXT:    addi sp, sp, 16
2410; RV32-NEXT:    ret
2411;
2412; RV64-LABEL: icmp_ugt_xv_nxv8i64:
2413; RV64:       # %bb.0:
2414; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
2415; RV64-NEXT:    vmsltu.vx v0, v8, a0
2416; RV64-NEXT:    ret
2417  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
2418  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
2419  %vc = icmp ugt <vscale x 8 x i64> %splat, %va
2420  ret <vscale x 8 x i1> %vc
2421}
2422
2423define <vscale x 8 x i1> @icmp_ugt_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
2424; CHECK-LABEL: icmp_ugt_vi_nxv8i64_0:
2425; CHECK:       # %bb.0:
2426; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
2427; CHECK-NEXT:    vmsgtu.vi v0, v8, 5
2428; CHECK-NEXT:    ret
2429  %head = insertelement <vscale x 8 x i64> poison, i64 5, i32 0
2430  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
2431  %vc = icmp ugt <vscale x 8 x i64> %va, %splat
2432  ret <vscale x 8 x i1> %vc
2433}
2434
2435define <vscale x 8 x i1> @icmp_uge_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
2436; CHECK-LABEL: icmp_uge_vv_nxv8i64:
2437; CHECK:       # %bb.0:
2438; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
2439; CHECK-NEXT:    vmsleu.vv v0, v16, v8
2440; CHECK-NEXT:    ret
2441  %vc = icmp uge <vscale x 8 x i64> %va, %vb
2442  ret <vscale x 8 x i1> %vc
2443}
2444
2445define <vscale x 8 x i1> @icmp_uge_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
2446; RV32-LABEL: icmp_uge_vx_nxv8i64:
2447; RV32:       # %bb.0:
2448; RV32-NEXT:    addi sp, sp, -16
2449; RV32-NEXT:    .cfi_def_cfa_offset 16
2450; RV32-NEXT:    sw a1, 12(sp)
2451; RV32-NEXT:    sw a0, 8(sp)
2452; RV32-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
2453; RV32-NEXT:    addi a0, sp, 8
2454; RV32-NEXT:    vlse64.v v16, (a0), zero
2455; RV32-NEXT:    vmsleu.vv v0, v16, v8
2456; RV32-NEXT:    addi sp, sp, 16
2457; RV32-NEXT:    ret
2458;
2459; RV64-LABEL: icmp_uge_vx_nxv8i64:
2460; RV64:       # %bb.0:
2461; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
2462; RV64-NEXT:    vmv.v.x v16, a0
2463; RV64-NEXT:    vmsleu.vv v0, v16, v8
2464; RV64-NEXT:    ret
2465  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
2466  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
2467  %vc = icmp uge <vscale x 8 x i64> %va, %splat
2468  ret <vscale x 8 x i1> %vc
2469}
2470
2471define <vscale x 8 x i1> @icmp_uge_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
2472; RV32-LABEL: icmp_uge_xv_nxv8i64:
2473; RV32:       # %bb.0:
2474; RV32-NEXT:    addi sp, sp, -16
2475; RV32-NEXT:    .cfi_def_cfa_offset 16
2476; RV32-NEXT:    sw a1, 12(sp)
2477; RV32-NEXT:    sw a0, 8(sp)
2478; RV32-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
2479; RV32-NEXT:    addi a0, sp, 8
2480; RV32-NEXT:    vlse64.v v16, (a0), zero
2481; RV32-NEXT:    vmsleu.vv v0, v8, v16
2482; RV32-NEXT:    addi sp, sp, 16
2483; RV32-NEXT:    ret
2484;
2485; RV64-LABEL: icmp_uge_xv_nxv8i64:
2486; RV64:       # %bb.0:
2487; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
2488; RV64-NEXT:    vmsleu.vx v0, v8, a0
2489; RV64-NEXT:    ret
2490  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
2491  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
2492  %vc = icmp uge <vscale x 8 x i64> %splat, %va
2493  ret <vscale x 8 x i1> %vc
2494}
2495
2496define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
2497; CHECK-LABEL: icmp_uge_vi_nxv8i64_0:
2498; CHECK:       # %bb.0:
2499; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
2500; CHECK-NEXT:    vmv.v.i v16, -16
2501; CHECK-NEXT:    vmsleu.vv v0, v16, v8
2502; CHECK-NEXT:    ret
2503  %head = insertelement <vscale x 8 x i64> poison, i64 -16, i32 0
2504  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
2505  %vc = icmp uge <vscale x 8 x i64> %va, %splat
2506  ret <vscale x 8 x i1> %vc
2507}
2508
2509define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_1(<vscale x 8 x i64> %va) {
2510; CHECK-LABEL: icmp_uge_vi_nxv8i64_1:
2511; CHECK:       # %bb.0:
2512; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
2513; CHECK-NEXT:    vmsgtu.vi v0, v8, 14
2514; CHECK-NEXT:    ret
2515  %head = insertelement <vscale x 8 x i64> poison, i64 15, i32 0
2516  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
2517  %vc = icmp uge <vscale x 8 x i64> %va, %splat
2518  ret <vscale x 8 x i1> %vc
2519}
2520
2521define <vscale x 8 x i1> @icmp_uge_iv_nxv8i64_1(<vscale x 8 x i64> %va) {
2522; CHECK-LABEL: icmp_uge_iv_nxv8i64_1:
2523; CHECK:       # %bb.0:
2524; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
2525; CHECK-NEXT:    vmsleu.vi v0, v8, 15
2526; CHECK-NEXT:    ret
2527  %head = insertelement <vscale x 8 x i64> poison, i64 15, i32 0
2528  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
2529  %vc = icmp uge <vscale x 8 x i64> %splat, %va
2530  ret <vscale x 8 x i1> %vc
2531}
2532
2533define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_2(<vscale x 8 x i64> %va) {
2534; CHECK-LABEL: icmp_uge_vi_nxv8i64_2:
2535; CHECK:       # %bb.0:
2536; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
2537; CHECK-NEXT:    vmset.m v0
2538; CHECK-NEXT:    ret
2539  %head = insertelement <vscale x 8 x i64> poison, i64 0, i32 0
2540  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
2541  %vc = icmp uge <vscale x 8 x i64> %va, %splat
2542  ret <vscale x 8 x i1> %vc
2543}
2544
2545define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_3(<vscale x 8 x i64> %va) {
2546; CHECK-LABEL: icmp_uge_vi_nxv8i64_3:
2547; CHECK:       # %bb.0:
2548; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
2549; CHECK-NEXT:    vmsgtu.vi v0, v8, 0
2550; CHECK-NEXT:    ret
2551  %head = insertelement <vscale x 8 x i64> poison, i64 1, i32 0
2552  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
2553  %vc = icmp uge <vscale x 8 x i64> %va, %splat
2554  ret <vscale x 8 x i1> %vc
2555}
2556
2557define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_4(<vscale x 8 x i64> %va) {
2558; CHECK-LABEL: icmp_uge_vi_nxv8i64_4:
2559; CHECK:       # %bb.0:
2560; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
2561; CHECK-NEXT:    vmsgtu.vi v0, v8, -16
2562; CHECK-NEXT:    ret
2563  %head = insertelement <vscale x 8 x i64> poison, i64 -15, i32 0
2564  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
2565  %vc = icmp uge <vscale x 8 x i64> %va, %splat
2566  ret <vscale x 8 x i1> %vc
2567}
2568
2569define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_5(<vscale x 8 x i64> %va) {
2570; CHECK-LABEL: icmp_uge_vi_nxv8i64_5:
2571; CHECK:       # %bb.0:
2572; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
2573; CHECK-NEXT:    vmsgtu.vi v0, v8, 15
2574; CHECK-NEXT:    ret
2575  %head = insertelement <vscale x 8 x i64> poison, i64 16, i32 0
2576  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
2577  %vc = icmp uge <vscale x 8 x i64> %va, %splat
2578  ret <vscale x 8 x i1> %vc
2579}
2580
2581define <vscale x 8 x i1> @icmp_ult_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
2582; CHECK-LABEL: icmp_ult_vv_nxv8i64:
2583; CHECK:       # %bb.0:
2584; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
2585; CHECK-NEXT:    vmsltu.vv v0, v8, v16
2586; CHECK-NEXT:    ret
2587  %vc = icmp ult <vscale x 8 x i64> %va, %vb
2588  ret <vscale x 8 x i1> %vc
2589}
2590
2591define <vscale x 8 x i1> @icmp_ult_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
2592; RV32-LABEL: icmp_ult_vx_nxv8i64:
2593; RV32:       # %bb.0:
2594; RV32-NEXT:    addi sp, sp, -16
2595; RV32-NEXT:    .cfi_def_cfa_offset 16
2596; RV32-NEXT:    sw a1, 12(sp)
2597; RV32-NEXT:    sw a0, 8(sp)
2598; RV32-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
2599; RV32-NEXT:    addi a0, sp, 8
2600; RV32-NEXT:    vlse64.v v16, (a0), zero
2601; RV32-NEXT:    vmsltu.vv v0, v8, v16
2602; RV32-NEXT:    addi sp, sp, 16
2603; RV32-NEXT:    ret
2604;
2605; RV64-LABEL: icmp_ult_vx_nxv8i64:
2606; RV64:       # %bb.0:
2607; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
2608; RV64-NEXT:    vmsltu.vx v0, v8, a0
2609; RV64-NEXT:    ret
2610  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
2611  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
2612  %vc = icmp ult <vscale x 8 x i64> %va, %splat
2613  ret <vscale x 8 x i1> %vc
2614}
2615
2616define <vscale x 8 x i1> @icmp_ult_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
2617; RV32-LABEL: icmp_ult_xv_nxv8i64:
2618; RV32:       # %bb.0:
2619; RV32-NEXT:    addi sp, sp, -16
2620; RV32-NEXT:    .cfi_def_cfa_offset 16
2621; RV32-NEXT:    sw a1, 12(sp)
2622; RV32-NEXT:    sw a0, 8(sp)
2623; RV32-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
2624; RV32-NEXT:    addi a0, sp, 8
2625; RV32-NEXT:    vlse64.v v16, (a0), zero
2626; RV32-NEXT:    vmsltu.vv v0, v16, v8
2627; RV32-NEXT:    addi sp, sp, 16
2628; RV32-NEXT:    ret
2629;
2630; RV64-LABEL: icmp_ult_xv_nxv8i64:
2631; RV64:       # %bb.0:
2632; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
2633; RV64-NEXT:    vmsgtu.vx v0, v8, a0
2634; RV64-NEXT:    ret
2635  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
2636  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
2637  %vc = icmp ult <vscale x 8 x i64> %splat, %va
2638  ret <vscale x 8 x i1> %vc
2639}
2640
2641define <vscale x 8 x i1> @icmp_ult_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
2642; CHECK-LABEL: icmp_ult_vi_nxv8i64_0:
2643; CHECK:       # %bb.0:
2644; CHECK-NEXT:    li a0, -16
2645; CHECK-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
2646; CHECK-NEXT:    vmsltu.vx v0, v8, a0
2647; CHECK-NEXT:    ret
2648  %head = insertelement <vscale x 8 x i64> poison, i64 -16, i32 0
2649  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
2650  %vc = icmp ult <vscale x 8 x i64> %va, %splat
2651  ret <vscale x 8 x i1> %vc
2652}
2653
2654define <vscale x 8 x i1> @icmp_ult_vi_nxv8i64_1(<vscale x 8 x i64> %va) {
2655; CHECK-LABEL: icmp_ult_vi_nxv8i64_1:
2656; CHECK:       # %bb.0:
2657; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
2658; CHECK-NEXT:    vmsleu.vi v0, v8, -16
2659; CHECK-NEXT:    ret
2660  %head = insertelement <vscale x 8 x i64> poison, i64 -15, i32 0
2661  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
2662  %vc = icmp ult <vscale x 8 x i64> %va, %splat
2663  ret <vscale x 8 x i1> %vc
2664}
2665
2666define <vscale x 8 x i1> @icmp_ult_iv_nxv8i64_1(<vscale x 8 x i64> %va) {
2667; CHECK-LABEL: icmp_ult_iv_nxv8i64_1:
2668; CHECK:       # %bb.0:
2669; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
2670; CHECK-NEXT:    vmsgtu.vi v0, v8, -15
2671; CHECK-NEXT:    ret
2672  %head = insertelement <vscale x 8 x i64> poison, i64 -15, i32 0
2673  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
2674  %vc = icmp ult <vscale x 8 x i64> %splat, %va
2675  ret <vscale x 8 x i1> %vc
2676}
2677
2678define <vscale x 8 x i1> @icmp_ult_vi_nxv8i64_2(<vscale x 8 x i64> %va) {
2679; CHECK-LABEL: icmp_ult_vi_nxv8i64_2:
2680; CHECK:       # %bb.0:
2681; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
2682; CHECK-NEXT:    vmclr.m v0
2683; CHECK-NEXT:    ret
2684  %head = insertelement <vscale x 8 x i64> poison, i64 0, i32 0
2685  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
2686  %vc = icmp ult <vscale x 8 x i64> %va, %splat
2687  ret <vscale x 8 x i1> %vc
2688}
2689
2690define <vscale x 8 x i1> @icmp_ult_vi_nxv8i64_3(<vscale x 8 x i64> %va) {
2691; CHECK-LABEL: icmp_ult_vi_nxv8i64_3:
2692; CHECK:       # %bb.0:
2693; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
2694; CHECK-NEXT:    vmseq.vi v0, v8, 0
2695; CHECK-NEXT:    ret
2696  %head = insertelement <vscale x 8 x i64> poison, i64 1, i32 0
2697  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
2698  %vc = icmp ult <vscale x 8 x i64> %va, %splat
2699  ret <vscale x 8 x i1> %vc
2700}
2701
2702define <vscale x 8 x i1> @icmp_ult_vi_nxv8i64_4(<vscale x 8 x i64> %va) {
2703; CHECK-LABEL: icmp_ult_vi_nxv8i64_4:
2704; CHECK:       # %bb.0:
2705; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
2706; CHECK-NEXT:    vmsleu.vi v0, v8, 15
2707; CHECK-NEXT:    ret
2708  %head = insertelement <vscale x 8 x i64> poison, i64 16, i32 0
2709  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
2710  %vc = icmp ult <vscale x 8 x i64> %va, %splat
2711  ret <vscale x 8 x i1> %vc
2712}
2713
2714define <vscale x 8 x i1> @icmp_ule_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
2715; CHECK-LABEL: icmp_ule_vv_nxv8i64:
2716; CHECK:       # %bb.0:
2717; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
2718; CHECK-NEXT:    vmsleu.vv v0, v8, v16
2719; CHECK-NEXT:    ret
2720  %vc = icmp ule <vscale x 8 x i64> %va, %vb
2721  ret <vscale x 8 x i1> %vc
2722}
2723
2724define <vscale x 8 x i1> @icmp_ule_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
2725; RV32-LABEL: icmp_ule_vx_nxv8i64:
2726; RV32:       # %bb.0:
2727; RV32-NEXT:    addi sp, sp, -16
2728; RV32-NEXT:    .cfi_def_cfa_offset 16
2729; RV32-NEXT:    sw a1, 12(sp)
2730; RV32-NEXT:    sw a0, 8(sp)
2731; RV32-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
2732; RV32-NEXT:    addi a0, sp, 8
2733; RV32-NEXT:    vlse64.v v16, (a0), zero
2734; RV32-NEXT:    vmsleu.vv v0, v8, v16
2735; RV32-NEXT:    addi sp, sp, 16
2736; RV32-NEXT:    ret
2737;
2738; RV64-LABEL: icmp_ule_vx_nxv8i64:
2739; RV64:       # %bb.0:
2740; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
2741; RV64-NEXT:    vmsleu.vx v0, v8, a0
2742; RV64-NEXT:    ret
2743  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
2744  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
2745  %vc = icmp ule <vscale x 8 x i64> %va, %splat
2746  ret <vscale x 8 x i1> %vc
2747}
2748
2749define <vscale x 8 x i1> @icmp_ule_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
2750; RV32-LABEL: icmp_ule_xv_nxv8i64:
2751; RV32:       # %bb.0:
2752; RV32-NEXT:    addi sp, sp, -16
2753; RV32-NEXT:    .cfi_def_cfa_offset 16
2754; RV32-NEXT:    sw a1, 12(sp)
2755; RV32-NEXT:    sw a0, 8(sp)
2756; RV32-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
2757; RV32-NEXT:    addi a0, sp, 8
2758; RV32-NEXT:    vlse64.v v16, (a0), zero
2759; RV32-NEXT:    vmsleu.vv v0, v16, v8
2760; RV32-NEXT:    addi sp, sp, 16
2761; RV32-NEXT:    ret
2762;
2763; RV64-LABEL: icmp_ule_xv_nxv8i64:
2764; RV64:       # %bb.0:
2765; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
2766; RV64-NEXT:    vmv.v.x v16, a0
2767; RV64-NEXT:    vmsleu.vv v0, v16, v8
2768; RV64-NEXT:    ret
2769  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
2770  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
2771  %vc = icmp ule <vscale x 8 x i64> %splat, %va
2772  ret <vscale x 8 x i1> %vc
2773}
2774
2775define <vscale x 8 x i1> @icmp_ule_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
2776; CHECK-LABEL: icmp_ule_vi_nxv8i64_0:
2777; CHECK:       # %bb.0:
2778; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
2779; CHECK-NEXT:    vmsleu.vi v0, v8, 5
2780; CHECK-NEXT:    ret
2781  %head = insertelement <vscale x 8 x i64> poison, i64 5, i32 0
2782  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
2783  %vc = icmp ule <vscale x 8 x i64> %va, %splat
2784  ret <vscale x 8 x i1> %vc
2785}
2786
2787define <vscale x 8 x i1> @icmp_sgt_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
2788; CHECK-LABEL: icmp_sgt_vv_nxv8i64:
2789; CHECK:       # %bb.0:
2790; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
2791; CHECK-NEXT:    vmslt.vv v0, v16, v8
2792; CHECK-NEXT:    ret
2793  %vc = icmp sgt <vscale x 8 x i64> %va, %vb
2794  ret <vscale x 8 x i1> %vc
2795}
2796
2797define <vscale x 8 x i1> @icmp_sgt_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
2798; RV32-LABEL: icmp_sgt_vx_nxv8i64:
2799; RV32:       # %bb.0:
2800; RV32-NEXT:    addi sp, sp, -16
2801; RV32-NEXT:    .cfi_def_cfa_offset 16
2802; RV32-NEXT:    sw a1, 12(sp)
2803; RV32-NEXT:    sw a0, 8(sp)
2804; RV32-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
2805; RV32-NEXT:    addi a0, sp, 8
2806; RV32-NEXT:    vlse64.v v16, (a0), zero
2807; RV32-NEXT:    vmslt.vv v0, v16, v8
2808; RV32-NEXT:    addi sp, sp, 16
2809; RV32-NEXT:    ret
2810;
2811; RV64-LABEL: icmp_sgt_vx_nxv8i64:
2812; RV64:       # %bb.0:
2813; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
2814; RV64-NEXT:    vmsgt.vx v0, v8, a0
2815; RV64-NEXT:    ret
2816  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
2817  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
2818  %vc = icmp sgt <vscale x 8 x i64> %va, %splat
2819  ret <vscale x 8 x i1> %vc
2820}
2821
2822define <vscale x 8 x i1> @icmp_sgt_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
2823; RV32-LABEL: icmp_sgt_xv_nxv8i64:
2824; RV32:       # %bb.0:
2825; RV32-NEXT:    addi sp, sp, -16
2826; RV32-NEXT:    .cfi_def_cfa_offset 16
2827; RV32-NEXT:    sw a1, 12(sp)
2828; RV32-NEXT:    sw a0, 8(sp)
2829; RV32-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
2830; RV32-NEXT:    addi a0, sp, 8
2831; RV32-NEXT:    vlse64.v v16, (a0), zero
2832; RV32-NEXT:    vmslt.vv v0, v8, v16
2833; RV32-NEXT:    addi sp, sp, 16
2834; RV32-NEXT:    ret
2835;
2836; RV64-LABEL: icmp_sgt_xv_nxv8i64:
2837; RV64:       # %bb.0:
2838; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
2839; RV64-NEXT:    vmslt.vx v0, v8, a0
2840; RV64-NEXT:    ret
2841  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
2842  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
2843  %vc = icmp sgt <vscale x 8 x i64> %splat, %va
2844  ret <vscale x 8 x i1> %vc
2845}
2846
2847define <vscale x 8 x i1> @icmp_sgt_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
2848; CHECK-LABEL: icmp_sgt_vi_nxv8i64_0:
2849; CHECK:       # %bb.0:
2850; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
2851; CHECK-NEXT:    vmsgt.vi v0, v8, 5
2852; CHECK-NEXT:    ret
2853  %head = insertelement <vscale x 8 x i64> poison, i64 5, i32 0
2854  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
2855  %vc = icmp sgt <vscale x 8 x i64> %va, %splat
2856  ret <vscale x 8 x i1> %vc
2857}
2858
2859define <vscale x 8 x i1> @icmp_sge_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
2860; CHECK-LABEL: icmp_sge_vv_nxv8i64:
2861; CHECK:       # %bb.0:
2862; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
2863; CHECK-NEXT:    vmsle.vv v0, v16, v8
2864; CHECK-NEXT:    ret
2865  %vc = icmp sge <vscale x 8 x i64> %va, %vb
2866  ret <vscale x 8 x i1> %vc
2867}
2868
2869define <vscale x 8 x i1> @icmp_sge_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
2870; RV32-LABEL: icmp_sge_vx_nxv8i64:
2871; RV32:       # %bb.0:
2872; RV32-NEXT:    addi sp, sp, -16
2873; RV32-NEXT:    .cfi_def_cfa_offset 16
2874; RV32-NEXT:    sw a1, 12(sp)
2875; RV32-NEXT:    sw a0, 8(sp)
2876; RV32-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
2877; RV32-NEXT:    addi a0, sp, 8
2878; RV32-NEXT:    vlse64.v v16, (a0), zero
2879; RV32-NEXT:    vmsle.vv v0, v16, v8
2880; RV32-NEXT:    addi sp, sp, 16
2881; RV32-NEXT:    ret
2882;
2883; RV64-LABEL: icmp_sge_vx_nxv8i64:
2884; RV64:       # %bb.0:
2885; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
2886; RV64-NEXT:    vmv.v.x v16, a0
2887; RV64-NEXT:    vmsle.vv v0, v16, v8
2888; RV64-NEXT:    ret
2889  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
2890  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
2891  %vc = icmp sge <vscale x 8 x i64> %va, %splat
2892  ret <vscale x 8 x i1> %vc
2893}
2894
2895define <vscale x 8 x i1> @icmp_sge_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
2896; RV32-LABEL: icmp_sge_xv_nxv8i64:
2897; RV32:       # %bb.0:
2898; RV32-NEXT:    addi sp, sp, -16
2899; RV32-NEXT:    .cfi_def_cfa_offset 16
2900; RV32-NEXT:    sw a1, 12(sp)
2901; RV32-NEXT:    sw a0, 8(sp)
2902; RV32-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
2903; RV32-NEXT:    addi a0, sp, 8
2904; RV32-NEXT:    vlse64.v v16, (a0), zero
2905; RV32-NEXT:    vmsle.vv v0, v8, v16
2906; RV32-NEXT:    addi sp, sp, 16
2907; RV32-NEXT:    ret
2908;
2909; RV64-LABEL: icmp_sge_xv_nxv8i64:
2910; RV64:       # %bb.0:
2911; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
2912; RV64-NEXT:    vmsle.vx v0, v8, a0
2913; RV64-NEXT:    ret
2914  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
2915  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
2916  %vc = icmp sge <vscale x 8 x i64> %splat, %va
2917  ret <vscale x 8 x i1> %vc
2918}
2919
2920define <vscale x 8 x i1> @icmp_sge_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
2921; CHECK-LABEL: icmp_sge_vi_nxv8i64_0:
2922; CHECK:       # %bb.0:
2923; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
2924; CHECK-NEXT:    vmv.v.i v16, -16
2925; CHECK-NEXT:    vmsle.vv v0, v16, v8
2926; CHECK-NEXT:    ret
2927  %head = insertelement <vscale x 8 x i64> poison, i64 -16, i32 0
2928  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
2929  %vc = icmp sge <vscale x 8 x i64> %va, %splat
2930  ret <vscale x 8 x i1> %vc
2931}
2932
2933define <vscale x 8 x i1> @icmp_sge_vi_nxv8i64_1(<vscale x 8 x i64> %va) {
2934; CHECK-LABEL: icmp_sge_vi_nxv8i64_1:
2935; CHECK:       # %bb.0:
2936; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
2937; CHECK-NEXT:    vmsgt.vi v0, v8, -16
2938; CHECK-NEXT:    ret
2939  %head = insertelement <vscale x 8 x i64> poison, i64 -15, i32 0
2940  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
2941  %vc = icmp sge <vscale x 8 x i64> %va, %splat
2942  ret <vscale x 8 x i1> %vc
2943}
2944
2945define <vscale x 8 x i1> @icmp_sge_iv_nxv8i64_1(<vscale x 8 x i64> %va) {
2946; CHECK-LABEL: icmp_sge_iv_nxv8i64_1:
2947; CHECK:       # %bb.0:
2948; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
2949; CHECK-NEXT:    vmsle.vi v0, v8, -15
2950; CHECK-NEXT:    ret
2951  %head = insertelement <vscale x 8 x i64> poison, i64 -15, i32 0
2952  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
2953  %vc = icmp sge <vscale x 8 x i64> %splat, %va
2954  ret <vscale x 8 x i1> %vc
2955}
2956
2957define <vscale x 8 x i1> @icmp_sge_vi_nxv8i64_2(<vscale x 8 x i64> %va) {
2958; CHECK-LABEL: icmp_sge_vi_nxv8i64_2:
2959; CHECK:       # %bb.0:
2960; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
2961; CHECK-NEXT:    vmsgt.vi v0, v8, -1
2962; CHECK-NEXT:    ret
2963  %head = insertelement <vscale x 8 x i64> poison, i64 0, i32 0
2964  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
2965  %vc = icmp sge <vscale x 8 x i64> %va, %splat
2966  ret <vscale x 8 x i1> %vc
2967}
2968
2969define <vscale x 8 x i1> @icmp_sge_vi_nxv8i64_3(<vscale x 8 x i64> %va) {
2970; CHECK-LABEL: icmp_sge_vi_nxv8i64_3:
2971; CHECK:       # %bb.0:
2972; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
2973; CHECK-NEXT:    vmsgt.vi v0, v8, 15
2974; CHECK-NEXT:    ret
2975  %head = insertelement <vscale x 8 x i64> poison, i64 16, i32 0
2976  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
2977  %vc = icmp sge <vscale x 8 x i64> %va, %splat
2978  ret <vscale x 8 x i1> %vc
2979}
2980
2981define <vscale x 8 x i1> @icmp_slt_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
2982; CHECK-LABEL: icmp_slt_vv_nxv8i64:
2983; CHECK:       # %bb.0:
2984; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
2985; CHECK-NEXT:    vmslt.vv v0, v8, v16
2986; CHECK-NEXT:    ret
2987  %vc = icmp slt <vscale x 8 x i64> %va, %vb
2988  ret <vscale x 8 x i1> %vc
2989}
2990
2991define <vscale x 8 x i1> @icmp_slt_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
2992; RV32-LABEL: icmp_slt_vx_nxv8i64:
2993; RV32:       # %bb.0:
2994; RV32-NEXT:    addi sp, sp, -16
2995; RV32-NEXT:    .cfi_def_cfa_offset 16
2996; RV32-NEXT:    sw a1, 12(sp)
2997; RV32-NEXT:    sw a0, 8(sp)
2998; RV32-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
2999; RV32-NEXT:    addi a0, sp, 8
3000; RV32-NEXT:    vlse64.v v16, (a0), zero
3001; RV32-NEXT:    vmslt.vv v0, v8, v16
3002; RV32-NEXT:    addi sp, sp, 16
3003; RV32-NEXT:    ret
3004;
3005; RV64-LABEL: icmp_slt_vx_nxv8i64:
3006; RV64:       # %bb.0:
3007; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
3008; RV64-NEXT:    vmslt.vx v0, v8, a0
3009; RV64-NEXT:    ret
3010  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
3011  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
3012  %vc = icmp slt <vscale x 8 x i64> %va, %splat
3013  ret <vscale x 8 x i1> %vc
3014}
3015
3016define <vscale x 8 x i1> @icmp_slt_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
3017; RV32-LABEL: icmp_slt_xv_nxv8i64:
3018; RV32:       # %bb.0:
3019; RV32-NEXT:    addi sp, sp, -16
3020; RV32-NEXT:    .cfi_def_cfa_offset 16
3021; RV32-NEXT:    sw a1, 12(sp)
3022; RV32-NEXT:    sw a0, 8(sp)
3023; RV32-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
3024; RV32-NEXT:    addi a0, sp, 8
3025; RV32-NEXT:    vlse64.v v16, (a0), zero
3026; RV32-NEXT:    vmslt.vv v0, v16, v8
3027; RV32-NEXT:    addi sp, sp, 16
3028; RV32-NEXT:    ret
3029;
3030; RV64-LABEL: icmp_slt_xv_nxv8i64:
3031; RV64:       # %bb.0:
3032; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
3033; RV64-NEXT:    vmsgt.vx v0, v8, a0
3034; RV64-NEXT:    ret
3035  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
3036  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
3037  %vc = icmp slt <vscale x 8 x i64> %splat, %va
3038  ret <vscale x 8 x i1> %vc
3039}
3040
3041define <vscale x 8 x i1> @icmp_slt_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
3042; CHECK-LABEL: icmp_slt_vi_nxv8i64_0:
3043; CHECK:       # %bb.0:
3044; CHECK-NEXT:    li a0, -16
3045; CHECK-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
3046; CHECK-NEXT:    vmslt.vx v0, v8, a0
3047; CHECK-NEXT:    ret
3048  %head = insertelement <vscale x 8 x i64> poison, i64 -16, i32 0
3049  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
3050  %vc = icmp slt <vscale x 8 x i64> %va, %splat
3051  ret <vscale x 8 x i1> %vc
3052}
3053
3054define <vscale x 8 x i1> @icmp_slt_vi_nxv8i64_1(<vscale x 8 x i64> %va) {
3055; CHECK-LABEL: icmp_slt_vi_nxv8i64_1:
3056; CHECK:       # %bb.0:
3057; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
3058; CHECK-NEXT:    vmsle.vi v0, v8, -16
3059; CHECK-NEXT:    ret
3060  %head = insertelement <vscale x 8 x i64> poison, i64 -15, i32 0
3061  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
3062  %vc = icmp slt <vscale x 8 x i64> %va, %splat
3063  ret <vscale x 8 x i1> %vc
3064}
3065
3066define <vscale x 8 x i1> @icmp_slt_iv_nxv8i64_1(<vscale x 8 x i64> %va) {
3067; CHECK-LABEL: icmp_slt_iv_nxv8i64_1:
3068; CHECK:       # %bb.0:
3069; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
3070; CHECK-NEXT:    vmsgt.vi v0, v8, -15
3071; CHECK-NEXT:    ret
3072  %head = insertelement <vscale x 8 x i64> poison, i64 -15, i32 0
3073  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
3074  %vc = icmp slt <vscale x 8 x i64> %splat, %va
3075  ret <vscale x 8 x i1> %vc
3076}
3077
3078define <vscale x 8 x i1> @icmp_slt_vi_nxv8i64_2(<vscale x 8 x i64> %va) {
3079; CHECK-LABEL: icmp_slt_vi_nxv8i64_2:
3080; CHECK:       # %bb.0:
3081; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
3082; CHECK-NEXT:    vmslt.vx v0, v8, zero
3083; CHECK-NEXT:    ret
3084  %head = insertelement <vscale x 8 x i64> poison, i64 0, i32 0
3085  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
3086  %vc = icmp slt <vscale x 8 x i64> %va, %splat
3087  ret <vscale x 8 x i1> %vc
3088}
3089
3090define <vscale x 8 x i1> @icmp_slt_vi_nxv8i64_3(<vscale x 8 x i64> %va) {
3091; CHECK-LABEL: icmp_slt_vi_nxv8i64_3:
3092; CHECK:       # %bb.0:
3093; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
3094; CHECK-NEXT:    vmsle.vi v0, v8, 15
3095; CHECK-NEXT:    ret
3096  %head = insertelement <vscale x 8 x i64> poison, i64 16, i32 0
3097  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
3098  %vc = icmp slt <vscale x 8 x i64> %va, %splat
3099  ret <vscale x 8 x i1> %vc
3100}
3101
3102define <vscale x 8 x i1> @icmp_sle_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) {
3103; CHECK-LABEL: icmp_sle_vv_nxv8i64:
3104; CHECK:       # %bb.0:
3105; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
3106; CHECK-NEXT:    vmsle.vv v0, v8, v16
3107; CHECK-NEXT:    ret
3108  %vc = icmp sle <vscale x 8 x i64> %va, %vb
3109  ret <vscale x 8 x i1> %vc
3110}
3111
3112define <vscale x 8 x i1> @icmp_sle_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
3113; RV32-LABEL: icmp_sle_vx_nxv8i64:
3114; RV32:       # %bb.0:
3115; RV32-NEXT:    addi sp, sp, -16
3116; RV32-NEXT:    .cfi_def_cfa_offset 16
3117; RV32-NEXT:    sw a1, 12(sp)
3118; RV32-NEXT:    sw a0, 8(sp)
3119; RV32-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
3120; RV32-NEXT:    addi a0, sp, 8
3121; RV32-NEXT:    vlse64.v v16, (a0), zero
3122; RV32-NEXT:    vmsle.vv v0, v8, v16
3123; RV32-NEXT:    addi sp, sp, 16
3124; RV32-NEXT:    ret
3125;
3126; RV64-LABEL: icmp_sle_vx_nxv8i64:
3127; RV64:       # %bb.0:
3128; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
3129; RV64-NEXT:    vmsle.vx v0, v8, a0
3130; RV64-NEXT:    ret
3131  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
3132  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
3133  %vc = icmp sle <vscale x 8 x i64> %va, %splat
3134  ret <vscale x 8 x i1> %vc
3135}
3136
3137define <vscale x 8 x i1> @icmp_sle_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) {
3138; RV32-LABEL: icmp_sle_xv_nxv8i64:
3139; RV32:       # %bb.0:
3140; RV32-NEXT:    addi sp, sp, -16
3141; RV32-NEXT:    .cfi_def_cfa_offset 16
3142; RV32-NEXT:    sw a1, 12(sp)
3143; RV32-NEXT:    sw a0, 8(sp)
3144; RV32-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
3145; RV32-NEXT:    addi a0, sp, 8
3146; RV32-NEXT:    vlse64.v v16, (a0), zero
3147; RV32-NEXT:    vmsle.vv v0, v16, v8
3148; RV32-NEXT:    addi sp, sp, 16
3149; RV32-NEXT:    ret
3150;
3151; RV64-LABEL: icmp_sle_xv_nxv8i64:
3152; RV64:       # %bb.0:
3153; RV64-NEXT:    vsetvli a1, zero, e64, m8, ta, mu
3154; RV64-NEXT:    vmv.v.x v16, a0
3155; RV64-NEXT:    vmsle.vv v0, v16, v8
3156; RV64-NEXT:    ret
3157  %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0
3158  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
3159  %vc = icmp sle <vscale x 8 x i64> %splat, %va
3160  ret <vscale x 8 x i1> %vc
3161}
3162
3163define <vscale x 8 x i1> @icmp_sle_vi_nxv8i64_0(<vscale x 8 x i64> %va) {
3164; CHECK-LABEL: icmp_sle_vi_nxv8i64_0:
3165; CHECK:       # %bb.0:
3166; CHECK-NEXT:    vsetvli a0, zero, e64, m8, ta, mu
3167; CHECK-NEXT:    vmsle.vi v0, v8, 5
3168; CHECK-NEXT:    ret
3169  %head = insertelement <vscale x 8 x i64> poison, i64 5, i32 0
3170  %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer
3171  %vc = icmp sle <vscale x 8 x i64> %va, %splat
3172  ret <vscale x 8 x i1> %vc
3173}
3174
3175; Check a setcc with two constant splats, which would previously get stuck in
3176; an infinite loop. DAGCombine isn't clever enough to constant-fold
3177; splat_vectors but could continuously swap the operands, trying to put the
3178; splat on the RHS.
3179define <vscale x 8 x i1> @icmp_eq_ii_nxv8i8() {
3180; CHECK-LABEL: icmp_eq_ii_nxv8i8:
3181; CHECK:       # %bb.0:
3182; CHECK-NEXT:    vsetvli a0, zero, e8, m1, ta, mu
3183; CHECK-NEXT:    vmclr.m v0
3184; CHECK-NEXT:    ret
3185  %heada = insertelement <vscale x 8 x i8> poison, i8 5, i32 0
3186  %splata = shufflevector <vscale x 8 x i8> %heada, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
3187  %headb = insertelement <vscale x 8 x i8> poison, i8 2, i32 0
3188  %splatb = shufflevector <vscale x 8 x i8> %headb, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer
3189  %vc = icmp eq <vscale x 8 x i8> %splata, %splatb
3190  ret <vscale x 8 x i1> %vc
3191}
3192
3193; This icmp/setcc is split and so we find a scalable-vector mask CONCAT_VECTOR
3194; node. Ensure we correctly (custom) lower this.
3195define <vscale x 16 x i1> @icmp_eq_vi_nx16i64(<vscale x 16 x i64> %va) {
3196; CHECK-LABEL: icmp_eq_vi_nx16i64:
3197; CHECK:       # %bb.0:
3198; CHECK-NEXT:    csrr a0, vlenb
3199; CHECK-NEXT:    srli a0, a0, 3
3200; CHECK-NEXT:    add a1, a0, a0
3201; CHECK-NEXT:    vsetvli a2, zero, e64, m8, ta, mu
3202; CHECK-NEXT:    vmseq.vi v24, v16, 0
3203; CHECK-NEXT:    vmseq.vi v0, v8, 0
3204; CHECK-NEXT:    vsetvli zero, a1, e8, mf4, ta, mu
3205; CHECK-NEXT:    vslideup.vx v0, v24, a0
3206; CHECK-NEXT:    ret
3207  %vc = icmp eq <vscale x 16 x i64> %va, zeroinitializer
3208  ret <vscale x 16 x i1> %vc
3209}
3210