1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py 2; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+m,+v \ 3; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV32 4; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+m,+v \ 5; RUN: -verify-machineinstrs | FileCheck %s --check-prefixes=CHECK,RV64 6 7define <vscale x 3 x i1> @icmp_eq_vv_nxv3i8(<vscale x 3 x i8> %va, <vscale x 3 x i8> %vb) { 8; CHECK-LABEL: icmp_eq_vv_nxv3i8: 9; CHECK: # %bb.0: 10; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma 11; CHECK-NEXT: vmseq.vv v0, v8, v9 12; CHECK-NEXT: ret 13 %vc = icmp eq <vscale x 3 x i8> %va, %vb 14 ret <vscale x 3 x i1> %vc 15} 16 17define <vscale x 3 x i1> @icmp_eq_vx_nxv3i8(<vscale x 3 x i8> %va, i8 %b) { 18; CHECK-LABEL: icmp_eq_vx_nxv3i8: 19; CHECK: # %bb.0: 20; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma 21; CHECK-NEXT: vmseq.vx v0, v8, a0 22; CHECK-NEXT: ret 23 %head = insertelement <vscale x 3 x i8> poison, i8 %b, i32 0 24 %splat = shufflevector <vscale x 3 x i8> %head, <vscale x 3 x i8> poison, <vscale x 3 x i32> zeroinitializer 25 %vc = icmp eq <vscale x 3 x i8> %va, %splat 26 ret <vscale x 3 x i1> %vc 27} 28 29define <vscale x 3 x i1> @icmp_eq_xv_nxv3i8(<vscale x 3 x i8> %va, i8 %b) { 30; CHECK-LABEL: icmp_eq_xv_nxv3i8: 31; CHECK: # %bb.0: 32; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma 33; CHECK-NEXT: vmseq.vx v0, v8, a0 34; CHECK-NEXT: ret 35 %head = insertelement <vscale x 3 x i8> poison, i8 %b, i32 0 36 %splat = shufflevector <vscale x 3 x i8> %head, <vscale x 3 x i8> poison, <vscale x 3 x i32> zeroinitializer 37 %vc = icmp eq <vscale x 3 x i8> %splat, %va 38 ret <vscale x 3 x i1> %vc 39} 40 41define <vscale x 8 x i1> @icmp_eq_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) { 42; CHECK-LABEL: icmp_eq_vv_nxv8i8: 43; CHECK: # %bb.0: 44; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma 45; CHECK-NEXT: vmseq.vv v0, v8, v9 46; CHECK-NEXT: ret 47 %vc = icmp eq <vscale x 8 x i8> %va, %vb 48 ret <vscale x 8 x i1> %vc 49} 50 51define <vscale x 8 x i1> @icmp_eq_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) { 52; CHECK-LABEL: icmp_eq_vx_nxv8i8: 53; CHECK: # %bb.0: 54; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma 55; CHECK-NEXT: vmseq.vx v0, v8, a0 56; CHECK-NEXT: ret 57 %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0 58 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 59 %vc = icmp eq <vscale x 8 x i8> %va, %splat 60 ret <vscale x 8 x i1> %vc 61} 62 63define <vscale x 8 x i1> @icmp_eq_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) { 64; CHECK-LABEL: icmp_eq_xv_nxv8i8: 65; CHECK: # %bb.0: 66; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma 67; CHECK-NEXT: vmseq.vx v0, v8, a0 68; CHECK-NEXT: ret 69 %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0 70 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 71 %vc = icmp eq <vscale x 8 x i8> %splat, %va 72 ret <vscale x 8 x i1> %vc 73} 74 75define <vscale x 8 x i1> @icmp_eq_vi_nxv8i8_0(<vscale x 8 x i8> %va) { 76; CHECK-LABEL: icmp_eq_vi_nxv8i8_0: 77; CHECK: # %bb.0: 78; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma 79; CHECK-NEXT: vmseq.vi v0, v8, 0 80; CHECK-NEXT: ret 81 %head = insertelement <vscale x 8 x i8> poison, i8 0, i32 0 82 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 83 %vc = icmp eq <vscale x 8 x i8> %va, %splat 84 ret <vscale x 8 x i1> %vc 85} 86 87define <vscale x 8 x i1> @icmp_eq_vi_nxv8i8_1(<vscale x 8 x i8> %va) { 88; CHECK-LABEL: icmp_eq_vi_nxv8i8_1: 89; CHECK: # %bb.0: 90; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma 91; CHECK-NEXT: vmseq.vi v0, v8, 5 92; CHECK-NEXT: ret 93 %head = insertelement <vscale x 8 x i8> poison, i8 5, i32 0 94 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 95 %vc = icmp eq <vscale x 8 x i8> %va, %splat 96 ret <vscale x 8 x i1> %vc 97} 98 99define <vscale x 8 x i1> @icmp_eq_iv_nxv8i8_1(<vscale x 8 x i8> %va) { 100; CHECK-LABEL: icmp_eq_iv_nxv8i8_1: 101; CHECK: # %bb.0: 102; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma 103; CHECK-NEXT: vmseq.vi v0, v8, 5 104; CHECK-NEXT: ret 105 %head = insertelement <vscale x 8 x i8> poison, i8 5, i32 0 106 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 107 %vc = icmp eq <vscale x 8 x i8> %splat, %va 108 ret <vscale x 8 x i1> %vc 109} 110 111define <vscale x 8 x i1> @icmp_ne_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) { 112; CHECK-LABEL: icmp_ne_vv_nxv8i8: 113; CHECK: # %bb.0: 114; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma 115; CHECK-NEXT: vmsne.vv v0, v8, v9 116; CHECK-NEXT: ret 117 %vc = icmp ne <vscale x 8 x i8> %va, %vb 118 ret <vscale x 8 x i1> %vc 119} 120 121define <vscale x 8 x i1> @icmp_ne_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) { 122; CHECK-LABEL: icmp_ne_vx_nxv8i8: 123; CHECK: # %bb.0: 124; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma 125; CHECK-NEXT: vmsne.vx v0, v8, a0 126; CHECK-NEXT: ret 127 %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0 128 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 129 %vc = icmp ne <vscale x 8 x i8> %va, %splat 130 ret <vscale x 8 x i1> %vc 131} 132 133define <vscale x 8 x i1> @icmp_ne_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) { 134; CHECK-LABEL: icmp_ne_xv_nxv8i8: 135; CHECK: # %bb.0: 136; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma 137; CHECK-NEXT: vmsne.vx v0, v8, a0 138; CHECK-NEXT: ret 139 %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0 140 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 141 %vc = icmp ne <vscale x 8 x i8> %splat, %va 142 ret <vscale x 8 x i1> %vc 143} 144 145define <vscale x 8 x i1> @icmp_ne_vi_nxv8i8_0(<vscale x 8 x i8> %va) { 146; CHECK-LABEL: icmp_ne_vi_nxv8i8_0: 147; CHECK: # %bb.0: 148; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma 149; CHECK-NEXT: vmsne.vi v0, v8, 5 150; CHECK-NEXT: ret 151 %head = insertelement <vscale x 8 x i8> poison, i8 5, i32 0 152 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 153 %vc = icmp ne <vscale x 8 x i8> %va, %splat 154 ret <vscale x 8 x i1> %vc 155} 156 157define <vscale x 8 x i1> @icmp_ugt_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) { 158; CHECK-LABEL: icmp_ugt_vv_nxv8i8: 159; CHECK: # %bb.0: 160; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma 161; CHECK-NEXT: vmsltu.vv v0, v9, v8 162; CHECK-NEXT: ret 163 %vc = icmp ugt <vscale x 8 x i8> %va, %vb 164 ret <vscale x 8 x i1> %vc 165} 166 167define <vscale x 8 x i1> @icmp_ugt_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) { 168; CHECK-LABEL: icmp_ugt_vx_nxv8i8: 169; CHECK: # %bb.0: 170; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma 171; CHECK-NEXT: vmsgtu.vx v0, v8, a0 172; CHECK-NEXT: ret 173 %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0 174 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 175 %vc = icmp ugt <vscale x 8 x i8> %va, %splat 176 ret <vscale x 8 x i1> %vc 177} 178 179define <vscale x 8 x i1> @icmp_ugt_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) { 180; CHECK-LABEL: icmp_ugt_xv_nxv8i8: 181; CHECK: # %bb.0: 182; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma 183; CHECK-NEXT: vmsltu.vx v0, v8, a0 184; CHECK-NEXT: ret 185 %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0 186 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 187 %vc = icmp ugt <vscale x 8 x i8> %splat, %va 188 ret <vscale x 8 x i1> %vc 189} 190 191define <vscale x 8 x i1> @icmp_ugt_vi_nxv8i8_0(<vscale x 8 x i8> %va) { 192; CHECK-LABEL: icmp_ugt_vi_nxv8i8_0: 193; CHECK: # %bb.0: 194; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma 195; CHECK-NEXT: vmsgtu.vi v0, v8, 5 196; CHECK-NEXT: ret 197 %head = insertelement <vscale x 8 x i8> poison, i8 5, i32 0 198 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 199 %vc = icmp ugt <vscale x 8 x i8> %va, %splat 200 ret <vscale x 8 x i1> %vc 201} 202 203define <vscale x 8 x i1> @icmp_uge_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) { 204; CHECK-LABEL: icmp_uge_vv_nxv8i8: 205; CHECK: # %bb.0: 206; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma 207; CHECK-NEXT: vmsleu.vv v0, v9, v8 208; CHECK-NEXT: ret 209 %vc = icmp uge <vscale x 8 x i8> %va, %vb 210 ret <vscale x 8 x i1> %vc 211} 212 213define <vscale x 8 x i1> @icmp_uge_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) { 214; CHECK-LABEL: icmp_uge_vx_nxv8i8: 215; CHECK: # %bb.0: 216; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma 217; CHECK-NEXT: vmv.v.x v9, a0 218; CHECK-NEXT: vmsleu.vv v0, v9, v8 219; CHECK-NEXT: ret 220 %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0 221 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 222 %vc = icmp uge <vscale x 8 x i8> %va, %splat 223 ret <vscale x 8 x i1> %vc 224} 225 226define <vscale x 8 x i1> @icmp_uge_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) { 227; CHECK-LABEL: icmp_uge_xv_nxv8i8: 228; CHECK: # %bb.0: 229; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma 230; CHECK-NEXT: vmsleu.vx v0, v8, a0 231; CHECK-NEXT: ret 232 %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0 233 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 234 %vc = icmp uge <vscale x 8 x i8> %splat, %va 235 ret <vscale x 8 x i1> %vc 236} 237 238define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_0(<vscale x 8 x i8> %va) { 239; CHECK-LABEL: icmp_uge_vi_nxv8i8_0: 240; CHECK: # %bb.0: 241; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma 242; CHECK-NEXT: vmv.v.i v9, -16 243; CHECK-NEXT: vmsleu.vv v0, v9, v8 244; CHECK-NEXT: ret 245 %head = insertelement <vscale x 8 x i8> poison, i8 -16, i32 0 246 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 247 %vc = icmp uge <vscale x 8 x i8> %va, %splat 248 ret <vscale x 8 x i1> %vc 249} 250 251define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_1(<vscale x 8 x i8> %va) { 252; CHECK-LABEL: icmp_uge_vi_nxv8i8_1: 253; CHECK: # %bb.0: 254; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma 255; CHECK-NEXT: vmsgtu.vi v0, v8, 14 256; CHECK-NEXT: ret 257 %head = insertelement <vscale x 8 x i8> poison, i8 15, i32 0 258 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 259 %vc = icmp uge <vscale x 8 x i8> %va, %splat 260 ret <vscale x 8 x i1> %vc 261} 262 263define <vscale x 8 x i1> @icmp_uge_iv_nxv8i8_1(<vscale x 8 x i8> %va) { 264; CHECK-LABEL: icmp_uge_iv_nxv8i8_1: 265; CHECK: # %bb.0: 266; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma 267; CHECK-NEXT: vmsleu.vi v0, v8, 15 268; CHECK-NEXT: ret 269 %head = insertelement <vscale x 8 x i8> poison, i8 15, i32 0 270 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 271 %vc = icmp uge <vscale x 8 x i8> %splat, %va 272 ret <vscale x 8 x i1> %vc 273} 274 275define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_2(<vscale x 8 x i8> %va) { 276; CHECK-LABEL: icmp_uge_vi_nxv8i8_2: 277; CHECK: # %bb.0: 278; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma 279; CHECK-NEXT: vmset.m v0 280; CHECK-NEXT: ret 281 %head = insertelement <vscale x 8 x i8> poison, i8 0, i32 0 282 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 283 %vc = icmp uge <vscale x 8 x i8> %va, %splat 284 ret <vscale x 8 x i1> %vc 285} 286 287define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_3(<vscale x 8 x i8> %va) { 288; CHECK-LABEL: icmp_uge_vi_nxv8i8_3: 289; CHECK: # %bb.0: 290; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma 291; CHECK-NEXT: vmsgtu.vi v0, v8, 0 292; CHECK-NEXT: ret 293 %head = insertelement <vscale x 8 x i8> poison, i8 1, i32 0 294 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 295 %vc = icmp uge <vscale x 8 x i8> %va, %splat 296 ret <vscale x 8 x i1> %vc 297} 298 299define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_4(<vscale x 8 x i8> %va) { 300; CHECK-LABEL: icmp_uge_vi_nxv8i8_4: 301; CHECK: # %bb.0: 302; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma 303; CHECK-NEXT: vmsgtu.vi v0, v8, -16 304; CHECK-NEXT: ret 305 %head = insertelement <vscale x 8 x i8> poison, i8 -15, i32 0 306 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 307 %vc = icmp uge <vscale x 8 x i8> %va, %splat 308 ret <vscale x 8 x i1> %vc 309} 310 311define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_5(<vscale x 8 x i8> %va) { 312; CHECK-LABEL: icmp_uge_vi_nxv8i8_5: 313; CHECK: # %bb.0: 314; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma 315; CHECK-NEXT: vmsgtu.vi v0, v8, 15 316; CHECK-NEXT: ret 317 %head = insertelement <vscale x 8 x i8> poison, i8 16, i32 0 318 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 319 %vc = icmp uge <vscale x 8 x i8> %va, %splat 320 ret <vscale x 8 x i1> %vc 321} 322 323; Test that we don't optimize uge x, 0 -> ugt x, -1 324define <vscale x 8 x i1> @icmp_uge_vi_nxv8i8_6(<vscale x 8 x i8> %va, iXLen %vl) { 325; CHECK-LABEL: icmp_uge_vi_nxv8i8_6: 326; CHECK: # %bb.0: 327; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma 328; CHECK-NEXT: vmv.v.i v9, 0 329; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma 330; CHECK-NEXT: vmsleu.vv v0, v9, v8 331; CHECK-NEXT: ret 332 %splat = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.iXLen(<vscale x 8 x i8> undef, i8 0, iXLen %vl) 333 %vc = icmp uge <vscale x 8 x i8> %va, %splat 334 ret <vscale x 8 x i1> %vc 335} 336 337define <vscale x 8 x i1> @icmp_ult_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) { 338; CHECK-LABEL: icmp_ult_vv_nxv8i8: 339; CHECK: # %bb.0: 340; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma 341; CHECK-NEXT: vmsltu.vv v0, v8, v9 342; CHECK-NEXT: ret 343 %vc = icmp ult <vscale x 8 x i8> %va, %vb 344 ret <vscale x 8 x i1> %vc 345} 346 347define <vscale x 8 x i1> @icmp_ult_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) { 348; CHECK-LABEL: icmp_ult_vx_nxv8i8: 349; CHECK: # %bb.0: 350; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma 351; CHECK-NEXT: vmsltu.vx v0, v8, a0 352; CHECK-NEXT: ret 353 %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0 354 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 355 %vc = icmp ult <vscale x 8 x i8> %va, %splat 356 ret <vscale x 8 x i1> %vc 357} 358 359define <vscale x 8 x i1> @icmp_ult_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) { 360; CHECK-LABEL: icmp_ult_xv_nxv8i8: 361; CHECK: # %bb.0: 362; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma 363; CHECK-NEXT: vmsgtu.vx v0, v8, a0 364; CHECK-NEXT: ret 365 %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0 366 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 367 %vc = icmp ult <vscale x 8 x i8> %splat, %va 368 ret <vscale x 8 x i1> %vc 369} 370 371define <vscale x 8 x i1> @icmp_ult_vi_nxv8i8_0(<vscale x 8 x i8> %va) { 372; CHECK-LABEL: icmp_ult_vi_nxv8i8_0: 373; CHECK: # %bb.0: 374; CHECK-NEXT: li a0, -16 375; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma 376; CHECK-NEXT: vmsltu.vx v0, v8, a0 377; CHECK-NEXT: ret 378 %head = insertelement <vscale x 8 x i8> poison, i8 -16, i32 0 379 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 380 %vc = icmp ult <vscale x 8 x i8> %va, %splat 381 ret <vscale x 8 x i1> %vc 382} 383 384define <vscale x 8 x i1> @icmp_ult_vi_nxv8i8_1(<vscale x 8 x i8> %va) { 385; CHECK-LABEL: icmp_ult_vi_nxv8i8_1: 386; CHECK: # %bb.0: 387; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma 388; CHECK-NEXT: vmsleu.vi v0, v8, -16 389; CHECK-NEXT: ret 390 %head = insertelement <vscale x 8 x i8> poison, i8 -15, i32 0 391 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 392 %vc = icmp ult <vscale x 8 x i8> %va, %splat 393 ret <vscale x 8 x i1> %vc 394} 395 396define <vscale x 8 x i1> @icmp_ult_iv_nxv8i8_1(<vscale x 8 x i8> %va) { 397; CHECK-LABEL: icmp_ult_iv_nxv8i8_1: 398; CHECK: # %bb.0: 399; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma 400; CHECK-NEXT: vmsgtu.vi v0, v8, -15 401; CHECK-NEXT: ret 402 %head = insertelement <vscale x 8 x i8> poison, i8 -15, i32 0 403 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 404 %vc = icmp ult <vscale x 8 x i8> %splat, %va 405 ret <vscale x 8 x i1> %vc 406} 407 408define <vscale x 8 x i1> @icmp_ult_vi_nxv8i8_2(<vscale x 8 x i8> %va) { 409; CHECK-LABEL: icmp_ult_vi_nxv8i8_2: 410; CHECK: # %bb.0: 411; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma 412; CHECK-NEXT: vmclr.m v0 413; CHECK-NEXT: ret 414 %head = insertelement <vscale x 8 x i8> poison, i8 0, i32 0 415 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 416 %vc = icmp ult <vscale x 8 x i8> %va, %splat 417 ret <vscale x 8 x i1> %vc 418} 419 420define <vscale x 8 x i1> @icmp_ult_vi_nxv8i8_3(<vscale x 8 x i8> %va) { 421; CHECK-LABEL: icmp_ult_vi_nxv8i8_3: 422; CHECK: # %bb.0: 423; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma 424; CHECK-NEXT: vmseq.vi v0, v8, 0 425; CHECK-NEXT: ret 426 %head = insertelement <vscale x 8 x i8> poison, i8 1, i32 0 427 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 428 %vc = icmp ult <vscale x 8 x i8> %va, %splat 429 ret <vscale x 8 x i1> %vc 430} 431 432define <vscale x 8 x i1> @icmp_ult_vi_nxv8i8_4(<vscale x 8 x i8> %va) { 433; CHECK-LABEL: icmp_ult_vi_nxv8i8_4: 434; CHECK: # %bb.0: 435; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma 436; CHECK-NEXT: vmsleu.vi v0, v8, 15 437; CHECK-NEXT: ret 438 %head = insertelement <vscale x 8 x i8> poison, i8 16, i32 0 439 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 440 %vc = icmp ult <vscale x 8 x i8> %va, %splat 441 ret <vscale x 8 x i1> %vc 442} 443 444declare <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.iXLen(<vscale x 8 x i8>, i8, iXLen); 445 446; Test that we don't optimize ult x, 0 -> ule x, -1 447define <vscale x 8 x i1> @icmp_ult_vi_nxv8i8_5(<vscale x 8 x i8> %va, iXLen %vl) { 448; CHECK-LABEL: icmp_ult_vi_nxv8i8_5: 449; CHECK: # %bb.0: 450; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma 451; CHECK-NEXT: vmsltu.vx v0, v8, zero 452; CHECK-NEXT: ret 453 %splat = call <vscale x 8 x i8> @llvm.riscv.vmv.v.x.nxv8i8.iXLen(<vscale x 8 x i8> undef, i8 0, iXLen %vl) 454 %vc = icmp ult <vscale x 8 x i8> %va, %splat 455 ret <vscale x 8 x i1> %vc 456} 457 458define <vscale x 8 x i1> @icmp_ule_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) { 459; CHECK-LABEL: icmp_ule_vv_nxv8i8: 460; CHECK: # %bb.0: 461; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma 462; CHECK-NEXT: vmsleu.vv v0, v8, v9 463; CHECK-NEXT: ret 464 %vc = icmp ule <vscale x 8 x i8> %va, %vb 465 ret <vscale x 8 x i1> %vc 466} 467 468define <vscale x 8 x i1> @icmp_ule_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) { 469; CHECK-LABEL: icmp_ule_vx_nxv8i8: 470; CHECK: # %bb.0: 471; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma 472; CHECK-NEXT: vmsleu.vx v0, v8, a0 473; CHECK-NEXT: ret 474 %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0 475 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 476 %vc = icmp ule <vscale x 8 x i8> %va, %splat 477 ret <vscale x 8 x i1> %vc 478} 479 480define <vscale x 8 x i1> @icmp_ule_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) { 481; CHECK-LABEL: icmp_ule_xv_nxv8i8: 482; CHECK: # %bb.0: 483; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma 484; CHECK-NEXT: vmv.v.x v9, a0 485; CHECK-NEXT: vmsleu.vv v0, v9, v8 486; CHECK-NEXT: ret 487 %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0 488 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 489 %vc = icmp ule <vscale x 8 x i8> %splat, %va 490 ret <vscale x 8 x i1> %vc 491} 492 493define <vscale x 8 x i1> @icmp_ule_vi_nxv8i8_0(<vscale x 8 x i8> %va) { 494; CHECK-LABEL: icmp_ule_vi_nxv8i8_0: 495; CHECK: # %bb.0: 496; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma 497; CHECK-NEXT: vmsleu.vi v0, v8, 5 498; CHECK-NEXT: ret 499 %head = insertelement <vscale x 8 x i8> poison, i8 5, i32 0 500 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 501 %vc = icmp ule <vscale x 8 x i8> %va, %splat 502 ret <vscale x 8 x i1> %vc 503} 504 505define <vscale x 8 x i1> @icmp_sgt_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) { 506; CHECK-LABEL: icmp_sgt_vv_nxv8i8: 507; CHECK: # %bb.0: 508; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma 509; CHECK-NEXT: vmslt.vv v0, v9, v8 510; CHECK-NEXT: ret 511 %vc = icmp sgt <vscale x 8 x i8> %va, %vb 512 ret <vscale x 8 x i1> %vc 513} 514 515define <vscale x 8 x i1> @icmp_sgt_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) { 516; CHECK-LABEL: icmp_sgt_vx_nxv8i8: 517; CHECK: # %bb.0: 518; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma 519; CHECK-NEXT: vmsgt.vx v0, v8, a0 520; CHECK-NEXT: ret 521 %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0 522 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 523 %vc = icmp sgt <vscale x 8 x i8> %va, %splat 524 ret <vscale x 8 x i1> %vc 525} 526 527define <vscale x 8 x i1> @icmp_sgt_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) { 528; CHECK-LABEL: icmp_sgt_xv_nxv8i8: 529; CHECK: # %bb.0: 530; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma 531; CHECK-NEXT: vmslt.vx v0, v8, a0 532; CHECK-NEXT: ret 533 %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0 534 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 535 %vc = icmp sgt <vscale x 8 x i8> %splat, %va 536 ret <vscale x 8 x i1> %vc 537} 538 539define <vscale x 8 x i1> @icmp_sgt_vi_nxv8i8_0(<vscale x 8 x i8> %va) { 540; CHECK-LABEL: icmp_sgt_vi_nxv8i8_0: 541; CHECK: # %bb.0: 542; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma 543; CHECK-NEXT: vmsgt.vi v0, v8, 5 544; CHECK-NEXT: ret 545 %head = insertelement <vscale x 8 x i8> poison, i8 5, i32 0 546 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 547 %vc = icmp sgt <vscale x 8 x i8> %va, %splat 548 ret <vscale x 8 x i1> %vc 549} 550 551define <vscale x 8 x i1> @icmp_sge_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) { 552; CHECK-LABEL: icmp_sge_vv_nxv8i8: 553; CHECK: # %bb.0: 554; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma 555; CHECK-NEXT: vmsle.vv v0, v9, v8 556; CHECK-NEXT: ret 557 %vc = icmp sge <vscale x 8 x i8> %va, %vb 558 ret <vscale x 8 x i1> %vc 559} 560 561define <vscale x 8 x i1> @icmp_sge_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) { 562; CHECK-LABEL: icmp_sge_vx_nxv8i8: 563; CHECK: # %bb.0: 564; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma 565; CHECK-NEXT: vmv.v.x v9, a0 566; CHECK-NEXT: vmsle.vv v0, v9, v8 567; CHECK-NEXT: ret 568 %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0 569 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 570 %vc = icmp sge <vscale x 8 x i8> %va, %splat 571 ret <vscale x 8 x i1> %vc 572} 573 574define <vscale x 8 x i1> @icmp_sge_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) { 575; CHECK-LABEL: icmp_sge_xv_nxv8i8: 576; CHECK: # %bb.0: 577; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma 578; CHECK-NEXT: vmsle.vx v0, v8, a0 579; CHECK-NEXT: ret 580 %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0 581 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 582 %vc = icmp sge <vscale x 8 x i8> %splat, %va 583 ret <vscale x 8 x i1> %vc 584} 585 586define <vscale x 8 x i1> @icmp_sge_vi_nxv8i8_0(<vscale x 8 x i8> %va) { 587; CHECK-LABEL: icmp_sge_vi_nxv8i8_0: 588; CHECK: # %bb.0: 589; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma 590; CHECK-NEXT: vmv.v.i v9, -16 591; CHECK-NEXT: vmsle.vv v0, v9, v8 592; CHECK-NEXT: ret 593 %head = insertelement <vscale x 8 x i8> poison, i8 -16, i32 0 594 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 595 %vc = icmp sge <vscale x 8 x i8> %va, %splat 596 ret <vscale x 8 x i1> %vc 597} 598 599define <vscale x 8 x i1> @icmp_sge_vi_nxv8i8_1(<vscale x 8 x i8> %va) { 600; CHECK-LABEL: icmp_sge_vi_nxv8i8_1: 601; CHECK: # %bb.0: 602; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma 603; CHECK-NEXT: vmsgt.vi v0, v8, -16 604; CHECK-NEXT: ret 605 %head = insertelement <vscale x 8 x i8> poison, i8 -15, i32 0 606 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 607 %vc = icmp sge <vscale x 8 x i8> %va, %splat 608 ret <vscale x 8 x i1> %vc 609} 610 611define <vscale x 8 x i1> @icmp_sge_iv_nxv8i8_1(<vscale x 8 x i8> %va) { 612; CHECK-LABEL: icmp_sge_iv_nxv8i8_1: 613; CHECK: # %bb.0: 614; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma 615; CHECK-NEXT: vmsle.vi v0, v8, -15 616; CHECK-NEXT: ret 617 %head = insertelement <vscale x 8 x i8> poison, i8 -15, i32 0 618 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 619 %vc = icmp sge <vscale x 8 x i8> %splat, %va 620 ret <vscale x 8 x i1> %vc 621} 622 623define <vscale x 8 x i1> @icmp_sge_vi_nxv8i8_2(<vscale x 8 x i8> %va) { 624; CHECK-LABEL: icmp_sge_vi_nxv8i8_2: 625; CHECK: # %bb.0: 626; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma 627; CHECK-NEXT: vmsgt.vi v0, v8, -1 628; CHECK-NEXT: ret 629 %head = insertelement <vscale x 8 x i8> poison, i8 0, i32 0 630 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 631 %vc = icmp sge <vscale x 8 x i8> %va, %splat 632 ret <vscale x 8 x i1> %vc 633} 634 635define <vscale x 8 x i1> @icmp_sge_vi_nxv8i8_3(<vscale x 8 x i8> %va) { 636; CHECK-LABEL: icmp_sge_vi_nxv8i8_3: 637; CHECK: # %bb.0: 638; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma 639; CHECK-NEXT: vmsgt.vi v0, v8, 15 640; CHECK-NEXT: ret 641 %head = insertelement <vscale x 8 x i8> poison, i8 16, i32 0 642 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 643 %vc = icmp sge <vscale x 8 x i8> %va, %splat 644 ret <vscale x 8 x i1> %vc 645} 646 647define <vscale x 8 x i1> @icmp_slt_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) { 648; CHECK-LABEL: icmp_slt_vv_nxv8i8: 649; CHECK: # %bb.0: 650; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma 651; CHECK-NEXT: vmslt.vv v0, v8, v9 652; CHECK-NEXT: ret 653 %vc = icmp slt <vscale x 8 x i8> %va, %vb 654 ret <vscale x 8 x i1> %vc 655} 656 657define <vscale x 8 x i1> @icmp_slt_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) { 658; CHECK-LABEL: icmp_slt_vx_nxv8i8: 659; CHECK: # %bb.0: 660; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma 661; CHECK-NEXT: vmslt.vx v0, v8, a0 662; CHECK-NEXT: ret 663 %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0 664 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 665 %vc = icmp slt <vscale x 8 x i8> %va, %splat 666 ret <vscale x 8 x i1> %vc 667} 668 669define <vscale x 8 x i1> @icmp_slt_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) { 670; CHECK-LABEL: icmp_slt_xv_nxv8i8: 671; CHECK: # %bb.0: 672; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma 673; CHECK-NEXT: vmsgt.vx v0, v8, a0 674; CHECK-NEXT: ret 675 %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0 676 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 677 %vc = icmp slt <vscale x 8 x i8> %splat, %va 678 ret <vscale x 8 x i1> %vc 679} 680 681define <vscale x 8 x i1> @icmp_slt_vi_nxv8i8_0(<vscale x 8 x i8> %va) { 682; CHECK-LABEL: icmp_slt_vi_nxv8i8_0: 683; CHECK: # %bb.0: 684; CHECK-NEXT: li a0, -16 685; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma 686; CHECK-NEXT: vmslt.vx v0, v8, a0 687; CHECK-NEXT: ret 688 %head = insertelement <vscale x 8 x i8> poison, i8 -16, i32 0 689 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 690 %vc = icmp slt <vscale x 8 x i8> %va, %splat 691 ret <vscale x 8 x i1> %vc 692} 693 694define <vscale x 8 x i1> @icmp_slt_vi_nxv8i8_1(<vscale x 8 x i8> %va) { 695; CHECK-LABEL: icmp_slt_vi_nxv8i8_1: 696; CHECK: # %bb.0: 697; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma 698; CHECK-NEXT: vmsle.vi v0, v8, -16 699; CHECK-NEXT: ret 700 %head = insertelement <vscale x 8 x i8> poison, i8 -15, i32 0 701 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 702 %vc = icmp slt <vscale x 8 x i8> %va, %splat 703 ret <vscale x 8 x i1> %vc 704} 705 706define <vscale x 8 x i1> @icmp_slt_iv_nxv8i8_1(<vscale x 8 x i8> %va) { 707; CHECK-LABEL: icmp_slt_iv_nxv8i8_1: 708; CHECK: # %bb.0: 709; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma 710; CHECK-NEXT: vmsgt.vi v0, v8, -15 711; CHECK-NEXT: ret 712 %head = insertelement <vscale x 8 x i8> poison, i8 -15, i32 0 713 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 714 %vc = icmp slt <vscale x 8 x i8> %splat, %va 715 ret <vscale x 8 x i1> %vc 716} 717 718define <vscale x 8 x i1> @icmp_slt_vi_nxv8i8_2(<vscale x 8 x i8> %va) { 719; CHECK-LABEL: icmp_slt_vi_nxv8i8_2: 720; CHECK: # %bb.0: 721; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma 722; CHECK-NEXT: vmslt.vx v0, v8, zero 723; CHECK-NEXT: ret 724 %head = insertelement <vscale x 8 x i8> poison, i8 0, i32 0 725 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 726 %vc = icmp slt <vscale x 8 x i8> %va, %splat 727 ret <vscale x 8 x i1> %vc 728} 729 730define <vscale x 8 x i1> @icmp_slt_vi_nxv8i8_3(<vscale x 8 x i8> %va) { 731; CHECK-LABEL: icmp_slt_vi_nxv8i8_3: 732; CHECK: # %bb.0: 733; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma 734; CHECK-NEXT: vmsle.vi v0, v8, 15 735; CHECK-NEXT: ret 736 %head = insertelement <vscale x 8 x i8> poison, i8 16, i32 0 737 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 738 %vc = icmp slt <vscale x 8 x i8> %va, %splat 739 ret <vscale x 8 x i1> %vc 740} 741 742define <vscale x 8 x i1> @icmp_sle_vv_nxv8i8(<vscale x 8 x i8> %va, <vscale x 8 x i8> %vb) { 743; CHECK-LABEL: icmp_sle_vv_nxv8i8: 744; CHECK: # %bb.0: 745; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma 746; CHECK-NEXT: vmsle.vv v0, v8, v9 747; CHECK-NEXT: ret 748 %vc = icmp sle <vscale x 8 x i8> %va, %vb 749 ret <vscale x 8 x i1> %vc 750} 751 752define <vscale x 8 x i1> @icmp_sle_vx_nxv8i8(<vscale x 8 x i8> %va, i8 %b) { 753; CHECK-LABEL: icmp_sle_vx_nxv8i8: 754; CHECK: # %bb.0: 755; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma 756; CHECK-NEXT: vmsle.vx v0, v8, a0 757; CHECK-NEXT: ret 758 %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0 759 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 760 %vc = icmp sle <vscale x 8 x i8> %va, %splat 761 ret <vscale x 8 x i1> %vc 762} 763 764define <vscale x 8 x i1> @icmp_sle_xv_nxv8i8(<vscale x 8 x i8> %va, i8 %b) { 765; CHECK-LABEL: icmp_sle_xv_nxv8i8: 766; CHECK: # %bb.0: 767; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma 768; CHECK-NEXT: vmv.v.x v9, a0 769; CHECK-NEXT: vmsle.vv v0, v9, v8 770; CHECK-NEXT: ret 771 %head = insertelement <vscale x 8 x i8> poison, i8 %b, i32 0 772 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 773 %vc = icmp sle <vscale x 8 x i8> %splat, %va 774 ret <vscale x 8 x i1> %vc 775} 776 777define <vscale x 8 x i1> @icmp_sle_vi_nxv8i8_0(<vscale x 8 x i8> %va) { 778; CHECK-LABEL: icmp_sle_vi_nxv8i8_0: 779; CHECK: # %bb.0: 780; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma 781; CHECK-NEXT: vmsle.vi v0, v8, 5 782; CHECK-NEXT: ret 783 %head = insertelement <vscale x 8 x i8> poison, i8 5, i32 0 784 %splat = shufflevector <vscale x 8 x i8> %head, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 785 %vc = icmp sle <vscale x 8 x i8> %va, %splat 786 ret <vscale x 8 x i1> %vc 787} 788 789define <vscale x 8 x i1> @icmp_eq_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) { 790; CHECK-LABEL: icmp_eq_vv_nxv8i16: 791; CHECK: # %bb.0: 792; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma 793; CHECK-NEXT: vmseq.vv v0, v8, v10 794; CHECK-NEXT: ret 795 %vc = icmp eq <vscale x 8 x i16> %va, %vb 796 ret <vscale x 8 x i1> %vc 797} 798 799define <vscale x 8 x i1> @icmp_eq_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) { 800; CHECK-LABEL: icmp_eq_vx_nxv8i16: 801; CHECK: # %bb.0: 802; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma 803; CHECK-NEXT: vmseq.vx v0, v8, a0 804; CHECK-NEXT: ret 805 %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0 806 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 807 %vc = icmp eq <vscale x 8 x i16> %va, %splat 808 ret <vscale x 8 x i1> %vc 809} 810 811define <vscale x 8 x i1> @icmp_eq_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) { 812; CHECK-LABEL: icmp_eq_xv_nxv8i16: 813; CHECK: # %bb.0: 814; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma 815; CHECK-NEXT: vmseq.vx v0, v8, a0 816; CHECK-NEXT: ret 817 %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0 818 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 819 %vc = icmp eq <vscale x 8 x i16> %splat, %va 820 ret <vscale x 8 x i1> %vc 821} 822 823define <vscale x 8 x i1> @icmp_eq_vi_nxv8i16_0(<vscale x 8 x i16> %va) { 824; CHECK-LABEL: icmp_eq_vi_nxv8i16_0: 825; CHECK: # %bb.0: 826; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma 827; CHECK-NEXT: vmseq.vi v0, v8, 0 828; CHECK-NEXT: ret 829 %head = insertelement <vscale x 8 x i16> poison, i16 0, i32 0 830 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 831 %vc = icmp eq <vscale x 8 x i16> %va, %splat 832 ret <vscale x 8 x i1> %vc 833} 834 835define <vscale x 8 x i1> @icmp_eq_vi_nxv8i16_1(<vscale x 8 x i16> %va) { 836; CHECK-LABEL: icmp_eq_vi_nxv8i16_1: 837; CHECK: # %bb.0: 838; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma 839; CHECK-NEXT: vmseq.vi v0, v8, 5 840; CHECK-NEXT: ret 841 %head = insertelement <vscale x 8 x i16> poison, i16 5, i32 0 842 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 843 %vc = icmp eq <vscale x 8 x i16> %va, %splat 844 ret <vscale x 8 x i1> %vc 845} 846 847define <vscale x 8 x i1> @icmp_eq_iv_nxv8i16_1(<vscale x 8 x i16> %va) { 848; CHECK-LABEL: icmp_eq_iv_nxv8i16_1: 849; CHECK: # %bb.0: 850; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma 851; CHECK-NEXT: vmseq.vi v0, v8, 5 852; CHECK-NEXT: ret 853 %head = insertelement <vscale x 8 x i16> poison, i16 5, i32 0 854 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 855 %vc = icmp eq <vscale x 8 x i16> %splat, %va 856 ret <vscale x 8 x i1> %vc 857} 858 859define <vscale x 8 x i1> @icmp_ne_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) { 860; CHECK-LABEL: icmp_ne_vv_nxv8i16: 861; CHECK: # %bb.0: 862; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma 863; CHECK-NEXT: vmsne.vv v0, v8, v10 864; CHECK-NEXT: ret 865 %vc = icmp ne <vscale x 8 x i16> %va, %vb 866 ret <vscale x 8 x i1> %vc 867} 868 869define <vscale x 8 x i1> @icmp_ne_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) { 870; CHECK-LABEL: icmp_ne_vx_nxv8i16: 871; CHECK: # %bb.0: 872; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma 873; CHECK-NEXT: vmsne.vx v0, v8, a0 874; CHECK-NEXT: ret 875 %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0 876 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 877 %vc = icmp ne <vscale x 8 x i16> %va, %splat 878 ret <vscale x 8 x i1> %vc 879} 880 881define <vscale x 8 x i1> @icmp_ne_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) { 882; CHECK-LABEL: icmp_ne_xv_nxv8i16: 883; CHECK: # %bb.0: 884; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma 885; CHECK-NEXT: vmsne.vx v0, v8, a0 886; CHECK-NEXT: ret 887 %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0 888 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 889 %vc = icmp ne <vscale x 8 x i16> %splat, %va 890 ret <vscale x 8 x i1> %vc 891} 892 893define <vscale x 8 x i1> @icmp_ne_vi_nxv8i16_0(<vscale x 8 x i16> %va) { 894; CHECK-LABEL: icmp_ne_vi_nxv8i16_0: 895; CHECK: # %bb.0: 896; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma 897; CHECK-NEXT: vmsne.vi v0, v8, 5 898; CHECK-NEXT: ret 899 %head = insertelement <vscale x 8 x i16> poison, i16 5, i32 0 900 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 901 %vc = icmp ne <vscale x 8 x i16> %va, %splat 902 ret <vscale x 8 x i1> %vc 903} 904 905define <vscale x 8 x i1> @icmp_ugt_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) { 906; CHECK-LABEL: icmp_ugt_vv_nxv8i16: 907; CHECK: # %bb.0: 908; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma 909; CHECK-NEXT: vmsltu.vv v0, v10, v8 910; CHECK-NEXT: ret 911 %vc = icmp ugt <vscale x 8 x i16> %va, %vb 912 ret <vscale x 8 x i1> %vc 913} 914 915define <vscale x 8 x i1> @icmp_ugt_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) { 916; CHECK-LABEL: icmp_ugt_vx_nxv8i16: 917; CHECK: # %bb.0: 918; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma 919; CHECK-NEXT: vmsgtu.vx v0, v8, a0 920; CHECK-NEXT: ret 921 %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0 922 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 923 %vc = icmp ugt <vscale x 8 x i16> %va, %splat 924 ret <vscale x 8 x i1> %vc 925} 926 927define <vscale x 8 x i1> @icmp_ugt_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) { 928; CHECK-LABEL: icmp_ugt_xv_nxv8i16: 929; CHECK: # %bb.0: 930; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma 931; CHECK-NEXT: vmsltu.vx v0, v8, a0 932; CHECK-NEXT: ret 933 %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0 934 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 935 %vc = icmp ugt <vscale x 8 x i16> %splat, %va 936 ret <vscale x 8 x i1> %vc 937} 938 939define <vscale x 8 x i1> @icmp_ugt_vi_nxv8i16_0(<vscale x 8 x i16> %va) { 940; CHECK-LABEL: icmp_ugt_vi_nxv8i16_0: 941; CHECK: # %bb.0: 942; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma 943; CHECK-NEXT: vmsgtu.vi v0, v8, 5 944; CHECK-NEXT: ret 945 %head = insertelement <vscale x 8 x i16> poison, i16 5, i32 0 946 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 947 %vc = icmp ugt <vscale x 8 x i16> %va, %splat 948 ret <vscale x 8 x i1> %vc 949} 950 951define <vscale x 8 x i1> @icmp_uge_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) { 952; CHECK-LABEL: icmp_uge_vv_nxv8i16: 953; CHECK: # %bb.0: 954; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma 955; CHECK-NEXT: vmsleu.vv v0, v10, v8 956; CHECK-NEXT: ret 957 %vc = icmp uge <vscale x 8 x i16> %va, %vb 958 ret <vscale x 8 x i1> %vc 959} 960 961define <vscale x 8 x i1> @icmp_uge_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) { 962; CHECK-LABEL: icmp_uge_vx_nxv8i16: 963; CHECK: # %bb.0: 964; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma 965; CHECK-NEXT: vmv.v.x v10, a0 966; CHECK-NEXT: vmsleu.vv v0, v10, v8 967; CHECK-NEXT: ret 968 %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0 969 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 970 %vc = icmp uge <vscale x 8 x i16> %va, %splat 971 ret <vscale x 8 x i1> %vc 972} 973 974define <vscale x 8 x i1> @icmp_uge_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) { 975; CHECK-LABEL: icmp_uge_xv_nxv8i16: 976; CHECK: # %bb.0: 977; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma 978; CHECK-NEXT: vmsleu.vx v0, v8, a0 979; CHECK-NEXT: ret 980 %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0 981 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 982 %vc = icmp uge <vscale x 8 x i16> %splat, %va 983 ret <vscale x 8 x i1> %vc 984} 985 986define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_0(<vscale x 8 x i16> %va) { 987; CHECK-LABEL: icmp_uge_vi_nxv8i16_0: 988; CHECK: # %bb.0: 989; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma 990; CHECK-NEXT: vmv.v.i v10, -16 991; CHECK-NEXT: vmsleu.vv v0, v10, v8 992; CHECK-NEXT: ret 993 %head = insertelement <vscale x 8 x i16> poison, i16 -16, i32 0 994 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 995 %vc = icmp uge <vscale x 8 x i16> %va, %splat 996 ret <vscale x 8 x i1> %vc 997} 998 999define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_1(<vscale x 8 x i16> %va) { 1000; CHECK-LABEL: icmp_uge_vi_nxv8i16_1: 1001; CHECK: # %bb.0: 1002; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma 1003; CHECK-NEXT: vmsgtu.vi v0, v8, 14 1004; CHECK-NEXT: ret 1005 %head = insertelement <vscale x 8 x i16> poison, i16 15, i32 0 1006 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 1007 %vc = icmp uge <vscale x 8 x i16> %va, %splat 1008 ret <vscale x 8 x i1> %vc 1009} 1010 1011define <vscale x 8 x i1> @icmp_uge_iv_nxv8i16_1(<vscale x 8 x i16> %va) { 1012; CHECK-LABEL: icmp_uge_iv_nxv8i16_1: 1013; CHECK: # %bb.0: 1014; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma 1015; CHECK-NEXT: vmsleu.vi v0, v8, 15 1016; CHECK-NEXT: ret 1017 %head = insertelement <vscale x 8 x i16> poison, i16 15, i32 0 1018 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 1019 %vc = icmp uge <vscale x 8 x i16> %splat, %va 1020 ret <vscale x 8 x i1> %vc 1021} 1022 1023define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_2(<vscale x 8 x i16> %va) { 1024; CHECK-LABEL: icmp_uge_vi_nxv8i16_2: 1025; CHECK: # %bb.0: 1026; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma 1027; CHECK-NEXT: vmset.m v0 1028; CHECK-NEXT: ret 1029 %head = insertelement <vscale x 8 x i16> poison, i16 0, i32 0 1030 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 1031 %vc = icmp uge <vscale x 8 x i16> %va, %splat 1032 ret <vscale x 8 x i1> %vc 1033} 1034 1035define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_3(<vscale x 8 x i16> %va) { 1036; CHECK-LABEL: icmp_uge_vi_nxv8i16_3: 1037; CHECK: # %bb.0: 1038; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma 1039; CHECK-NEXT: vmsgtu.vi v0, v8, 0 1040; CHECK-NEXT: ret 1041 %head = insertelement <vscale x 8 x i16> poison, i16 1, i32 0 1042 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 1043 %vc = icmp uge <vscale x 8 x i16> %va, %splat 1044 ret <vscale x 8 x i1> %vc 1045} 1046 1047define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_4(<vscale x 8 x i16> %va) { 1048; CHECK-LABEL: icmp_uge_vi_nxv8i16_4: 1049; CHECK: # %bb.0: 1050; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma 1051; CHECK-NEXT: vmsgtu.vi v0, v8, -16 1052; CHECK-NEXT: ret 1053 %head = insertelement <vscale x 8 x i16> poison, i16 -15, i32 0 1054 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 1055 %vc = icmp uge <vscale x 8 x i16> %va, %splat 1056 ret <vscale x 8 x i1> %vc 1057} 1058 1059define <vscale x 8 x i1> @icmp_uge_vi_nxv8i16_5(<vscale x 8 x i16> %va) { 1060; CHECK-LABEL: icmp_uge_vi_nxv8i16_5: 1061; CHECK: # %bb.0: 1062; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma 1063; CHECK-NEXT: vmsgtu.vi v0, v8, 15 1064; CHECK-NEXT: ret 1065 %head = insertelement <vscale x 8 x i16> poison, i16 16, i32 0 1066 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 1067 %vc = icmp uge <vscale x 8 x i16> %va, %splat 1068 ret <vscale x 8 x i1> %vc 1069} 1070 1071define <vscale x 8 x i1> @icmp_ult_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) { 1072; CHECK-LABEL: icmp_ult_vv_nxv8i16: 1073; CHECK: # %bb.0: 1074; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma 1075; CHECK-NEXT: vmsltu.vv v0, v8, v10 1076; CHECK-NEXT: ret 1077 %vc = icmp ult <vscale x 8 x i16> %va, %vb 1078 ret <vscale x 8 x i1> %vc 1079} 1080 1081define <vscale x 8 x i1> @icmp_ult_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) { 1082; CHECK-LABEL: icmp_ult_vx_nxv8i16: 1083; CHECK: # %bb.0: 1084; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma 1085; CHECK-NEXT: vmsltu.vx v0, v8, a0 1086; CHECK-NEXT: ret 1087 %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0 1088 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 1089 %vc = icmp ult <vscale x 8 x i16> %va, %splat 1090 ret <vscale x 8 x i1> %vc 1091} 1092 1093define <vscale x 8 x i1> @icmp_ult_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) { 1094; CHECK-LABEL: icmp_ult_xv_nxv8i16: 1095; CHECK: # %bb.0: 1096; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma 1097; CHECK-NEXT: vmsgtu.vx v0, v8, a0 1098; CHECK-NEXT: ret 1099 %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0 1100 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 1101 %vc = icmp ult <vscale x 8 x i16> %splat, %va 1102 ret <vscale x 8 x i1> %vc 1103} 1104 1105define <vscale x 8 x i1> @icmp_ult_vi_nxv8i16_0(<vscale x 8 x i16> %va) { 1106; CHECK-LABEL: icmp_ult_vi_nxv8i16_0: 1107; CHECK: # %bb.0: 1108; CHECK-NEXT: li a0, -16 1109; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma 1110; CHECK-NEXT: vmsltu.vx v0, v8, a0 1111; CHECK-NEXT: ret 1112 %head = insertelement <vscale x 8 x i16> poison, i16 -16, i32 0 1113 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 1114 %vc = icmp ult <vscale x 8 x i16> %va, %splat 1115 ret <vscale x 8 x i1> %vc 1116} 1117 1118define <vscale x 8 x i1> @icmp_ult_vi_nxv8i16_1(<vscale x 8 x i16> %va) { 1119; CHECK-LABEL: icmp_ult_vi_nxv8i16_1: 1120; CHECK: # %bb.0: 1121; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma 1122; CHECK-NEXT: vmsleu.vi v0, v8, -16 1123; CHECK-NEXT: ret 1124 %head = insertelement <vscale x 8 x i16> poison, i16 -15, i32 0 1125 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 1126 %vc = icmp ult <vscale x 8 x i16> %va, %splat 1127 ret <vscale x 8 x i1> %vc 1128} 1129 1130define <vscale x 8 x i1> @icmp_ult_iv_nxv8i16_1(<vscale x 8 x i16> %va) { 1131; CHECK-LABEL: icmp_ult_iv_nxv8i16_1: 1132; CHECK: # %bb.0: 1133; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma 1134; CHECK-NEXT: vmsgtu.vi v0, v8, -15 1135; CHECK-NEXT: ret 1136 %head = insertelement <vscale x 8 x i16> poison, i16 -15, i32 0 1137 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 1138 %vc = icmp ult <vscale x 8 x i16> %splat, %va 1139 ret <vscale x 8 x i1> %vc 1140} 1141 1142define <vscale x 8 x i1> @icmp_ult_vi_nxv8i16_2(<vscale x 8 x i16> %va) { 1143; CHECK-LABEL: icmp_ult_vi_nxv8i16_2: 1144; CHECK: # %bb.0: 1145; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma 1146; CHECK-NEXT: vmclr.m v0 1147; CHECK-NEXT: ret 1148 %head = insertelement <vscale x 8 x i16> poison, i16 0, i32 0 1149 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 1150 %vc = icmp ult <vscale x 8 x i16> %va, %splat 1151 ret <vscale x 8 x i1> %vc 1152} 1153 1154define <vscale x 8 x i1> @icmp_ult_vi_nxv8i16_3(<vscale x 8 x i16> %va) { 1155; CHECK-LABEL: icmp_ult_vi_nxv8i16_3: 1156; CHECK: # %bb.0: 1157; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma 1158; CHECK-NEXT: vmseq.vi v0, v8, 0 1159; CHECK-NEXT: ret 1160 %head = insertelement <vscale x 8 x i16> poison, i16 1, i32 0 1161 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 1162 %vc = icmp ult <vscale x 8 x i16> %va, %splat 1163 ret <vscale x 8 x i1> %vc 1164} 1165 1166define <vscale x 8 x i1> @icmp_ult_vi_nxv8i16_4(<vscale x 8 x i16> %va) { 1167; CHECK-LABEL: icmp_ult_vi_nxv8i16_4: 1168; CHECK: # %bb.0: 1169; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma 1170; CHECK-NEXT: vmsleu.vi v0, v8, 15 1171; CHECK-NEXT: ret 1172 %head = insertelement <vscale x 8 x i16> poison, i16 16, i32 0 1173 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 1174 %vc = icmp ult <vscale x 8 x i16> %va, %splat 1175 ret <vscale x 8 x i1> %vc 1176} 1177 1178define <vscale x 8 x i1> @icmp_ule_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) { 1179; CHECK-LABEL: icmp_ule_vv_nxv8i16: 1180; CHECK: # %bb.0: 1181; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma 1182; CHECK-NEXT: vmsleu.vv v0, v8, v10 1183; CHECK-NEXT: ret 1184 %vc = icmp ule <vscale x 8 x i16> %va, %vb 1185 ret <vscale x 8 x i1> %vc 1186} 1187 1188define <vscale x 8 x i1> @icmp_ule_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) { 1189; CHECK-LABEL: icmp_ule_vx_nxv8i16: 1190; CHECK: # %bb.0: 1191; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma 1192; CHECK-NEXT: vmsleu.vx v0, v8, a0 1193; CHECK-NEXT: ret 1194 %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0 1195 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 1196 %vc = icmp ule <vscale x 8 x i16> %va, %splat 1197 ret <vscale x 8 x i1> %vc 1198} 1199 1200define <vscale x 8 x i1> @icmp_ule_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) { 1201; CHECK-LABEL: icmp_ule_xv_nxv8i16: 1202; CHECK: # %bb.0: 1203; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma 1204; CHECK-NEXT: vmv.v.x v10, a0 1205; CHECK-NEXT: vmsleu.vv v0, v10, v8 1206; CHECK-NEXT: ret 1207 %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0 1208 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 1209 %vc = icmp ule <vscale x 8 x i16> %splat, %va 1210 ret <vscale x 8 x i1> %vc 1211} 1212 1213define <vscale x 8 x i1> @icmp_ule_vi_nxv8i16_0(<vscale x 8 x i16> %va) { 1214; CHECK-LABEL: icmp_ule_vi_nxv8i16_0: 1215; CHECK: # %bb.0: 1216; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma 1217; CHECK-NEXT: vmsleu.vi v0, v8, 5 1218; CHECK-NEXT: ret 1219 %head = insertelement <vscale x 8 x i16> poison, i16 5, i32 0 1220 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 1221 %vc = icmp ule <vscale x 8 x i16> %va, %splat 1222 ret <vscale x 8 x i1> %vc 1223} 1224 1225define <vscale x 8 x i1> @icmp_sgt_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) { 1226; CHECK-LABEL: icmp_sgt_vv_nxv8i16: 1227; CHECK: # %bb.0: 1228; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma 1229; CHECK-NEXT: vmslt.vv v0, v10, v8 1230; CHECK-NEXT: ret 1231 %vc = icmp sgt <vscale x 8 x i16> %va, %vb 1232 ret <vscale x 8 x i1> %vc 1233} 1234 1235define <vscale x 8 x i1> @icmp_sgt_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) { 1236; CHECK-LABEL: icmp_sgt_vx_nxv8i16: 1237; CHECK: # %bb.0: 1238; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma 1239; CHECK-NEXT: vmsgt.vx v0, v8, a0 1240; CHECK-NEXT: ret 1241 %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0 1242 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 1243 %vc = icmp sgt <vscale x 8 x i16> %va, %splat 1244 ret <vscale x 8 x i1> %vc 1245} 1246 1247define <vscale x 8 x i1> @icmp_sgt_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) { 1248; CHECK-LABEL: icmp_sgt_xv_nxv8i16: 1249; CHECK: # %bb.0: 1250; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma 1251; CHECK-NEXT: vmslt.vx v0, v8, a0 1252; CHECK-NEXT: ret 1253 %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0 1254 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 1255 %vc = icmp sgt <vscale x 8 x i16> %splat, %va 1256 ret <vscale x 8 x i1> %vc 1257} 1258 1259define <vscale x 8 x i1> @icmp_sgt_vi_nxv8i16_0(<vscale x 8 x i16> %va) { 1260; CHECK-LABEL: icmp_sgt_vi_nxv8i16_0: 1261; CHECK: # %bb.0: 1262; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma 1263; CHECK-NEXT: vmsgt.vi v0, v8, 5 1264; CHECK-NEXT: ret 1265 %head = insertelement <vscale x 8 x i16> poison, i16 5, i32 0 1266 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 1267 %vc = icmp sgt <vscale x 8 x i16> %va, %splat 1268 ret <vscale x 8 x i1> %vc 1269} 1270 1271define <vscale x 8 x i1> @icmp_sge_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) { 1272; CHECK-LABEL: icmp_sge_vv_nxv8i16: 1273; CHECK: # %bb.0: 1274; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma 1275; CHECK-NEXT: vmsle.vv v0, v10, v8 1276; CHECK-NEXT: ret 1277 %vc = icmp sge <vscale x 8 x i16> %va, %vb 1278 ret <vscale x 8 x i1> %vc 1279} 1280 1281define <vscale x 8 x i1> @icmp_sge_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) { 1282; CHECK-LABEL: icmp_sge_vx_nxv8i16: 1283; CHECK: # %bb.0: 1284; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma 1285; CHECK-NEXT: vmv.v.x v10, a0 1286; CHECK-NEXT: vmsle.vv v0, v10, v8 1287; CHECK-NEXT: ret 1288 %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0 1289 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 1290 %vc = icmp sge <vscale x 8 x i16> %va, %splat 1291 ret <vscale x 8 x i1> %vc 1292} 1293 1294define <vscale x 8 x i1> @icmp_sge_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) { 1295; CHECK-LABEL: icmp_sge_xv_nxv8i16: 1296; CHECK: # %bb.0: 1297; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma 1298; CHECK-NEXT: vmsle.vx v0, v8, a0 1299; CHECK-NEXT: ret 1300 %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0 1301 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 1302 %vc = icmp sge <vscale x 8 x i16> %splat, %va 1303 ret <vscale x 8 x i1> %vc 1304} 1305 1306define <vscale x 8 x i1> @icmp_sge_vi_nxv8i16_0(<vscale x 8 x i16> %va) { 1307; CHECK-LABEL: icmp_sge_vi_nxv8i16_0: 1308; CHECK: # %bb.0: 1309; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma 1310; CHECK-NEXT: vmv.v.i v10, -16 1311; CHECK-NEXT: vmsle.vv v0, v10, v8 1312; CHECK-NEXT: ret 1313 %head = insertelement <vscale x 8 x i16> poison, i16 -16, i32 0 1314 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 1315 %vc = icmp sge <vscale x 8 x i16> %va, %splat 1316 ret <vscale x 8 x i1> %vc 1317} 1318 1319define <vscale x 8 x i1> @icmp_sge_vi_nxv8i16_1(<vscale x 8 x i16> %va) { 1320; CHECK-LABEL: icmp_sge_vi_nxv8i16_1: 1321; CHECK: # %bb.0: 1322; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma 1323; CHECK-NEXT: vmsgt.vi v0, v8, -16 1324; CHECK-NEXT: ret 1325 %head = insertelement <vscale x 8 x i16> poison, i16 -15, i32 0 1326 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 1327 %vc = icmp sge <vscale x 8 x i16> %va, %splat 1328 ret <vscale x 8 x i1> %vc 1329} 1330 1331define <vscale x 8 x i1> @icmp_sge_iv_nxv8i16_1(<vscale x 8 x i16> %va) { 1332; CHECK-LABEL: icmp_sge_iv_nxv8i16_1: 1333; CHECK: # %bb.0: 1334; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma 1335; CHECK-NEXT: vmsle.vi v0, v8, -15 1336; CHECK-NEXT: ret 1337 %head = insertelement <vscale x 8 x i16> poison, i16 -15, i32 0 1338 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 1339 %vc = icmp sge <vscale x 8 x i16> %splat, %va 1340 ret <vscale x 8 x i1> %vc 1341} 1342 1343define <vscale x 8 x i1> @icmp_sge_vi_nxv8i16_2(<vscale x 8 x i16> %va) { 1344; CHECK-LABEL: icmp_sge_vi_nxv8i16_2: 1345; CHECK: # %bb.0: 1346; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma 1347; CHECK-NEXT: vmsgt.vi v0, v8, -1 1348; CHECK-NEXT: ret 1349 %head = insertelement <vscale x 8 x i16> poison, i16 0, i32 0 1350 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 1351 %vc = icmp sge <vscale x 8 x i16> %va, %splat 1352 ret <vscale x 8 x i1> %vc 1353} 1354 1355define <vscale x 8 x i1> @icmp_sge_vi_nxv8i16_3(<vscale x 8 x i16> %va) { 1356; CHECK-LABEL: icmp_sge_vi_nxv8i16_3: 1357; CHECK: # %bb.0: 1358; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma 1359; CHECK-NEXT: vmsgt.vi v0, v8, 15 1360; CHECK-NEXT: ret 1361 %head = insertelement <vscale x 8 x i16> poison, i16 16, i32 0 1362 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 1363 %vc = icmp sge <vscale x 8 x i16> %va, %splat 1364 ret <vscale x 8 x i1> %vc 1365} 1366 1367define <vscale x 8 x i1> @icmp_slt_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) { 1368; CHECK-LABEL: icmp_slt_vv_nxv8i16: 1369; CHECK: # %bb.0: 1370; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma 1371; CHECK-NEXT: vmslt.vv v0, v8, v10 1372; CHECK-NEXT: ret 1373 %vc = icmp slt <vscale x 8 x i16> %va, %vb 1374 ret <vscale x 8 x i1> %vc 1375} 1376 1377define <vscale x 8 x i1> @icmp_slt_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) { 1378; CHECK-LABEL: icmp_slt_vx_nxv8i16: 1379; CHECK: # %bb.0: 1380; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma 1381; CHECK-NEXT: vmslt.vx v0, v8, a0 1382; CHECK-NEXT: ret 1383 %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0 1384 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 1385 %vc = icmp slt <vscale x 8 x i16> %va, %splat 1386 ret <vscale x 8 x i1> %vc 1387} 1388 1389define <vscale x 8 x i1> @icmp_slt_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) { 1390; CHECK-LABEL: icmp_slt_xv_nxv8i16: 1391; CHECK: # %bb.0: 1392; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma 1393; CHECK-NEXT: vmsgt.vx v0, v8, a0 1394; CHECK-NEXT: ret 1395 %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0 1396 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 1397 %vc = icmp slt <vscale x 8 x i16> %splat, %va 1398 ret <vscale x 8 x i1> %vc 1399} 1400 1401define <vscale x 8 x i1> @icmp_slt_vi_nxv8i16_0(<vscale x 8 x i16> %va) { 1402; CHECK-LABEL: icmp_slt_vi_nxv8i16_0: 1403; CHECK: # %bb.0: 1404; CHECK-NEXT: li a0, -16 1405; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma 1406; CHECK-NEXT: vmslt.vx v0, v8, a0 1407; CHECK-NEXT: ret 1408 %head = insertelement <vscale x 8 x i16> poison, i16 -16, i32 0 1409 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 1410 %vc = icmp slt <vscale x 8 x i16> %va, %splat 1411 ret <vscale x 8 x i1> %vc 1412} 1413 1414define <vscale x 8 x i1> @icmp_slt_vi_nxv8i16_1(<vscale x 8 x i16> %va) { 1415; CHECK-LABEL: icmp_slt_vi_nxv8i16_1: 1416; CHECK: # %bb.0: 1417; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma 1418; CHECK-NEXT: vmsle.vi v0, v8, -16 1419; CHECK-NEXT: ret 1420 %head = insertelement <vscale x 8 x i16> poison, i16 -15, i32 0 1421 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 1422 %vc = icmp slt <vscale x 8 x i16> %va, %splat 1423 ret <vscale x 8 x i1> %vc 1424} 1425 1426define <vscale x 8 x i1> @icmp_slt_iv_nxv8i16_1(<vscale x 8 x i16> %va) { 1427; CHECK-LABEL: icmp_slt_iv_nxv8i16_1: 1428; CHECK: # %bb.0: 1429; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma 1430; CHECK-NEXT: vmsgt.vi v0, v8, -15 1431; CHECK-NEXT: ret 1432 %head = insertelement <vscale x 8 x i16> poison, i16 -15, i32 0 1433 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 1434 %vc = icmp slt <vscale x 8 x i16> %splat, %va 1435 ret <vscale x 8 x i1> %vc 1436} 1437 1438define <vscale x 8 x i1> @icmp_slt_vi_nxv8i16_2(<vscale x 8 x i16> %va) { 1439; CHECK-LABEL: icmp_slt_vi_nxv8i16_2: 1440; CHECK: # %bb.0: 1441; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma 1442; CHECK-NEXT: vmslt.vx v0, v8, zero 1443; CHECK-NEXT: ret 1444 %head = insertelement <vscale x 8 x i16> poison, i16 0, i32 0 1445 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 1446 %vc = icmp slt <vscale x 8 x i16> %va, %splat 1447 ret <vscale x 8 x i1> %vc 1448} 1449 1450define <vscale x 8 x i1> @icmp_slt_vi_nxv8i16_3(<vscale x 8 x i16> %va) { 1451; CHECK-LABEL: icmp_slt_vi_nxv8i16_3: 1452; CHECK: # %bb.0: 1453; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma 1454; CHECK-NEXT: vmsle.vi v0, v8, 15 1455; CHECK-NEXT: ret 1456 %head = insertelement <vscale x 8 x i16> poison, i16 16, i32 0 1457 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 1458 %vc = icmp slt <vscale x 8 x i16> %va, %splat 1459 ret <vscale x 8 x i1> %vc 1460} 1461 1462define <vscale x 8 x i1> @icmp_sle_vv_nxv8i16(<vscale x 8 x i16> %va, <vscale x 8 x i16> %vb) { 1463; CHECK-LABEL: icmp_sle_vv_nxv8i16: 1464; CHECK: # %bb.0: 1465; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma 1466; CHECK-NEXT: vmsle.vv v0, v8, v10 1467; CHECK-NEXT: ret 1468 %vc = icmp sle <vscale x 8 x i16> %va, %vb 1469 ret <vscale x 8 x i1> %vc 1470} 1471 1472define <vscale x 8 x i1> @icmp_sle_vx_nxv8i16(<vscale x 8 x i16> %va, i16 %b) { 1473; CHECK-LABEL: icmp_sle_vx_nxv8i16: 1474; CHECK: # %bb.0: 1475; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma 1476; CHECK-NEXT: vmsle.vx v0, v8, a0 1477; CHECK-NEXT: ret 1478 %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0 1479 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 1480 %vc = icmp sle <vscale x 8 x i16> %va, %splat 1481 ret <vscale x 8 x i1> %vc 1482} 1483 1484define <vscale x 8 x i1> @icmp_sle_xv_nxv8i16(<vscale x 8 x i16> %va, i16 %b) { 1485; CHECK-LABEL: icmp_sle_xv_nxv8i16: 1486; CHECK: # %bb.0: 1487; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma 1488; CHECK-NEXT: vmv.v.x v10, a0 1489; CHECK-NEXT: vmsle.vv v0, v10, v8 1490; CHECK-NEXT: ret 1491 %head = insertelement <vscale x 8 x i16> poison, i16 %b, i32 0 1492 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 1493 %vc = icmp sle <vscale x 8 x i16> %splat, %va 1494 ret <vscale x 8 x i1> %vc 1495} 1496 1497define <vscale x 8 x i1> @icmp_sle_vi_nxv8i16_0(<vscale x 8 x i16> %va) { 1498; CHECK-LABEL: icmp_sle_vi_nxv8i16_0: 1499; CHECK: # %bb.0: 1500; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma 1501; CHECK-NEXT: vmsle.vi v0, v8, 5 1502; CHECK-NEXT: ret 1503 %head = insertelement <vscale x 8 x i16> poison, i16 5, i32 0 1504 %splat = shufflevector <vscale x 8 x i16> %head, <vscale x 8 x i16> poison, <vscale x 8 x i32> zeroinitializer 1505 %vc = icmp sle <vscale x 8 x i16> %va, %splat 1506 ret <vscale x 8 x i1> %vc 1507} 1508 1509define <vscale x 8 x i1> @icmp_eq_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) { 1510; CHECK-LABEL: icmp_eq_vv_nxv8i32: 1511; CHECK: # %bb.0: 1512; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma 1513; CHECK-NEXT: vmseq.vv v0, v8, v12 1514; CHECK-NEXT: ret 1515 %vc = icmp eq <vscale x 8 x i32> %va, %vb 1516 ret <vscale x 8 x i1> %vc 1517} 1518 1519define <vscale x 8 x i1> @icmp_eq_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) { 1520; CHECK-LABEL: icmp_eq_vx_nxv8i32: 1521; CHECK: # %bb.0: 1522; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma 1523; CHECK-NEXT: vmseq.vx v0, v8, a0 1524; CHECK-NEXT: ret 1525 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0 1526 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 1527 %vc = icmp eq <vscale x 8 x i32> %va, %splat 1528 ret <vscale x 8 x i1> %vc 1529} 1530 1531define <vscale x 8 x i1> @icmp_eq_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) { 1532; CHECK-LABEL: icmp_eq_xv_nxv8i32: 1533; CHECK: # %bb.0: 1534; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma 1535; CHECK-NEXT: vmseq.vx v0, v8, a0 1536; CHECK-NEXT: ret 1537 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0 1538 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 1539 %vc = icmp eq <vscale x 8 x i32> %splat, %va 1540 ret <vscale x 8 x i1> %vc 1541} 1542 1543define <vscale x 8 x i1> @icmp_eq_vi_nxv8i32_0(<vscale x 8 x i32> %va) { 1544; CHECK-LABEL: icmp_eq_vi_nxv8i32_0: 1545; CHECK: # %bb.0: 1546; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma 1547; CHECK-NEXT: vmseq.vi v0, v8, 0 1548; CHECK-NEXT: ret 1549 %head = insertelement <vscale x 8 x i32> poison, i32 0, i32 0 1550 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 1551 %vc = icmp eq <vscale x 8 x i32> %va, %splat 1552 ret <vscale x 8 x i1> %vc 1553} 1554 1555define <vscale x 8 x i1> @icmp_eq_vi_nxv8i32_1(<vscale x 8 x i32> %va) { 1556; CHECK-LABEL: icmp_eq_vi_nxv8i32_1: 1557; CHECK: # %bb.0: 1558; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma 1559; CHECK-NEXT: vmseq.vi v0, v8, 5 1560; CHECK-NEXT: ret 1561 %head = insertelement <vscale x 8 x i32> poison, i32 5, i32 0 1562 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 1563 %vc = icmp eq <vscale x 8 x i32> %va, %splat 1564 ret <vscale x 8 x i1> %vc 1565} 1566 1567define <vscale x 8 x i1> @icmp_eq_iv_nxv8i32_1(<vscale x 8 x i32> %va) { 1568; CHECK-LABEL: icmp_eq_iv_nxv8i32_1: 1569; CHECK: # %bb.0: 1570; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma 1571; CHECK-NEXT: vmseq.vi v0, v8, 5 1572; CHECK-NEXT: ret 1573 %head = insertelement <vscale x 8 x i32> poison, i32 5, i32 0 1574 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 1575 %vc = icmp eq <vscale x 8 x i32> %splat, %va 1576 ret <vscale x 8 x i1> %vc 1577} 1578 1579define <vscale x 8 x i1> @icmp_ne_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) { 1580; CHECK-LABEL: icmp_ne_vv_nxv8i32: 1581; CHECK: # %bb.0: 1582; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma 1583; CHECK-NEXT: vmsne.vv v0, v8, v12 1584; CHECK-NEXT: ret 1585 %vc = icmp ne <vscale x 8 x i32> %va, %vb 1586 ret <vscale x 8 x i1> %vc 1587} 1588 1589define <vscale x 8 x i1> @icmp_ne_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) { 1590; CHECK-LABEL: icmp_ne_vx_nxv8i32: 1591; CHECK: # %bb.0: 1592; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma 1593; CHECK-NEXT: vmsne.vx v0, v8, a0 1594; CHECK-NEXT: ret 1595 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0 1596 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 1597 %vc = icmp ne <vscale x 8 x i32> %va, %splat 1598 ret <vscale x 8 x i1> %vc 1599} 1600 1601define <vscale x 8 x i1> @icmp_ne_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) { 1602; CHECK-LABEL: icmp_ne_xv_nxv8i32: 1603; CHECK: # %bb.0: 1604; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma 1605; CHECK-NEXT: vmsne.vx v0, v8, a0 1606; CHECK-NEXT: ret 1607 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0 1608 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 1609 %vc = icmp ne <vscale x 8 x i32> %splat, %va 1610 ret <vscale x 8 x i1> %vc 1611} 1612 1613define <vscale x 8 x i1> @icmp_ne_vi_nxv8i32_0(<vscale x 8 x i32> %va) { 1614; CHECK-LABEL: icmp_ne_vi_nxv8i32_0: 1615; CHECK: # %bb.0: 1616; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma 1617; CHECK-NEXT: vmsne.vi v0, v8, 5 1618; CHECK-NEXT: ret 1619 %head = insertelement <vscale x 8 x i32> poison, i32 5, i32 0 1620 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 1621 %vc = icmp ne <vscale x 8 x i32> %va, %splat 1622 ret <vscale x 8 x i1> %vc 1623} 1624 1625define <vscale x 8 x i1> @icmp_ugt_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) { 1626; CHECK-LABEL: icmp_ugt_vv_nxv8i32: 1627; CHECK: # %bb.0: 1628; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma 1629; CHECK-NEXT: vmsltu.vv v0, v12, v8 1630; CHECK-NEXT: ret 1631 %vc = icmp ugt <vscale x 8 x i32> %va, %vb 1632 ret <vscale x 8 x i1> %vc 1633} 1634 1635define <vscale x 8 x i1> @icmp_ugt_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) { 1636; CHECK-LABEL: icmp_ugt_vx_nxv8i32: 1637; CHECK: # %bb.0: 1638; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma 1639; CHECK-NEXT: vmsgtu.vx v0, v8, a0 1640; CHECK-NEXT: ret 1641 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0 1642 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 1643 %vc = icmp ugt <vscale x 8 x i32> %va, %splat 1644 ret <vscale x 8 x i1> %vc 1645} 1646 1647define <vscale x 8 x i1> @icmp_ugt_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) { 1648; CHECK-LABEL: icmp_ugt_xv_nxv8i32: 1649; CHECK: # %bb.0: 1650; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma 1651; CHECK-NEXT: vmsltu.vx v0, v8, a0 1652; CHECK-NEXT: ret 1653 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0 1654 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 1655 %vc = icmp ugt <vscale x 8 x i32> %splat, %va 1656 ret <vscale x 8 x i1> %vc 1657} 1658 1659define <vscale x 8 x i1> @icmp_ugt_vi_nxv8i32_0(<vscale x 8 x i32> %va) { 1660; CHECK-LABEL: icmp_ugt_vi_nxv8i32_0: 1661; CHECK: # %bb.0: 1662; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma 1663; CHECK-NEXT: vmsgtu.vi v0, v8, 5 1664; CHECK-NEXT: ret 1665 %head = insertelement <vscale x 8 x i32> poison, i32 5, i32 0 1666 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 1667 %vc = icmp ugt <vscale x 8 x i32> %va, %splat 1668 ret <vscale x 8 x i1> %vc 1669} 1670 1671define <vscale x 8 x i1> @icmp_uge_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) { 1672; CHECK-LABEL: icmp_uge_vv_nxv8i32: 1673; CHECK: # %bb.0: 1674; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma 1675; CHECK-NEXT: vmsleu.vv v0, v12, v8 1676; CHECK-NEXT: ret 1677 %vc = icmp uge <vscale x 8 x i32> %va, %vb 1678 ret <vscale x 8 x i1> %vc 1679} 1680 1681define <vscale x 8 x i1> @icmp_uge_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) { 1682; CHECK-LABEL: icmp_uge_vx_nxv8i32: 1683; CHECK: # %bb.0: 1684; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma 1685; CHECK-NEXT: vmv.v.x v12, a0 1686; CHECK-NEXT: vmsleu.vv v0, v12, v8 1687; CHECK-NEXT: ret 1688 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0 1689 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 1690 %vc = icmp uge <vscale x 8 x i32> %va, %splat 1691 ret <vscale x 8 x i1> %vc 1692} 1693 1694define <vscale x 8 x i1> @icmp_uge_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) { 1695; CHECK-LABEL: icmp_uge_xv_nxv8i32: 1696; CHECK: # %bb.0: 1697; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma 1698; CHECK-NEXT: vmsleu.vx v0, v8, a0 1699; CHECK-NEXT: ret 1700 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0 1701 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 1702 %vc = icmp uge <vscale x 8 x i32> %splat, %va 1703 ret <vscale x 8 x i1> %vc 1704} 1705 1706define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_0(<vscale x 8 x i32> %va) { 1707; CHECK-LABEL: icmp_uge_vi_nxv8i32_0: 1708; CHECK: # %bb.0: 1709; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma 1710; CHECK-NEXT: vmv.v.i v12, -16 1711; CHECK-NEXT: vmsleu.vv v0, v12, v8 1712; CHECK-NEXT: ret 1713 %head = insertelement <vscale x 8 x i32> poison, i32 -16, i32 0 1714 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 1715 %vc = icmp uge <vscale x 8 x i32> %va, %splat 1716 ret <vscale x 8 x i1> %vc 1717} 1718 1719define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_1(<vscale x 8 x i32> %va) { 1720; CHECK-LABEL: icmp_uge_vi_nxv8i32_1: 1721; CHECK: # %bb.0: 1722; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma 1723; CHECK-NEXT: vmsgtu.vi v0, v8, 14 1724; CHECK-NEXT: ret 1725 %head = insertelement <vscale x 8 x i32> poison, i32 15, i32 0 1726 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 1727 %vc = icmp uge <vscale x 8 x i32> %va, %splat 1728 ret <vscale x 8 x i1> %vc 1729} 1730 1731define <vscale x 8 x i1> @icmp_uge_iv_nxv8i32_1(<vscale x 8 x i32> %va) { 1732; CHECK-LABEL: icmp_uge_iv_nxv8i32_1: 1733; CHECK: # %bb.0: 1734; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma 1735; CHECK-NEXT: vmsleu.vi v0, v8, 15 1736; CHECK-NEXT: ret 1737 %head = insertelement <vscale x 8 x i32> poison, i32 15, i32 0 1738 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 1739 %vc = icmp uge <vscale x 8 x i32> %splat, %va 1740 ret <vscale x 8 x i1> %vc 1741} 1742 1743define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_2(<vscale x 8 x i32> %va) { 1744; CHECK-LABEL: icmp_uge_vi_nxv8i32_2: 1745; CHECK: # %bb.0: 1746; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma 1747; CHECK-NEXT: vmset.m v0 1748; CHECK-NEXT: ret 1749 %head = insertelement <vscale x 8 x i32> poison, i32 0, i32 0 1750 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 1751 %vc = icmp uge <vscale x 8 x i32> %va, %splat 1752 ret <vscale x 8 x i1> %vc 1753} 1754 1755define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_3(<vscale x 8 x i32> %va) { 1756; CHECK-LABEL: icmp_uge_vi_nxv8i32_3: 1757; CHECK: # %bb.0: 1758; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma 1759; CHECK-NEXT: vmsgtu.vi v0, v8, 0 1760; CHECK-NEXT: ret 1761 %head = insertelement <vscale x 8 x i32> poison, i32 1, i32 0 1762 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 1763 %vc = icmp uge <vscale x 8 x i32> %va, %splat 1764 ret <vscale x 8 x i1> %vc 1765} 1766 1767define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_4(<vscale x 8 x i32> %va) { 1768; CHECK-LABEL: icmp_uge_vi_nxv8i32_4: 1769; CHECK: # %bb.0: 1770; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma 1771; CHECK-NEXT: vmsgtu.vi v0, v8, -16 1772; CHECK-NEXT: ret 1773 %head = insertelement <vscale x 8 x i32> poison, i32 -15, i32 0 1774 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 1775 %vc = icmp uge <vscale x 8 x i32> %va, %splat 1776 ret <vscale x 8 x i1> %vc 1777} 1778 1779define <vscale x 8 x i1> @icmp_uge_vi_nxv8i32_5(<vscale x 8 x i32> %va) { 1780; CHECK-LABEL: icmp_uge_vi_nxv8i32_5: 1781; CHECK: # %bb.0: 1782; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma 1783; CHECK-NEXT: vmsgtu.vi v0, v8, 15 1784; CHECK-NEXT: ret 1785 %head = insertelement <vscale x 8 x i32> poison, i32 16, i32 0 1786 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 1787 %vc = icmp uge <vscale x 8 x i32> %va, %splat 1788 ret <vscale x 8 x i1> %vc 1789} 1790 1791define <vscale x 8 x i1> @icmp_ult_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) { 1792; CHECK-LABEL: icmp_ult_vv_nxv8i32: 1793; CHECK: # %bb.0: 1794; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma 1795; CHECK-NEXT: vmsltu.vv v0, v8, v12 1796; CHECK-NEXT: ret 1797 %vc = icmp ult <vscale x 8 x i32> %va, %vb 1798 ret <vscale x 8 x i1> %vc 1799} 1800 1801define <vscale x 8 x i1> @icmp_ult_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) { 1802; CHECK-LABEL: icmp_ult_vx_nxv8i32: 1803; CHECK: # %bb.0: 1804; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma 1805; CHECK-NEXT: vmsltu.vx v0, v8, a0 1806; CHECK-NEXT: ret 1807 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0 1808 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 1809 %vc = icmp ult <vscale x 8 x i32> %va, %splat 1810 ret <vscale x 8 x i1> %vc 1811} 1812 1813define <vscale x 8 x i1> @icmp_ult_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) { 1814; CHECK-LABEL: icmp_ult_xv_nxv8i32: 1815; CHECK: # %bb.0: 1816; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma 1817; CHECK-NEXT: vmsgtu.vx v0, v8, a0 1818; CHECK-NEXT: ret 1819 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0 1820 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 1821 %vc = icmp ult <vscale x 8 x i32> %splat, %va 1822 ret <vscale x 8 x i1> %vc 1823} 1824 1825define <vscale x 8 x i1> @icmp_ult_vi_nxv8i32_0(<vscale x 8 x i32> %va) { 1826; CHECK-LABEL: icmp_ult_vi_nxv8i32_0: 1827; CHECK: # %bb.0: 1828; CHECK-NEXT: li a0, -16 1829; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma 1830; CHECK-NEXT: vmsltu.vx v0, v8, a0 1831; CHECK-NEXT: ret 1832 %head = insertelement <vscale x 8 x i32> poison, i32 -16, i32 0 1833 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 1834 %vc = icmp ult <vscale x 8 x i32> %va, %splat 1835 ret <vscale x 8 x i1> %vc 1836} 1837 1838define <vscale x 8 x i1> @icmp_ult_vi_nxv8i32_1(<vscale x 8 x i32> %va) { 1839; CHECK-LABEL: icmp_ult_vi_nxv8i32_1: 1840; CHECK: # %bb.0: 1841; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma 1842; CHECK-NEXT: vmsleu.vi v0, v8, -16 1843; CHECK-NEXT: ret 1844 %head = insertelement <vscale x 8 x i32> poison, i32 -15, i32 0 1845 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 1846 %vc = icmp ult <vscale x 8 x i32> %va, %splat 1847 ret <vscale x 8 x i1> %vc 1848} 1849 1850define <vscale x 8 x i1> @icmp_ult_iv_nxv8i32_1(<vscale x 8 x i32> %va) { 1851; CHECK-LABEL: icmp_ult_iv_nxv8i32_1: 1852; CHECK: # %bb.0: 1853; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma 1854; CHECK-NEXT: vmsgtu.vi v0, v8, -15 1855; CHECK-NEXT: ret 1856 %head = insertelement <vscale x 8 x i32> poison, i32 -15, i32 0 1857 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 1858 %vc = icmp ult <vscale x 8 x i32> %splat, %va 1859 ret <vscale x 8 x i1> %vc 1860} 1861 1862define <vscale x 8 x i1> @icmp_ult_vi_nxv8i32_2(<vscale x 8 x i32> %va) { 1863; CHECK-LABEL: icmp_ult_vi_nxv8i32_2: 1864; CHECK: # %bb.0: 1865; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma 1866; CHECK-NEXT: vmclr.m v0 1867; CHECK-NEXT: ret 1868 %head = insertelement <vscale x 8 x i32> poison, i32 0, i32 0 1869 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 1870 %vc = icmp ult <vscale x 8 x i32> %va, %splat 1871 ret <vscale x 8 x i1> %vc 1872} 1873 1874define <vscale x 8 x i1> @icmp_ult_vi_nxv8i32_3(<vscale x 8 x i32> %va) { 1875; CHECK-LABEL: icmp_ult_vi_nxv8i32_3: 1876; CHECK: # %bb.0: 1877; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma 1878; CHECK-NEXT: vmseq.vi v0, v8, 0 1879; CHECK-NEXT: ret 1880 %head = insertelement <vscale x 8 x i32> poison, i32 1, i32 0 1881 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 1882 %vc = icmp ult <vscale x 8 x i32> %va, %splat 1883 ret <vscale x 8 x i1> %vc 1884} 1885 1886define <vscale x 8 x i1> @icmp_ult_vi_nxv8i32_4(<vscale x 8 x i32> %va) { 1887; CHECK-LABEL: icmp_ult_vi_nxv8i32_4: 1888; CHECK: # %bb.0: 1889; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma 1890; CHECK-NEXT: vmsleu.vi v0, v8, 15 1891; CHECK-NEXT: ret 1892 %head = insertelement <vscale x 8 x i32> poison, i32 16, i32 0 1893 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 1894 %vc = icmp ult <vscale x 8 x i32> %va, %splat 1895 ret <vscale x 8 x i1> %vc 1896} 1897 1898define <vscale x 8 x i1> @icmp_ule_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) { 1899; CHECK-LABEL: icmp_ule_vv_nxv8i32: 1900; CHECK: # %bb.0: 1901; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma 1902; CHECK-NEXT: vmsleu.vv v0, v8, v12 1903; CHECK-NEXT: ret 1904 %vc = icmp ule <vscale x 8 x i32> %va, %vb 1905 ret <vscale x 8 x i1> %vc 1906} 1907 1908define <vscale x 8 x i1> @icmp_ule_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) { 1909; CHECK-LABEL: icmp_ule_vx_nxv8i32: 1910; CHECK: # %bb.0: 1911; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma 1912; CHECK-NEXT: vmsleu.vx v0, v8, a0 1913; CHECK-NEXT: ret 1914 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0 1915 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 1916 %vc = icmp ule <vscale x 8 x i32> %va, %splat 1917 ret <vscale x 8 x i1> %vc 1918} 1919 1920define <vscale x 8 x i1> @icmp_ule_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) { 1921; CHECK-LABEL: icmp_ule_xv_nxv8i32: 1922; CHECK: # %bb.0: 1923; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma 1924; CHECK-NEXT: vmv.v.x v12, a0 1925; CHECK-NEXT: vmsleu.vv v0, v12, v8 1926; CHECK-NEXT: ret 1927 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0 1928 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 1929 %vc = icmp ule <vscale x 8 x i32> %splat, %va 1930 ret <vscale x 8 x i1> %vc 1931} 1932 1933define <vscale x 8 x i1> @icmp_ule_vi_nxv8i32_0(<vscale x 8 x i32> %va) { 1934; CHECK-LABEL: icmp_ule_vi_nxv8i32_0: 1935; CHECK: # %bb.0: 1936; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma 1937; CHECK-NEXT: vmsleu.vi v0, v8, 5 1938; CHECK-NEXT: ret 1939 %head = insertelement <vscale x 8 x i32> poison, i32 5, i32 0 1940 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 1941 %vc = icmp ule <vscale x 8 x i32> %va, %splat 1942 ret <vscale x 8 x i1> %vc 1943} 1944 1945define <vscale x 8 x i1> @icmp_sgt_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) { 1946; CHECK-LABEL: icmp_sgt_vv_nxv8i32: 1947; CHECK: # %bb.0: 1948; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma 1949; CHECK-NEXT: vmslt.vv v0, v12, v8 1950; CHECK-NEXT: ret 1951 %vc = icmp sgt <vscale x 8 x i32> %va, %vb 1952 ret <vscale x 8 x i1> %vc 1953} 1954 1955define <vscale x 8 x i1> @icmp_sgt_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) { 1956; CHECK-LABEL: icmp_sgt_vx_nxv8i32: 1957; CHECK: # %bb.0: 1958; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma 1959; CHECK-NEXT: vmsgt.vx v0, v8, a0 1960; CHECK-NEXT: ret 1961 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0 1962 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 1963 %vc = icmp sgt <vscale x 8 x i32> %va, %splat 1964 ret <vscale x 8 x i1> %vc 1965} 1966 1967define <vscale x 8 x i1> @icmp_sgt_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) { 1968; CHECK-LABEL: icmp_sgt_xv_nxv8i32: 1969; CHECK: # %bb.0: 1970; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma 1971; CHECK-NEXT: vmslt.vx v0, v8, a0 1972; CHECK-NEXT: ret 1973 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0 1974 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 1975 %vc = icmp sgt <vscale x 8 x i32> %splat, %va 1976 ret <vscale x 8 x i1> %vc 1977} 1978 1979define <vscale x 8 x i1> @icmp_sgt_vi_nxv8i32_0(<vscale x 8 x i32> %va) { 1980; CHECK-LABEL: icmp_sgt_vi_nxv8i32_0: 1981; CHECK: # %bb.0: 1982; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma 1983; CHECK-NEXT: vmsgt.vi v0, v8, 5 1984; CHECK-NEXT: ret 1985 %head = insertelement <vscale x 8 x i32> poison, i32 5, i32 0 1986 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 1987 %vc = icmp sgt <vscale x 8 x i32> %va, %splat 1988 ret <vscale x 8 x i1> %vc 1989} 1990 1991define <vscale x 8 x i1> @icmp_sge_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) { 1992; CHECK-LABEL: icmp_sge_vv_nxv8i32: 1993; CHECK: # %bb.0: 1994; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma 1995; CHECK-NEXT: vmsle.vv v0, v12, v8 1996; CHECK-NEXT: ret 1997 %vc = icmp sge <vscale x 8 x i32> %va, %vb 1998 ret <vscale x 8 x i1> %vc 1999} 2000 2001define <vscale x 8 x i1> @icmp_sge_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) { 2002; CHECK-LABEL: icmp_sge_vx_nxv8i32: 2003; CHECK: # %bb.0: 2004; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma 2005; CHECK-NEXT: vmv.v.x v12, a0 2006; CHECK-NEXT: vmsle.vv v0, v12, v8 2007; CHECK-NEXT: ret 2008 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0 2009 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 2010 %vc = icmp sge <vscale x 8 x i32> %va, %splat 2011 ret <vscale x 8 x i1> %vc 2012} 2013 2014define <vscale x 8 x i1> @icmp_sge_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) { 2015; CHECK-LABEL: icmp_sge_xv_nxv8i32: 2016; CHECK: # %bb.0: 2017; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma 2018; CHECK-NEXT: vmsle.vx v0, v8, a0 2019; CHECK-NEXT: ret 2020 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0 2021 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 2022 %vc = icmp sge <vscale x 8 x i32> %splat, %va 2023 ret <vscale x 8 x i1> %vc 2024} 2025 2026define <vscale x 8 x i1> @icmp_sge_vi_nxv8i32_0(<vscale x 8 x i32> %va) { 2027; CHECK-LABEL: icmp_sge_vi_nxv8i32_0: 2028; CHECK: # %bb.0: 2029; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma 2030; CHECK-NEXT: vmv.v.i v12, -16 2031; CHECK-NEXT: vmsle.vv v0, v12, v8 2032; CHECK-NEXT: ret 2033 %head = insertelement <vscale x 8 x i32> poison, i32 -16, i32 0 2034 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 2035 %vc = icmp sge <vscale x 8 x i32> %va, %splat 2036 ret <vscale x 8 x i1> %vc 2037} 2038 2039define <vscale x 8 x i1> @icmp_sge_vi_nxv8i32_1(<vscale x 8 x i32> %va) { 2040; CHECK-LABEL: icmp_sge_vi_nxv8i32_1: 2041; CHECK: # %bb.0: 2042; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma 2043; CHECK-NEXT: vmsgt.vi v0, v8, -16 2044; CHECK-NEXT: ret 2045 %head = insertelement <vscale x 8 x i32> poison, i32 -15, i32 0 2046 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 2047 %vc = icmp sge <vscale x 8 x i32> %va, %splat 2048 ret <vscale x 8 x i1> %vc 2049} 2050 2051define <vscale x 8 x i1> @icmp_sge_iv_nxv8i32_1(<vscale x 8 x i32> %va) { 2052; CHECK-LABEL: icmp_sge_iv_nxv8i32_1: 2053; CHECK: # %bb.0: 2054; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma 2055; CHECK-NEXT: vmsle.vi v0, v8, -15 2056; CHECK-NEXT: ret 2057 %head = insertelement <vscale x 8 x i32> poison, i32 -15, i32 0 2058 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 2059 %vc = icmp sge <vscale x 8 x i32> %splat, %va 2060 ret <vscale x 8 x i1> %vc 2061} 2062 2063define <vscale x 8 x i1> @icmp_sge_vi_nxv8i32_2(<vscale x 8 x i32> %va) { 2064; CHECK-LABEL: icmp_sge_vi_nxv8i32_2: 2065; CHECK: # %bb.0: 2066; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma 2067; CHECK-NEXT: vmsgt.vi v0, v8, -1 2068; CHECK-NEXT: ret 2069 %head = insertelement <vscale x 8 x i32> poison, i32 0, i32 0 2070 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 2071 %vc = icmp sge <vscale x 8 x i32> %va, %splat 2072 ret <vscale x 8 x i1> %vc 2073} 2074 2075define <vscale x 8 x i1> @icmp_sge_vi_nxv8i32_3(<vscale x 8 x i32> %va) { 2076; CHECK-LABEL: icmp_sge_vi_nxv8i32_3: 2077; CHECK: # %bb.0: 2078; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma 2079; CHECK-NEXT: vmsgt.vi v0, v8, 15 2080; CHECK-NEXT: ret 2081 %head = insertelement <vscale x 8 x i32> poison, i32 16, i32 0 2082 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 2083 %vc = icmp sge <vscale x 8 x i32> %va, %splat 2084 ret <vscale x 8 x i1> %vc 2085} 2086 2087define <vscale x 8 x i1> @icmp_slt_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) { 2088; CHECK-LABEL: icmp_slt_vv_nxv8i32: 2089; CHECK: # %bb.0: 2090; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma 2091; CHECK-NEXT: vmslt.vv v0, v8, v12 2092; CHECK-NEXT: ret 2093 %vc = icmp slt <vscale x 8 x i32> %va, %vb 2094 ret <vscale x 8 x i1> %vc 2095} 2096 2097define <vscale x 8 x i1> @icmp_slt_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) { 2098; CHECK-LABEL: icmp_slt_vx_nxv8i32: 2099; CHECK: # %bb.0: 2100; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma 2101; CHECK-NEXT: vmslt.vx v0, v8, a0 2102; CHECK-NEXT: ret 2103 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0 2104 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 2105 %vc = icmp slt <vscale x 8 x i32> %va, %splat 2106 ret <vscale x 8 x i1> %vc 2107} 2108 2109define <vscale x 8 x i1> @icmp_slt_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) { 2110; CHECK-LABEL: icmp_slt_xv_nxv8i32: 2111; CHECK: # %bb.0: 2112; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma 2113; CHECK-NEXT: vmsgt.vx v0, v8, a0 2114; CHECK-NEXT: ret 2115 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0 2116 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 2117 %vc = icmp slt <vscale x 8 x i32> %splat, %va 2118 ret <vscale x 8 x i1> %vc 2119} 2120 2121define <vscale x 8 x i1> @icmp_slt_vi_nxv8i32_0(<vscale x 8 x i32> %va) { 2122; CHECK-LABEL: icmp_slt_vi_nxv8i32_0: 2123; CHECK: # %bb.0: 2124; CHECK-NEXT: li a0, -16 2125; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma 2126; CHECK-NEXT: vmslt.vx v0, v8, a0 2127; CHECK-NEXT: ret 2128 %head = insertelement <vscale x 8 x i32> poison, i32 -16, i32 0 2129 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 2130 %vc = icmp slt <vscale x 8 x i32> %va, %splat 2131 ret <vscale x 8 x i1> %vc 2132} 2133 2134define <vscale x 8 x i1> @icmp_slt_vi_nxv8i32_1(<vscale x 8 x i32> %va) { 2135; CHECK-LABEL: icmp_slt_vi_nxv8i32_1: 2136; CHECK: # %bb.0: 2137; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma 2138; CHECK-NEXT: vmsle.vi v0, v8, -16 2139; CHECK-NEXT: ret 2140 %head = insertelement <vscale x 8 x i32> poison, i32 -15, i32 0 2141 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 2142 %vc = icmp slt <vscale x 8 x i32> %va, %splat 2143 ret <vscale x 8 x i1> %vc 2144} 2145 2146define <vscale x 8 x i1> @icmp_slt_iv_nxv8i32_1(<vscale x 8 x i32> %va) { 2147; CHECK-LABEL: icmp_slt_iv_nxv8i32_1: 2148; CHECK: # %bb.0: 2149; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma 2150; CHECK-NEXT: vmsgt.vi v0, v8, -15 2151; CHECK-NEXT: ret 2152 %head = insertelement <vscale x 8 x i32> poison, i32 -15, i32 0 2153 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 2154 %vc = icmp slt <vscale x 8 x i32> %splat, %va 2155 ret <vscale x 8 x i1> %vc 2156} 2157 2158define <vscale x 8 x i1> @icmp_slt_vi_nxv8i32_2(<vscale x 8 x i32> %va) { 2159; CHECK-LABEL: icmp_slt_vi_nxv8i32_2: 2160; CHECK: # %bb.0: 2161; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma 2162; CHECK-NEXT: vmslt.vx v0, v8, zero 2163; CHECK-NEXT: ret 2164 %head = insertelement <vscale x 8 x i32> poison, i32 0, i32 0 2165 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 2166 %vc = icmp slt <vscale x 8 x i32> %va, %splat 2167 ret <vscale x 8 x i1> %vc 2168} 2169 2170define <vscale x 8 x i1> @icmp_slt_vi_nxv8i32_3(<vscale x 8 x i32> %va) { 2171; CHECK-LABEL: icmp_slt_vi_nxv8i32_3: 2172; CHECK: # %bb.0: 2173; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma 2174; CHECK-NEXT: vmsle.vi v0, v8, 15 2175; CHECK-NEXT: ret 2176 %head = insertelement <vscale x 8 x i32> poison, i32 16, i32 0 2177 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 2178 %vc = icmp slt <vscale x 8 x i32> %va, %splat 2179 ret <vscale x 8 x i1> %vc 2180} 2181 2182define <vscale x 8 x i1> @icmp_sle_vv_nxv8i32(<vscale x 8 x i32> %va, <vscale x 8 x i32> %vb) { 2183; CHECK-LABEL: icmp_sle_vv_nxv8i32: 2184; CHECK: # %bb.0: 2185; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma 2186; CHECK-NEXT: vmsle.vv v0, v8, v12 2187; CHECK-NEXT: ret 2188 %vc = icmp sle <vscale x 8 x i32> %va, %vb 2189 ret <vscale x 8 x i1> %vc 2190} 2191 2192define <vscale x 8 x i1> @icmp_sle_vx_nxv8i32(<vscale x 8 x i32> %va, i32 %b) { 2193; CHECK-LABEL: icmp_sle_vx_nxv8i32: 2194; CHECK: # %bb.0: 2195; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma 2196; CHECK-NEXT: vmsle.vx v0, v8, a0 2197; CHECK-NEXT: ret 2198 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0 2199 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 2200 %vc = icmp sle <vscale x 8 x i32> %va, %splat 2201 ret <vscale x 8 x i1> %vc 2202} 2203 2204define <vscale x 8 x i1> @icmp_sle_xv_nxv8i32(<vscale x 8 x i32> %va, i32 %b) { 2205; CHECK-LABEL: icmp_sle_xv_nxv8i32: 2206; CHECK: # %bb.0: 2207; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma 2208; CHECK-NEXT: vmv.v.x v12, a0 2209; CHECK-NEXT: vmsle.vv v0, v12, v8 2210; CHECK-NEXT: ret 2211 %head = insertelement <vscale x 8 x i32> poison, i32 %b, i32 0 2212 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 2213 %vc = icmp sle <vscale x 8 x i32> %splat, %va 2214 ret <vscale x 8 x i1> %vc 2215} 2216 2217define <vscale x 8 x i1> @icmp_sle_vi_nxv8i32_0(<vscale x 8 x i32> %va) { 2218; CHECK-LABEL: icmp_sle_vi_nxv8i32_0: 2219; CHECK: # %bb.0: 2220; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma 2221; CHECK-NEXT: vmsle.vi v0, v8, 5 2222; CHECK-NEXT: ret 2223 %head = insertelement <vscale x 8 x i32> poison, i32 5, i32 0 2224 %splat = shufflevector <vscale x 8 x i32> %head, <vscale x 8 x i32> poison, <vscale x 8 x i32> zeroinitializer 2225 %vc = icmp sle <vscale x 8 x i32> %va, %splat 2226 ret <vscale x 8 x i1> %vc 2227} 2228 2229define <vscale x 8 x i1> @icmp_eq_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) { 2230; CHECK-LABEL: icmp_eq_vv_nxv8i64: 2231; CHECK: # %bb.0: 2232; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma 2233; CHECK-NEXT: vmseq.vv v0, v8, v16 2234; CHECK-NEXT: ret 2235 %vc = icmp eq <vscale x 8 x i64> %va, %vb 2236 ret <vscale x 8 x i1> %vc 2237} 2238 2239define <vscale x 8 x i1> @icmp_eq_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { 2240; RV32-LABEL: icmp_eq_vx_nxv8i64: 2241; RV32: # %bb.0: 2242; RV32-NEXT: addi sp, sp, -16 2243; RV32-NEXT: .cfi_def_cfa_offset 16 2244; RV32-NEXT: sw a1, 12(sp) 2245; RV32-NEXT: sw a0, 8(sp) 2246; RV32-NEXT: addi a0, sp, 8 2247; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma 2248; RV32-NEXT: vlse64.v v16, (a0), zero 2249; RV32-NEXT: vmseq.vv v0, v8, v16 2250; RV32-NEXT: addi sp, sp, 16 2251; RV32-NEXT: ret 2252; 2253; RV64-LABEL: icmp_eq_vx_nxv8i64: 2254; RV64: # %bb.0: 2255; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma 2256; RV64-NEXT: vmseq.vx v0, v8, a0 2257; RV64-NEXT: ret 2258 %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 2259 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 2260 %vc = icmp eq <vscale x 8 x i64> %va, %splat 2261 ret <vscale x 8 x i1> %vc 2262} 2263 2264define <vscale x 8 x i1> @icmp_eq_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { 2265; RV32-LABEL: icmp_eq_xv_nxv8i64: 2266; RV32: # %bb.0: 2267; RV32-NEXT: addi sp, sp, -16 2268; RV32-NEXT: .cfi_def_cfa_offset 16 2269; RV32-NEXT: sw a1, 12(sp) 2270; RV32-NEXT: sw a0, 8(sp) 2271; RV32-NEXT: addi a0, sp, 8 2272; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma 2273; RV32-NEXT: vlse64.v v16, (a0), zero 2274; RV32-NEXT: vmseq.vv v0, v16, v8 2275; RV32-NEXT: addi sp, sp, 16 2276; RV32-NEXT: ret 2277; 2278; RV64-LABEL: icmp_eq_xv_nxv8i64: 2279; RV64: # %bb.0: 2280; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma 2281; RV64-NEXT: vmseq.vx v0, v8, a0 2282; RV64-NEXT: ret 2283 %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 2284 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 2285 %vc = icmp eq <vscale x 8 x i64> %splat, %va 2286 ret <vscale x 8 x i1> %vc 2287} 2288 2289define <vscale x 8 x i1> @icmp_eq_vi_nxv8i64_0(<vscale x 8 x i64> %va) { 2290; CHECK-LABEL: icmp_eq_vi_nxv8i64_0: 2291; CHECK: # %bb.0: 2292; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma 2293; CHECK-NEXT: vmseq.vi v0, v8, 0 2294; CHECK-NEXT: ret 2295 %head = insertelement <vscale x 8 x i64> poison, i64 0, i32 0 2296 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 2297 %vc = icmp eq <vscale x 8 x i64> %va, %splat 2298 ret <vscale x 8 x i1> %vc 2299} 2300 2301define <vscale x 8 x i1> @icmp_eq_vi_nxv8i64_1(<vscale x 8 x i64> %va) { 2302; CHECK-LABEL: icmp_eq_vi_nxv8i64_1: 2303; CHECK: # %bb.0: 2304; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma 2305; CHECK-NEXT: vmseq.vi v0, v8, 5 2306; CHECK-NEXT: ret 2307 %head = insertelement <vscale x 8 x i64> poison, i64 5, i32 0 2308 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 2309 %vc = icmp eq <vscale x 8 x i64> %va, %splat 2310 ret <vscale x 8 x i1> %vc 2311} 2312 2313define <vscale x 8 x i1> @icmp_eq_iv_nxv8i64_1(<vscale x 8 x i64> %va) { 2314; CHECK-LABEL: icmp_eq_iv_nxv8i64_1: 2315; CHECK: # %bb.0: 2316; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma 2317; CHECK-NEXT: vmseq.vi v0, v8, 5 2318; CHECK-NEXT: ret 2319 %head = insertelement <vscale x 8 x i64> poison, i64 5, i32 0 2320 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 2321 %vc = icmp eq <vscale x 8 x i64> %splat, %va 2322 ret <vscale x 8 x i1> %vc 2323} 2324 2325define <vscale x 8 x i1> @icmp_ne_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) { 2326; CHECK-LABEL: icmp_ne_vv_nxv8i64: 2327; CHECK: # %bb.0: 2328; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma 2329; CHECK-NEXT: vmsne.vv v0, v8, v16 2330; CHECK-NEXT: ret 2331 %vc = icmp ne <vscale x 8 x i64> %va, %vb 2332 ret <vscale x 8 x i1> %vc 2333} 2334 2335define <vscale x 8 x i1> @icmp_ne_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { 2336; RV32-LABEL: icmp_ne_vx_nxv8i64: 2337; RV32: # %bb.0: 2338; RV32-NEXT: addi sp, sp, -16 2339; RV32-NEXT: .cfi_def_cfa_offset 16 2340; RV32-NEXT: sw a1, 12(sp) 2341; RV32-NEXT: sw a0, 8(sp) 2342; RV32-NEXT: addi a0, sp, 8 2343; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma 2344; RV32-NEXT: vlse64.v v16, (a0), zero 2345; RV32-NEXT: vmsne.vv v0, v8, v16 2346; RV32-NEXT: addi sp, sp, 16 2347; RV32-NEXT: ret 2348; 2349; RV64-LABEL: icmp_ne_vx_nxv8i64: 2350; RV64: # %bb.0: 2351; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma 2352; RV64-NEXT: vmsne.vx v0, v8, a0 2353; RV64-NEXT: ret 2354 %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 2355 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 2356 %vc = icmp ne <vscale x 8 x i64> %va, %splat 2357 ret <vscale x 8 x i1> %vc 2358} 2359 2360define <vscale x 8 x i1> @icmp_ne_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { 2361; RV32-LABEL: icmp_ne_xv_nxv8i64: 2362; RV32: # %bb.0: 2363; RV32-NEXT: addi sp, sp, -16 2364; RV32-NEXT: .cfi_def_cfa_offset 16 2365; RV32-NEXT: sw a1, 12(sp) 2366; RV32-NEXT: sw a0, 8(sp) 2367; RV32-NEXT: addi a0, sp, 8 2368; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma 2369; RV32-NEXT: vlse64.v v16, (a0), zero 2370; RV32-NEXT: vmsne.vv v0, v16, v8 2371; RV32-NEXT: addi sp, sp, 16 2372; RV32-NEXT: ret 2373; 2374; RV64-LABEL: icmp_ne_xv_nxv8i64: 2375; RV64: # %bb.0: 2376; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma 2377; RV64-NEXT: vmsne.vx v0, v8, a0 2378; RV64-NEXT: ret 2379 %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 2380 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 2381 %vc = icmp ne <vscale x 8 x i64> %splat, %va 2382 ret <vscale x 8 x i1> %vc 2383} 2384 2385define <vscale x 8 x i1> @icmp_ne_vi_nxv8i64_0(<vscale x 8 x i64> %va) { 2386; CHECK-LABEL: icmp_ne_vi_nxv8i64_0: 2387; CHECK: # %bb.0: 2388; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma 2389; CHECK-NEXT: vmsne.vi v0, v8, 5 2390; CHECK-NEXT: ret 2391 %head = insertelement <vscale x 8 x i64> poison, i64 5, i32 0 2392 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 2393 %vc = icmp ne <vscale x 8 x i64> %va, %splat 2394 ret <vscale x 8 x i1> %vc 2395} 2396 2397define <vscale x 8 x i1> @icmp_ugt_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) { 2398; CHECK-LABEL: icmp_ugt_vv_nxv8i64: 2399; CHECK: # %bb.0: 2400; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma 2401; CHECK-NEXT: vmsltu.vv v0, v16, v8 2402; CHECK-NEXT: ret 2403 %vc = icmp ugt <vscale x 8 x i64> %va, %vb 2404 ret <vscale x 8 x i1> %vc 2405} 2406 2407define <vscale x 8 x i1> @icmp_ugt_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { 2408; RV32-LABEL: icmp_ugt_vx_nxv8i64: 2409; RV32: # %bb.0: 2410; RV32-NEXT: addi sp, sp, -16 2411; RV32-NEXT: .cfi_def_cfa_offset 16 2412; RV32-NEXT: sw a1, 12(sp) 2413; RV32-NEXT: sw a0, 8(sp) 2414; RV32-NEXT: addi a0, sp, 8 2415; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma 2416; RV32-NEXT: vlse64.v v16, (a0), zero 2417; RV32-NEXT: vmsltu.vv v0, v16, v8 2418; RV32-NEXT: addi sp, sp, 16 2419; RV32-NEXT: ret 2420; 2421; RV64-LABEL: icmp_ugt_vx_nxv8i64: 2422; RV64: # %bb.0: 2423; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma 2424; RV64-NEXT: vmsgtu.vx v0, v8, a0 2425; RV64-NEXT: ret 2426 %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 2427 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 2428 %vc = icmp ugt <vscale x 8 x i64> %va, %splat 2429 ret <vscale x 8 x i1> %vc 2430} 2431 2432define <vscale x 8 x i1> @icmp_ugt_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { 2433; RV32-LABEL: icmp_ugt_xv_nxv8i64: 2434; RV32: # %bb.0: 2435; RV32-NEXT: addi sp, sp, -16 2436; RV32-NEXT: .cfi_def_cfa_offset 16 2437; RV32-NEXT: sw a1, 12(sp) 2438; RV32-NEXT: sw a0, 8(sp) 2439; RV32-NEXT: addi a0, sp, 8 2440; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma 2441; RV32-NEXT: vlse64.v v16, (a0), zero 2442; RV32-NEXT: vmsltu.vv v0, v8, v16 2443; RV32-NEXT: addi sp, sp, 16 2444; RV32-NEXT: ret 2445; 2446; RV64-LABEL: icmp_ugt_xv_nxv8i64: 2447; RV64: # %bb.0: 2448; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma 2449; RV64-NEXT: vmsltu.vx v0, v8, a0 2450; RV64-NEXT: ret 2451 %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 2452 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 2453 %vc = icmp ugt <vscale x 8 x i64> %splat, %va 2454 ret <vscale x 8 x i1> %vc 2455} 2456 2457define <vscale x 8 x i1> @icmp_ugt_vi_nxv8i64_0(<vscale x 8 x i64> %va) { 2458; CHECK-LABEL: icmp_ugt_vi_nxv8i64_0: 2459; CHECK: # %bb.0: 2460; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma 2461; CHECK-NEXT: vmsgtu.vi v0, v8, 5 2462; CHECK-NEXT: ret 2463 %head = insertelement <vscale x 8 x i64> poison, i64 5, i32 0 2464 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 2465 %vc = icmp ugt <vscale x 8 x i64> %va, %splat 2466 ret <vscale x 8 x i1> %vc 2467} 2468 2469define <vscale x 8 x i1> @icmp_uge_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) { 2470; CHECK-LABEL: icmp_uge_vv_nxv8i64: 2471; CHECK: # %bb.0: 2472; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma 2473; CHECK-NEXT: vmsleu.vv v0, v16, v8 2474; CHECK-NEXT: ret 2475 %vc = icmp uge <vscale x 8 x i64> %va, %vb 2476 ret <vscale x 8 x i1> %vc 2477} 2478 2479define <vscale x 8 x i1> @icmp_uge_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { 2480; RV32-LABEL: icmp_uge_vx_nxv8i64: 2481; RV32: # %bb.0: 2482; RV32-NEXT: addi sp, sp, -16 2483; RV32-NEXT: .cfi_def_cfa_offset 16 2484; RV32-NEXT: sw a1, 12(sp) 2485; RV32-NEXT: sw a0, 8(sp) 2486; RV32-NEXT: addi a0, sp, 8 2487; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma 2488; RV32-NEXT: vlse64.v v16, (a0), zero 2489; RV32-NEXT: vmsleu.vv v0, v16, v8 2490; RV32-NEXT: addi sp, sp, 16 2491; RV32-NEXT: ret 2492; 2493; RV64-LABEL: icmp_uge_vx_nxv8i64: 2494; RV64: # %bb.0: 2495; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma 2496; RV64-NEXT: vmv.v.x v16, a0 2497; RV64-NEXT: vmsleu.vv v0, v16, v8 2498; RV64-NEXT: ret 2499 %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 2500 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 2501 %vc = icmp uge <vscale x 8 x i64> %va, %splat 2502 ret <vscale x 8 x i1> %vc 2503} 2504 2505define <vscale x 8 x i1> @icmp_uge_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { 2506; RV32-LABEL: icmp_uge_xv_nxv8i64: 2507; RV32: # %bb.0: 2508; RV32-NEXT: addi sp, sp, -16 2509; RV32-NEXT: .cfi_def_cfa_offset 16 2510; RV32-NEXT: sw a1, 12(sp) 2511; RV32-NEXT: sw a0, 8(sp) 2512; RV32-NEXT: addi a0, sp, 8 2513; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma 2514; RV32-NEXT: vlse64.v v16, (a0), zero 2515; RV32-NEXT: vmsleu.vv v0, v8, v16 2516; RV32-NEXT: addi sp, sp, 16 2517; RV32-NEXT: ret 2518; 2519; RV64-LABEL: icmp_uge_xv_nxv8i64: 2520; RV64: # %bb.0: 2521; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma 2522; RV64-NEXT: vmsleu.vx v0, v8, a0 2523; RV64-NEXT: ret 2524 %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 2525 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 2526 %vc = icmp uge <vscale x 8 x i64> %splat, %va 2527 ret <vscale x 8 x i1> %vc 2528} 2529 2530define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_0(<vscale x 8 x i64> %va) { 2531; CHECK-LABEL: icmp_uge_vi_nxv8i64_0: 2532; CHECK: # %bb.0: 2533; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma 2534; CHECK-NEXT: vmv.v.i v16, -16 2535; CHECK-NEXT: vmsleu.vv v0, v16, v8 2536; CHECK-NEXT: ret 2537 %head = insertelement <vscale x 8 x i64> poison, i64 -16, i32 0 2538 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 2539 %vc = icmp uge <vscale x 8 x i64> %va, %splat 2540 ret <vscale x 8 x i1> %vc 2541} 2542 2543define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_1(<vscale x 8 x i64> %va) { 2544; CHECK-LABEL: icmp_uge_vi_nxv8i64_1: 2545; CHECK: # %bb.0: 2546; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma 2547; CHECK-NEXT: vmsgtu.vi v0, v8, 14 2548; CHECK-NEXT: ret 2549 %head = insertelement <vscale x 8 x i64> poison, i64 15, i32 0 2550 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 2551 %vc = icmp uge <vscale x 8 x i64> %va, %splat 2552 ret <vscale x 8 x i1> %vc 2553} 2554 2555define <vscale x 8 x i1> @icmp_uge_iv_nxv8i64_1(<vscale x 8 x i64> %va) { 2556; CHECK-LABEL: icmp_uge_iv_nxv8i64_1: 2557; CHECK: # %bb.0: 2558; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma 2559; CHECK-NEXT: vmsleu.vi v0, v8, 15 2560; CHECK-NEXT: ret 2561 %head = insertelement <vscale x 8 x i64> poison, i64 15, i32 0 2562 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 2563 %vc = icmp uge <vscale x 8 x i64> %splat, %va 2564 ret <vscale x 8 x i1> %vc 2565} 2566 2567define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_2(<vscale x 8 x i64> %va) { 2568; CHECK-LABEL: icmp_uge_vi_nxv8i64_2: 2569; CHECK: # %bb.0: 2570; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma 2571; CHECK-NEXT: vmset.m v0 2572; CHECK-NEXT: ret 2573 %head = insertelement <vscale x 8 x i64> poison, i64 0, i32 0 2574 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 2575 %vc = icmp uge <vscale x 8 x i64> %va, %splat 2576 ret <vscale x 8 x i1> %vc 2577} 2578 2579define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_3(<vscale x 8 x i64> %va) { 2580; CHECK-LABEL: icmp_uge_vi_nxv8i64_3: 2581; CHECK: # %bb.0: 2582; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma 2583; CHECK-NEXT: vmsgtu.vi v0, v8, 0 2584; CHECK-NEXT: ret 2585 %head = insertelement <vscale x 8 x i64> poison, i64 1, i32 0 2586 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 2587 %vc = icmp uge <vscale x 8 x i64> %va, %splat 2588 ret <vscale x 8 x i1> %vc 2589} 2590 2591define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_4(<vscale x 8 x i64> %va) { 2592; CHECK-LABEL: icmp_uge_vi_nxv8i64_4: 2593; CHECK: # %bb.0: 2594; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma 2595; CHECK-NEXT: vmsgtu.vi v0, v8, -16 2596; CHECK-NEXT: ret 2597 %head = insertelement <vscale x 8 x i64> poison, i64 -15, i32 0 2598 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 2599 %vc = icmp uge <vscale x 8 x i64> %va, %splat 2600 ret <vscale x 8 x i1> %vc 2601} 2602 2603define <vscale x 8 x i1> @icmp_uge_vi_nxv8i64_5(<vscale x 8 x i64> %va) { 2604; CHECK-LABEL: icmp_uge_vi_nxv8i64_5: 2605; CHECK: # %bb.0: 2606; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma 2607; CHECK-NEXT: vmsgtu.vi v0, v8, 15 2608; CHECK-NEXT: ret 2609 %head = insertelement <vscale x 8 x i64> poison, i64 16, i32 0 2610 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 2611 %vc = icmp uge <vscale x 8 x i64> %va, %splat 2612 ret <vscale x 8 x i1> %vc 2613} 2614 2615define <vscale x 8 x i1> @icmp_ult_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) { 2616; CHECK-LABEL: icmp_ult_vv_nxv8i64: 2617; CHECK: # %bb.0: 2618; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma 2619; CHECK-NEXT: vmsltu.vv v0, v8, v16 2620; CHECK-NEXT: ret 2621 %vc = icmp ult <vscale x 8 x i64> %va, %vb 2622 ret <vscale x 8 x i1> %vc 2623} 2624 2625define <vscale x 8 x i1> @icmp_ult_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { 2626; RV32-LABEL: icmp_ult_vx_nxv8i64: 2627; RV32: # %bb.0: 2628; RV32-NEXT: addi sp, sp, -16 2629; RV32-NEXT: .cfi_def_cfa_offset 16 2630; RV32-NEXT: sw a1, 12(sp) 2631; RV32-NEXT: sw a0, 8(sp) 2632; RV32-NEXT: addi a0, sp, 8 2633; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma 2634; RV32-NEXT: vlse64.v v16, (a0), zero 2635; RV32-NEXT: vmsltu.vv v0, v8, v16 2636; RV32-NEXT: addi sp, sp, 16 2637; RV32-NEXT: ret 2638; 2639; RV64-LABEL: icmp_ult_vx_nxv8i64: 2640; RV64: # %bb.0: 2641; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma 2642; RV64-NEXT: vmsltu.vx v0, v8, a0 2643; RV64-NEXT: ret 2644 %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 2645 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 2646 %vc = icmp ult <vscale x 8 x i64> %va, %splat 2647 ret <vscale x 8 x i1> %vc 2648} 2649 2650define <vscale x 8 x i1> @icmp_ult_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { 2651; RV32-LABEL: icmp_ult_xv_nxv8i64: 2652; RV32: # %bb.0: 2653; RV32-NEXT: addi sp, sp, -16 2654; RV32-NEXT: .cfi_def_cfa_offset 16 2655; RV32-NEXT: sw a1, 12(sp) 2656; RV32-NEXT: sw a0, 8(sp) 2657; RV32-NEXT: addi a0, sp, 8 2658; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma 2659; RV32-NEXT: vlse64.v v16, (a0), zero 2660; RV32-NEXT: vmsltu.vv v0, v16, v8 2661; RV32-NEXT: addi sp, sp, 16 2662; RV32-NEXT: ret 2663; 2664; RV64-LABEL: icmp_ult_xv_nxv8i64: 2665; RV64: # %bb.0: 2666; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma 2667; RV64-NEXT: vmsgtu.vx v0, v8, a0 2668; RV64-NEXT: ret 2669 %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 2670 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 2671 %vc = icmp ult <vscale x 8 x i64> %splat, %va 2672 ret <vscale x 8 x i1> %vc 2673} 2674 2675define <vscale x 8 x i1> @icmp_ult_vi_nxv8i64_0(<vscale x 8 x i64> %va) { 2676; CHECK-LABEL: icmp_ult_vi_nxv8i64_0: 2677; CHECK: # %bb.0: 2678; CHECK-NEXT: li a0, -16 2679; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma 2680; CHECK-NEXT: vmsltu.vx v0, v8, a0 2681; CHECK-NEXT: ret 2682 %head = insertelement <vscale x 8 x i64> poison, i64 -16, i32 0 2683 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 2684 %vc = icmp ult <vscale x 8 x i64> %va, %splat 2685 ret <vscale x 8 x i1> %vc 2686} 2687 2688define <vscale x 8 x i1> @icmp_ult_vi_nxv8i64_1(<vscale x 8 x i64> %va) { 2689; CHECK-LABEL: icmp_ult_vi_nxv8i64_1: 2690; CHECK: # %bb.0: 2691; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma 2692; CHECK-NEXT: vmsleu.vi v0, v8, -16 2693; CHECK-NEXT: ret 2694 %head = insertelement <vscale x 8 x i64> poison, i64 -15, i32 0 2695 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 2696 %vc = icmp ult <vscale x 8 x i64> %va, %splat 2697 ret <vscale x 8 x i1> %vc 2698} 2699 2700define <vscale x 8 x i1> @icmp_ult_iv_nxv8i64_1(<vscale x 8 x i64> %va) { 2701; CHECK-LABEL: icmp_ult_iv_nxv8i64_1: 2702; CHECK: # %bb.0: 2703; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma 2704; CHECK-NEXT: vmsgtu.vi v0, v8, -15 2705; CHECK-NEXT: ret 2706 %head = insertelement <vscale x 8 x i64> poison, i64 -15, i32 0 2707 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 2708 %vc = icmp ult <vscale x 8 x i64> %splat, %va 2709 ret <vscale x 8 x i1> %vc 2710} 2711 2712define <vscale x 8 x i1> @icmp_ult_vi_nxv8i64_2(<vscale x 8 x i64> %va) { 2713; CHECK-LABEL: icmp_ult_vi_nxv8i64_2: 2714; CHECK: # %bb.0: 2715; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma 2716; CHECK-NEXT: vmclr.m v0 2717; CHECK-NEXT: ret 2718 %head = insertelement <vscale x 8 x i64> poison, i64 0, i32 0 2719 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 2720 %vc = icmp ult <vscale x 8 x i64> %va, %splat 2721 ret <vscale x 8 x i1> %vc 2722} 2723 2724define <vscale x 8 x i1> @icmp_ult_vi_nxv8i64_3(<vscale x 8 x i64> %va) { 2725; CHECK-LABEL: icmp_ult_vi_nxv8i64_3: 2726; CHECK: # %bb.0: 2727; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma 2728; CHECK-NEXT: vmseq.vi v0, v8, 0 2729; CHECK-NEXT: ret 2730 %head = insertelement <vscale x 8 x i64> poison, i64 1, i32 0 2731 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 2732 %vc = icmp ult <vscale x 8 x i64> %va, %splat 2733 ret <vscale x 8 x i1> %vc 2734} 2735 2736define <vscale x 8 x i1> @icmp_ult_vi_nxv8i64_4(<vscale x 8 x i64> %va) { 2737; CHECK-LABEL: icmp_ult_vi_nxv8i64_4: 2738; CHECK: # %bb.0: 2739; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma 2740; CHECK-NEXT: vmsleu.vi v0, v8, 15 2741; CHECK-NEXT: ret 2742 %head = insertelement <vscale x 8 x i64> poison, i64 16, i32 0 2743 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 2744 %vc = icmp ult <vscale x 8 x i64> %va, %splat 2745 ret <vscale x 8 x i1> %vc 2746} 2747 2748define <vscale x 8 x i1> @icmp_ule_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) { 2749; CHECK-LABEL: icmp_ule_vv_nxv8i64: 2750; CHECK: # %bb.0: 2751; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma 2752; CHECK-NEXT: vmsleu.vv v0, v8, v16 2753; CHECK-NEXT: ret 2754 %vc = icmp ule <vscale x 8 x i64> %va, %vb 2755 ret <vscale x 8 x i1> %vc 2756} 2757 2758define <vscale x 8 x i1> @icmp_ule_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { 2759; RV32-LABEL: icmp_ule_vx_nxv8i64: 2760; RV32: # %bb.0: 2761; RV32-NEXT: addi sp, sp, -16 2762; RV32-NEXT: .cfi_def_cfa_offset 16 2763; RV32-NEXT: sw a1, 12(sp) 2764; RV32-NEXT: sw a0, 8(sp) 2765; RV32-NEXT: addi a0, sp, 8 2766; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma 2767; RV32-NEXT: vlse64.v v16, (a0), zero 2768; RV32-NEXT: vmsleu.vv v0, v8, v16 2769; RV32-NEXT: addi sp, sp, 16 2770; RV32-NEXT: ret 2771; 2772; RV64-LABEL: icmp_ule_vx_nxv8i64: 2773; RV64: # %bb.0: 2774; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma 2775; RV64-NEXT: vmsleu.vx v0, v8, a0 2776; RV64-NEXT: ret 2777 %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 2778 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 2779 %vc = icmp ule <vscale x 8 x i64> %va, %splat 2780 ret <vscale x 8 x i1> %vc 2781} 2782 2783define <vscale x 8 x i1> @icmp_ule_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { 2784; RV32-LABEL: icmp_ule_xv_nxv8i64: 2785; RV32: # %bb.0: 2786; RV32-NEXT: addi sp, sp, -16 2787; RV32-NEXT: .cfi_def_cfa_offset 16 2788; RV32-NEXT: sw a1, 12(sp) 2789; RV32-NEXT: sw a0, 8(sp) 2790; RV32-NEXT: addi a0, sp, 8 2791; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma 2792; RV32-NEXT: vlse64.v v16, (a0), zero 2793; RV32-NEXT: vmsleu.vv v0, v16, v8 2794; RV32-NEXT: addi sp, sp, 16 2795; RV32-NEXT: ret 2796; 2797; RV64-LABEL: icmp_ule_xv_nxv8i64: 2798; RV64: # %bb.0: 2799; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma 2800; RV64-NEXT: vmv.v.x v16, a0 2801; RV64-NEXT: vmsleu.vv v0, v16, v8 2802; RV64-NEXT: ret 2803 %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 2804 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 2805 %vc = icmp ule <vscale x 8 x i64> %splat, %va 2806 ret <vscale x 8 x i1> %vc 2807} 2808 2809define <vscale x 8 x i1> @icmp_ule_vi_nxv8i64_0(<vscale x 8 x i64> %va) { 2810; CHECK-LABEL: icmp_ule_vi_nxv8i64_0: 2811; CHECK: # %bb.0: 2812; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma 2813; CHECK-NEXT: vmsleu.vi v0, v8, 5 2814; CHECK-NEXT: ret 2815 %head = insertelement <vscale x 8 x i64> poison, i64 5, i32 0 2816 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 2817 %vc = icmp ule <vscale x 8 x i64> %va, %splat 2818 ret <vscale x 8 x i1> %vc 2819} 2820 2821define <vscale x 8 x i1> @icmp_sgt_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) { 2822; CHECK-LABEL: icmp_sgt_vv_nxv8i64: 2823; CHECK: # %bb.0: 2824; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma 2825; CHECK-NEXT: vmslt.vv v0, v16, v8 2826; CHECK-NEXT: ret 2827 %vc = icmp sgt <vscale x 8 x i64> %va, %vb 2828 ret <vscale x 8 x i1> %vc 2829} 2830 2831define <vscale x 8 x i1> @icmp_sgt_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { 2832; RV32-LABEL: icmp_sgt_vx_nxv8i64: 2833; RV32: # %bb.0: 2834; RV32-NEXT: addi sp, sp, -16 2835; RV32-NEXT: .cfi_def_cfa_offset 16 2836; RV32-NEXT: sw a1, 12(sp) 2837; RV32-NEXT: sw a0, 8(sp) 2838; RV32-NEXT: addi a0, sp, 8 2839; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma 2840; RV32-NEXT: vlse64.v v16, (a0), zero 2841; RV32-NEXT: vmslt.vv v0, v16, v8 2842; RV32-NEXT: addi sp, sp, 16 2843; RV32-NEXT: ret 2844; 2845; RV64-LABEL: icmp_sgt_vx_nxv8i64: 2846; RV64: # %bb.0: 2847; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma 2848; RV64-NEXT: vmsgt.vx v0, v8, a0 2849; RV64-NEXT: ret 2850 %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 2851 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 2852 %vc = icmp sgt <vscale x 8 x i64> %va, %splat 2853 ret <vscale x 8 x i1> %vc 2854} 2855 2856define <vscale x 8 x i1> @icmp_sgt_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { 2857; RV32-LABEL: icmp_sgt_xv_nxv8i64: 2858; RV32: # %bb.0: 2859; RV32-NEXT: addi sp, sp, -16 2860; RV32-NEXT: .cfi_def_cfa_offset 16 2861; RV32-NEXT: sw a1, 12(sp) 2862; RV32-NEXT: sw a0, 8(sp) 2863; RV32-NEXT: addi a0, sp, 8 2864; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma 2865; RV32-NEXT: vlse64.v v16, (a0), zero 2866; RV32-NEXT: vmslt.vv v0, v8, v16 2867; RV32-NEXT: addi sp, sp, 16 2868; RV32-NEXT: ret 2869; 2870; RV64-LABEL: icmp_sgt_xv_nxv8i64: 2871; RV64: # %bb.0: 2872; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma 2873; RV64-NEXT: vmslt.vx v0, v8, a0 2874; RV64-NEXT: ret 2875 %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 2876 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 2877 %vc = icmp sgt <vscale x 8 x i64> %splat, %va 2878 ret <vscale x 8 x i1> %vc 2879} 2880 2881define <vscale x 8 x i1> @icmp_sgt_vi_nxv8i64_0(<vscale x 8 x i64> %va) { 2882; CHECK-LABEL: icmp_sgt_vi_nxv8i64_0: 2883; CHECK: # %bb.0: 2884; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma 2885; CHECK-NEXT: vmsgt.vi v0, v8, 5 2886; CHECK-NEXT: ret 2887 %head = insertelement <vscale x 8 x i64> poison, i64 5, i32 0 2888 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 2889 %vc = icmp sgt <vscale x 8 x i64> %va, %splat 2890 ret <vscale x 8 x i1> %vc 2891} 2892 2893define <vscale x 8 x i1> @icmp_sge_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) { 2894; CHECK-LABEL: icmp_sge_vv_nxv8i64: 2895; CHECK: # %bb.0: 2896; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma 2897; CHECK-NEXT: vmsle.vv v0, v16, v8 2898; CHECK-NEXT: ret 2899 %vc = icmp sge <vscale x 8 x i64> %va, %vb 2900 ret <vscale x 8 x i1> %vc 2901} 2902 2903define <vscale x 8 x i1> @icmp_sge_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { 2904; RV32-LABEL: icmp_sge_vx_nxv8i64: 2905; RV32: # %bb.0: 2906; RV32-NEXT: addi sp, sp, -16 2907; RV32-NEXT: .cfi_def_cfa_offset 16 2908; RV32-NEXT: sw a1, 12(sp) 2909; RV32-NEXT: sw a0, 8(sp) 2910; RV32-NEXT: addi a0, sp, 8 2911; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma 2912; RV32-NEXT: vlse64.v v16, (a0), zero 2913; RV32-NEXT: vmsle.vv v0, v16, v8 2914; RV32-NEXT: addi sp, sp, 16 2915; RV32-NEXT: ret 2916; 2917; RV64-LABEL: icmp_sge_vx_nxv8i64: 2918; RV64: # %bb.0: 2919; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma 2920; RV64-NEXT: vmv.v.x v16, a0 2921; RV64-NEXT: vmsle.vv v0, v16, v8 2922; RV64-NEXT: ret 2923 %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 2924 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 2925 %vc = icmp sge <vscale x 8 x i64> %va, %splat 2926 ret <vscale x 8 x i1> %vc 2927} 2928 2929define <vscale x 8 x i1> @icmp_sge_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { 2930; RV32-LABEL: icmp_sge_xv_nxv8i64: 2931; RV32: # %bb.0: 2932; RV32-NEXT: addi sp, sp, -16 2933; RV32-NEXT: .cfi_def_cfa_offset 16 2934; RV32-NEXT: sw a1, 12(sp) 2935; RV32-NEXT: sw a0, 8(sp) 2936; RV32-NEXT: addi a0, sp, 8 2937; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma 2938; RV32-NEXT: vlse64.v v16, (a0), zero 2939; RV32-NEXT: vmsle.vv v0, v8, v16 2940; RV32-NEXT: addi sp, sp, 16 2941; RV32-NEXT: ret 2942; 2943; RV64-LABEL: icmp_sge_xv_nxv8i64: 2944; RV64: # %bb.0: 2945; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma 2946; RV64-NEXT: vmsle.vx v0, v8, a0 2947; RV64-NEXT: ret 2948 %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 2949 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 2950 %vc = icmp sge <vscale x 8 x i64> %splat, %va 2951 ret <vscale x 8 x i1> %vc 2952} 2953 2954define <vscale x 8 x i1> @icmp_sge_vi_nxv8i64_0(<vscale x 8 x i64> %va) { 2955; CHECK-LABEL: icmp_sge_vi_nxv8i64_0: 2956; CHECK: # %bb.0: 2957; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma 2958; CHECK-NEXT: vmv.v.i v16, -16 2959; CHECK-NEXT: vmsle.vv v0, v16, v8 2960; CHECK-NEXT: ret 2961 %head = insertelement <vscale x 8 x i64> poison, i64 -16, i32 0 2962 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 2963 %vc = icmp sge <vscale x 8 x i64> %va, %splat 2964 ret <vscale x 8 x i1> %vc 2965} 2966 2967define <vscale x 8 x i1> @icmp_sge_vi_nxv8i64_1(<vscale x 8 x i64> %va) { 2968; CHECK-LABEL: icmp_sge_vi_nxv8i64_1: 2969; CHECK: # %bb.0: 2970; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma 2971; CHECK-NEXT: vmsgt.vi v0, v8, -16 2972; CHECK-NEXT: ret 2973 %head = insertelement <vscale x 8 x i64> poison, i64 -15, i32 0 2974 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 2975 %vc = icmp sge <vscale x 8 x i64> %va, %splat 2976 ret <vscale x 8 x i1> %vc 2977} 2978 2979define <vscale x 8 x i1> @icmp_sge_iv_nxv8i64_1(<vscale x 8 x i64> %va) { 2980; CHECK-LABEL: icmp_sge_iv_nxv8i64_1: 2981; CHECK: # %bb.0: 2982; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma 2983; CHECK-NEXT: vmsle.vi v0, v8, -15 2984; CHECK-NEXT: ret 2985 %head = insertelement <vscale x 8 x i64> poison, i64 -15, i32 0 2986 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 2987 %vc = icmp sge <vscale x 8 x i64> %splat, %va 2988 ret <vscale x 8 x i1> %vc 2989} 2990 2991define <vscale x 8 x i1> @icmp_sge_vi_nxv8i64_2(<vscale x 8 x i64> %va) { 2992; CHECK-LABEL: icmp_sge_vi_nxv8i64_2: 2993; CHECK: # %bb.0: 2994; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma 2995; CHECK-NEXT: vmsgt.vi v0, v8, -1 2996; CHECK-NEXT: ret 2997 %head = insertelement <vscale x 8 x i64> poison, i64 0, i32 0 2998 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 2999 %vc = icmp sge <vscale x 8 x i64> %va, %splat 3000 ret <vscale x 8 x i1> %vc 3001} 3002 3003define <vscale x 8 x i1> @icmp_sge_vi_nxv8i64_3(<vscale x 8 x i64> %va) { 3004; CHECK-LABEL: icmp_sge_vi_nxv8i64_3: 3005; CHECK: # %bb.0: 3006; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma 3007; CHECK-NEXT: vmsgt.vi v0, v8, 15 3008; CHECK-NEXT: ret 3009 %head = insertelement <vscale x 8 x i64> poison, i64 16, i32 0 3010 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 3011 %vc = icmp sge <vscale x 8 x i64> %va, %splat 3012 ret <vscale x 8 x i1> %vc 3013} 3014 3015define <vscale x 8 x i1> @icmp_slt_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) { 3016; CHECK-LABEL: icmp_slt_vv_nxv8i64: 3017; CHECK: # %bb.0: 3018; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma 3019; CHECK-NEXT: vmslt.vv v0, v8, v16 3020; CHECK-NEXT: ret 3021 %vc = icmp slt <vscale x 8 x i64> %va, %vb 3022 ret <vscale x 8 x i1> %vc 3023} 3024 3025define <vscale x 8 x i1> @icmp_slt_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { 3026; RV32-LABEL: icmp_slt_vx_nxv8i64: 3027; RV32: # %bb.0: 3028; RV32-NEXT: addi sp, sp, -16 3029; RV32-NEXT: .cfi_def_cfa_offset 16 3030; RV32-NEXT: sw a1, 12(sp) 3031; RV32-NEXT: sw a0, 8(sp) 3032; RV32-NEXT: addi a0, sp, 8 3033; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma 3034; RV32-NEXT: vlse64.v v16, (a0), zero 3035; RV32-NEXT: vmslt.vv v0, v8, v16 3036; RV32-NEXT: addi sp, sp, 16 3037; RV32-NEXT: ret 3038; 3039; RV64-LABEL: icmp_slt_vx_nxv8i64: 3040; RV64: # %bb.0: 3041; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma 3042; RV64-NEXT: vmslt.vx v0, v8, a0 3043; RV64-NEXT: ret 3044 %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 3045 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 3046 %vc = icmp slt <vscale x 8 x i64> %va, %splat 3047 ret <vscale x 8 x i1> %vc 3048} 3049 3050define <vscale x 8 x i1> @icmp_slt_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { 3051; RV32-LABEL: icmp_slt_xv_nxv8i64: 3052; RV32: # %bb.0: 3053; RV32-NEXT: addi sp, sp, -16 3054; RV32-NEXT: .cfi_def_cfa_offset 16 3055; RV32-NEXT: sw a1, 12(sp) 3056; RV32-NEXT: sw a0, 8(sp) 3057; RV32-NEXT: addi a0, sp, 8 3058; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma 3059; RV32-NEXT: vlse64.v v16, (a0), zero 3060; RV32-NEXT: vmslt.vv v0, v16, v8 3061; RV32-NEXT: addi sp, sp, 16 3062; RV32-NEXT: ret 3063; 3064; RV64-LABEL: icmp_slt_xv_nxv8i64: 3065; RV64: # %bb.0: 3066; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma 3067; RV64-NEXT: vmsgt.vx v0, v8, a0 3068; RV64-NEXT: ret 3069 %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 3070 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 3071 %vc = icmp slt <vscale x 8 x i64> %splat, %va 3072 ret <vscale x 8 x i1> %vc 3073} 3074 3075define <vscale x 8 x i1> @icmp_slt_vi_nxv8i64_0(<vscale x 8 x i64> %va) { 3076; CHECK-LABEL: icmp_slt_vi_nxv8i64_0: 3077; CHECK: # %bb.0: 3078; CHECK-NEXT: li a0, -16 3079; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma 3080; CHECK-NEXT: vmslt.vx v0, v8, a0 3081; CHECK-NEXT: ret 3082 %head = insertelement <vscale x 8 x i64> poison, i64 -16, i32 0 3083 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 3084 %vc = icmp slt <vscale x 8 x i64> %va, %splat 3085 ret <vscale x 8 x i1> %vc 3086} 3087 3088define <vscale x 8 x i1> @icmp_slt_vi_nxv8i64_1(<vscale x 8 x i64> %va) { 3089; CHECK-LABEL: icmp_slt_vi_nxv8i64_1: 3090; CHECK: # %bb.0: 3091; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma 3092; CHECK-NEXT: vmsle.vi v0, v8, -16 3093; CHECK-NEXT: ret 3094 %head = insertelement <vscale x 8 x i64> poison, i64 -15, i32 0 3095 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 3096 %vc = icmp slt <vscale x 8 x i64> %va, %splat 3097 ret <vscale x 8 x i1> %vc 3098} 3099 3100define <vscale x 8 x i1> @icmp_slt_iv_nxv8i64_1(<vscale x 8 x i64> %va) { 3101; CHECK-LABEL: icmp_slt_iv_nxv8i64_1: 3102; CHECK: # %bb.0: 3103; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma 3104; CHECK-NEXT: vmsgt.vi v0, v8, -15 3105; CHECK-NEXT: ret 3106 %head = insertelement <vscale x 8 x i64> poison, i64 -15, i32 0 3107 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 3108 %vc = icmp slt <vscale x 8 x i64> %splat, %va 3109 ret <vscale x 8 x i1> %vc 3110} 3111 3112define <vscale x 8 x i1> @icmp_slt_vi_nxv8i64_2(<vscale x 8 x i64> %va) { 3113; CHECK-LABEL: icmp_slt_vi_nxv8i64_2: 3114; CHECK: # %bb.0: 3115; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma 3116; CHECK-NEXT: vmslt.vx v0, v8, zero 3117; CHECK-NEXT: ret 3118 %head = insertelement <vscale x 8 x i64> poison, i64 0, i32 0 3119 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 3120 %vc = icmp slt <vscale x 8 x i64> %va, %splat 3121 ret <vscale x 8 x i1> %vc 3122} 3123 3124define <vscale x 8 x i1> @icmp_slt_vi_nxv8i64_3(<vscale x 8 x i64> %va) { 3125; CHECK-LABEL: icmp_slt_vi_nxv8i64_3: 3126; CHECK: # %bb.0: 3127; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma 3128; CHECK-NEXT: vmsle.vi v0, v8, 15 3129; CHECK-NEXT: ret 3130 %head = insertelement <vscale x 8 x i64> poison, i64 16, i32 0 3131 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 3132 %vc = icmp slt <vscale x 8 x i64> %va, %splat 3133 ret <vscale x 8 x i1> %vc 3134} 3135 3136define <vscale x 8 x i1> @icmp_sle_vv_nxv8i64(<vscale x 8 x i64> %va, <vscale x 8 x i64> %vb) { 3137; CHECK-LABEL: icmp_sle_vv_nxv8i64: 3138; CHECK: # %bb.0: 3139; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma 3140; CHECK-NEXT: vmsle.vv v0, v8, v16 3141; CHECK-NEXT: ret 3142 %vc = icmp sle <vscale x 8 x i64> %va, %vb 3143 ret <vscale x 8 x i1> %vc 3144} 3145 3146define <vscale x 8 x i1> @icmp_sle_vx_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { 3147; RV32-LABEL: icmp_sle_vx_nxv8i64: 3148; RV32: # %bb.0: 3149; RV32-NEXT: addi sp, sp, -16 3150; RV32-NEXT: .cfi_def_cfa_offset 16 3151; RV32-NEXT: sw a1, 12(sp) 3152; RV32-NEXT: sw a0, 8(sp) 3153; RV32-NEXT: addi a0, sp, 8 3154; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma 3155; RV32-NEXT: vlse64.v v16, (a0), zero 3156; RV32-NEXT: vmsle.vv v0, v8, v16 3157; RV32-NEXT: addi sp, sp, 16 3158; RV32-NEXT: ret 3159; 3160; RV64-LABEL: icmp_sle_vx_nxv8i64: 3161; RV64: # %bb.0: 3162; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma 3163; RV64-NEXT: vmsle.vx v0, v8, a0 3164; RV64-NEXT: ret 3165 %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 3166 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 3167 %vc = icmp sle <vscale x 8 x i64> %va, %splat 3168 ret <vscale x 8 x i1> %vc 3169} 3170 3171define <vscale x 8 x i1> @icmp_sle_xv_nxv8i64(<vscale x 8 x i64> %va, i64 %b) { 3172; RV32-LABEL: icmp_sle_xv_nxv8i64: 3173; RV32: # %bb.0: 3174; RV32-NEXT: addi sp, sp, -16 3175; RV32-NEXT: .cfi_def_cfa_offset 16 3176; RV32-NEXT: sw a1, 12(sp) 3177; RV32-NEXT: sw a0, 8(sp) 3178; RV32-NEXT: addi a0, sp, 8 3179; RV32-NEXT: vsetvli a1, zero, e64, m8, ta, ma 3180; RV32-NEXT: vlse64.v v16, (a0), zero 3181; RV32-NEXT: vmsle.vv v0, v16, v8 3182; RV32-NEXT: addi sp, sp, 16 3183; RV32-NEXT: ret 3184; 3185; RV64-LABEL: icmp_sle_xv_nxv8i64: 3186; RV64: # %bb.0: 3187; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma 3188; RV64-NEXT: vmv.v.x v16, a0 3189; RV64-NEXT: vmsle.vv v0, v16, v8 3190; RV64-NEXT: ret 3191 %head = insertelement <vscale x 8 x i64> poison, i64 %b, i32 0 3192 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 3193 %vc = icmp sle <vscale x 8 x i64> %splat, %va 3194 ret <vscale x 8 x i1> %vc 3195} 3196 3197define <vscale x 8 x i1> @icmp_sle_vi_nxv8i64_0(<vscale x 8 x i64> %va) { 3198; CHECK-LABEL: icmp_sle_vi_nxv8i64_0: 3199; CHECK: # %bb.0: 3200; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma 3201; CHECK-NEXT: vmsle.vi v0, v8, 5 3202; CHECK-NEXT: ret 3203 %head = insertelement <vscale x 8 x i64> poison, i64 5, i32 0 3204 %splat = shufflevector <vscale x 8 x i64> %head, <vscale x 8 x i64> poison, <vscale x 8 x i32> zeroinitializer 3205 %vc = icmp sle <vscale x 8 x i64> %va, %splat 3206 ret <vscale x 8 x i1> %vc 3207} 3208 3209; Check a setcc with two constant splats, which would previously get stuck in 3210; an infinite loop. DAGCombine isn't clever enough to constant-fold 3211; splat_vectors but could continuously swap the operands, trying to put the 3212; splat on the RHS. 3213define <vscale x 8 x i1> @icmp_eq_ii_nxv8i8() { 3214; CHECK-LABEL: icmp_eq_ii_nxv8i8: 3215; CHECK: # %bb.0: 3216; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma 3217; CHECK-NEXT: vmclr.m v0 3218; CHECK-NEXT: ret 3219 %heada = insertelement <vscale x 8 x i8> poison, i8 5, i32 0 3220 %splata = shufflevector <vscale x 8 x i8> %heada, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 3221 %headb = insertelement <vscale x 8 x i8> poison, i8 2, i32 0 3222 %splatb = shufflevector <vscale x 8 x i8> %headb, <vscale x 8 x i8> poison, <vscale x 8 x i32> zeroinitializer 3223 %vc = icmp eq <vscale x 8 x i8> %splata, %splatb 3224 ret <vscale x 8 x i1> %vc 3225} 3226 3227; This icmp/setcc is split and so we find a scalable-vector mask CONCAT_VECTOR 3228; node. Ensure we correctly (custom) lower this. 3229define <vscale x 16 x i1> @icmp_eq_vi_nx16i64(<vscale x 16 x i64> %va) { 3230; CHECK-LABEL: icmp_eq_vi_nx16i64: 3231; CHECK: # %bb.0: 3232; CHECK-NEXT: csrr a0, vlenb 3233; CHECK-NEXT: srli a0, a0, 3 3234; CHECK-NEXT: add a1, a0, a0 3235; CHECK-NEXT: vsetvli a2, zero, e64, m8, ta, ma 3236; CHECK-NEXT: vmseq.vi v24, v16, 0 3237; CHECK-NEXT: vmseq.vi v0, v8, 0 3238; CHECK-NEXT: vsetvli zero, a1, e8, mf4, tu, ma 3239; CHECK-NEXT: vslideup.vx v0, v24, a0 3240; CHECK-NEXT: ret 3241 %vc = icmp eq <vscale x 16 x i64> %va, zeroinitializer 3242 ret <vscale x 16 x i1> %vc 3243} 3244