1; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5 2; RUN: llc < %s -mtriple=riscv64 -mattr=+v -stop-after=finalize-isel | FileCheck %s 3 4define void @vslidedown() { 5 ; CHECK-LABEL: name: vslidedown 6 ; CHECK: bb.0.entry: 7 ; CHECK-NEXT: [[ADDI:%[0-9]+]]:gpr = ADDI %stack.0.v, 0 8 ; CHECK-NEXT: [[PseudoVLE8_V_M8_:%[0-9]+]]:vrm8 = PseudoVLE8_V_M8 $noreg, killed [[ADDI]], -1, 3 /* e8 */, 3 /* ta, ma */ :: (load (<vscale x 1 x s512>) from %ir.v, align 1) 9 ; CHECK-NEXT: [[ADDI1:%[0-9]+]]:gpr = ADDI %stack.1, 0 10 ; CHECK-NEXT: PseudoVSE8_V_M8 killed [[PseudoVLE8_V_M8_]], killed [[ADDI1]], -1, 3 /* e8 */ :: (store (<vscale x 1 x s512>) into %stack.1) 11 ; CHECK-NEXT: INLINEASM &"vadd.vv $0, $0, $0", 25 /* sideeffect mayload maystore attdialect */, 262166 /* mem:m */, %stack.0.v, 0, 262166 /* mem:m */, %stack.1, 0 12 ; CHECK-NEXT: PseudoRET 13entry: 14 %v = alloca <vscale x 64 x i8>, align 1 15 %0 = load <vscale x 64 x i8>, ptr %v, align 1 16 call void asm sideeffect "vadd.vv $0, $0, $0", "=*imr,imr"(ptr elementtype(<vscale x 64 x i8>) %v, <vscale x 64 x i8> %0) 17 ret void 18} 19