143927542SJim Lin; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 2*26766a00SCraig Topper; RUN: llc -mtriple=riscv32 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK 3*26766a00SCraig Topper; RUN: llc -mtriple=riscv64 -mattr=+m,+v -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK 443927542SJim Lin 543927542SJim Lindefine <8 x i8> @v8i8_from_v16xi8_low(<16 x i8> %a) nounwind { 643927542SJim Lin; CHECK-LABEL: v8i8_from_v16xi8_low: 743927542SJim Lin; CHECK: # %bb.0: 843927542SJim Lin; CHECK-NEXT: ret 943927542SJim Lin %ret = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7> 1043927542SJim Lin ret <8 x i8> %ret 1143927542SJim Lin} 1243927542SJim Lin 1343927542SJim Lindefine <8 x i8> @v8i8_from_v16xi8_high(<16 x i8> %a) nounwind { 1443927542SJim Lin; CHECK-LABEL: v8i8_from_v16xi8_high: 1543927542SJim Lin; CHECK: # %bb.0: 1643927542SJim Lin; CHECK-NEXT: vsetivli zero, 8, e8, m1, ta, ma 1743927542SJim Lin; CHECK-NEXT: vslidedown.vi v8, v8, 8 1843927542SJim Lin; CHECK-NEXT: ret 1943927542SJim Lin %ret = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 2043927542SJim Lin ret <8 x i8> %ret 2143927542SJim Lin} 2243927542SJim Lin 2343927542SJim Lindefine <8 x i8> @v8i8_from_v16xi8_mid(<16 x i8> %a) nounwind { 2443927542SJim Lin; CHECK-LABEL: v8i8_from_v16xi8_mid: 2543927542SJim Lin; CHECK: # %bb.0: 2643927542SJim Lin; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma 2743927542SJim Lin; CHECK-NEXT: vslidedown.vi v8, v8, 5 2843927542SJim Lin; CHECK-NEXT: ret 2943927542SJim Lin %ret = shufflevector <16 x i8> %a, <16 x i8> undef, <8 x i32> <i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12> 3043927542SJim Lin ret <8 x i8> %ret 3143927542SJim Lin} 3243927542SJim Lin 3343927542SJim Lindefine <4 x i8> @v4i8_from_v16xi8_high(<16 x i8> %a) nounwind { 3443927542SJim Lin; CHECK-LABEL: v4i8_from_v16xi8_high: 3543927542SJim Lin; CHECK: # %bb.0: 3643927542SJim Lin; CHECK-NEXT: vsetivli zero, 4, e8, m1, ta, ma 3743927542SJim Lin; CHECK-NEXT: vslidedown.vi v8, v8, 8 3843927542SJim Lin; CHECK-NEXT: ret 3943927542SJim Lin %ret = shufflevector <16 x i8> %a, <16 x i8> undef, <4 x i32> <i32 8, i32 9, i32 10, i32 11> 4043927542SJim Lin ret <4 x i8> %ret 4143927542SJim Lin} 4243927542SJim Lin 4343927542SJim Lindefine <4 x i16> @v4i16_from_v8i16_high(<8 x i16> %a) nounwind { 4443927542SJim Lin; CHECK-LABEL: v4i16_from_v8i16_high: 4543927542SJim Lin; CHECK: # %bb.0: 4643927542SJim Lin; CHECK-NEXT: vsetivli zero, 4, e16, m1, ta, ma 4743927542SJim Lin; CHECK-NEXT: vslidedown.vi v8, v8, 4 4843927542SJim Lin; CHECK-NEXT: ret 4943927542SJim Lin %ret = shufflevector <8 x i16> %a, <8 x i16> undef, <4 x i32> <i32 4, i32 5, i32 6, i32 7> 5043927542SJim Lin ret <4 x i16> %ret 5143927542SJim Lin} 5243927542SJim Lin 5343927542SJim Lin 5443927542SJim Lindefine <8 x i32> @v8i32_from_v16xi32_high(<16 x i32> %a) nounwind { 5543927542SJim Lin; CHECK-LABEL: v8i32_from_v16xi32_high: 5643927542SJim Lin; CHECK: # %bb.0: 5743927542SJim Lin; CHECK-NEXT: vsetivli zero, 8, e32, m4, ta, ma 5843927542SJim Lin; CHECK-NEXT: vslidedown.vi v8, v8, 8 5943927542SJim Lin; CHECK-NEXT: ret 6043927542SJim Lin %ret = shufflevector <16 x i32> %a, <16 x i32> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 6143927542SJim Lin ret <8 x i32> %ret 6243927542SJim Lin} 6343927542SJim Lin 6443927542SJim Lin 6543927542SJim Lindefine <8 x i64> @v8i64_from_v16xi64_high(<16 x i64> %a) nounwind { 6643927542SJim Lin; CHECK-LABEL: v8i64_from_v16xi64_high: 6743927542SJim Lin; CHECK: # %bb.0: 6843927542SJim Lin; CHECK-NEXT: vsetivli zero, 8, e64, m8, ta, ma 6943927542SJim Lin; CHECK-NEXT: vslidedown.vi v8, v8, 8 7043927542SJim Lin; CHECK-NEXT: ret 7143927542SJim Lin %ret = shufflevector <16 x i64> %a, <16 x i64> undef, <8 x i32> <i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15> 7243927542SJim Lin ret <8 x i64> %ret 7343927542SJim Lin} 74