1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 2; RUN: llc < %s -O3 -mtriple=riscv64 -mattr=+v | FileCheck %s 3 4; TODO: The case below demonstrates a regression in cross block CSE of vector 5; instructions with undefined passthru operands. The second vadd.vv should be 6; removed. 7define void @foo(<vscale x 2 x i32> %x, <vscale x 2 x i32> %y, ptr %p1, ptr %p2, i1 zeroext %cond) { 8; CHECK-LABEL: foo: 9; CHECK: # %bb.0: 10; CHECK-NEXT: vsetvli a3, zero, e32, m1, ta, ma 11; CHECK-NEXT: vadd.vv v10, v8, v9 12; CHECK-NEXT: vs1r.v v10, (a0) 13; CHECK-NEXT: bnez a2, .LBB0_2 14; CHECK-NEXT: # %bb.1: # %falsebb 15; CHECK-NEXT: vadd.vv v8, v8, v9 16; CHECK-NEXT: vs1r.v v8, (a1) 17; CHECK-NEXT: .LBB0_2: # %mergebb 18; CHECK-NEXT: ret 19 %a = add <vscale x 2 x i32> %x, %y 20 store <vscale x 2 x i32> %a, ptr %p1 21 br i1 %cond, label %mergebb, label %falsebb 22 23falsebb: 24 %b = add <vscale x 2 x i32> %x, %y 25 store <vscale x 2 x i32> %b, ptr %p2 26 br label %mergebb 27 28mergebb: 29 ret void 30} 31