xref: /llvm-project/llvm/test/CodeGen/RISCV/rvv/access-fixed-objects-by-rvv.ll (revision ab393cee9dffdb225b94badcb9c21f80b156b74b) 
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv64 -mattr=+m,+v -O2 < %s \
3; RUN:   | FileCheck %s -check-prefix=RV64IV
4
5define <vscale x 1 x i64> @access_fixed_object(ptr %val) {
6; RV64IV-LABEL: access_fixed_object:
7; RV64IV:       # %bb.0:
8; RV64IV-NEXT:    addi sp, sp, -528
9; RV64IV-NEXT:    .cfi_def_cfa_offset 528
10; RV64IV-NEXT:    addi a1, sp, 8
11; RV64IV-NEXT:    vl1re64.v v8, (a1)
12; RV64IV-NEXT:    ld a1, 520(sp)
13; RV64IV-NEXT:    sd a1, 0(a0)
14; RV64IV-NEXT:    addi sp, sp, 528
15; RV64IV-NEXT:    ret
16  %local = alloca i64
17  %array = alloca [64 x i64]
18  %v = load <vscale x 1 x i64>, ptr %array
19  %len = load i64, ptr %local
20  store i64 %len, ptr %val
21  ret <vscale x 1 x i64> %v
22}
23
24declare <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64(
25  <vscale x 1 x i64>,
26  <vscale x 1 x i64>,
27  <vscale x 1 x i64>,
28  i64);
29
30define <vscale x 1 x i64> @access_fixed_and_vector_objects(ptr %val) {
31; RV64IV-LABEL: access_fixed_and_vector_objects:
32; RV64IV:       # %bb.0:
33; RV64IV-NEXT:    addi sp, sp, -528
34; RV64IV-NEXT:    .cfi_def_cfa_offset 528
35; RV64IV-NEXT:    csrr a0, vlenb
36; RV64IV-NEXT:    sub sp, sp, a0
37; RV64IV-NEXT:    .cfi_escape 0x0f, 0x0e, 0x72, 0x00, 0x11, 0x90, 0x04, 0x22, 0x11, 0x01, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 528 + 1 * vlenb
38; RV64IV-NEXT:    addi a0, sp, 8
39; RV64IV-NEXT:    vl1re64.v v8, (a0)
40; RV64IV-NEXT:    addi a0, sp, 528
41; RV64IV-NEXT:    vl1re64.v v9, (a0)
42; RV64IV-NEXT:    ld a0, 520(sp)
43; RV64IV-NEXT:    vsetvli zero, a0, e64, m1, ta, ma
44; RV64IV-NEXT:    vadd.vv v8, v8, v9
45; RV64IV-NEXT:    csrr a0, vlenb
46; RV64IV-NEXT:    add sp, sp, a0
47; RV64IV-NEXT:    addi sp, sp, 528
48; RV64IV-NEXT:    ret
49  %local = alloca i64
50  %vector = alloca <vscale x 1 x i64>
51  %array = alloca [64 x i64]
52  %v1 = load <vscale x 1 x i64>, ptr %array
53  %v2 = load <vscale x 1 x i64>, ptr %vector
54  %len = load i64, ptr %local
55
56  %a = call <vscale x 1 x i64> @llvm.riscv.vadd.nxv1i64.nxv1i64(
57    <vscale x 1 x i64> undef,
58    <vscale x 1 x i64> %v1,
59    <vscale x 1 x i64> %v2,
60    i64 %len)
61
62  ret <vscale x 1 x i64> %a
63}
64